psycho.c revision 1.85
1 /* $NetBSD: psycho.c,v 1.85 2008/04/05 13:40:05 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Eduardo E. Horvath 5 * Copyright (c) 1999, 2000 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.85 2008/04/05 13:40:05 cegger Exp $"); 34 35 #include "opt_ddb.h" 36 37 /* 38 * Support for `psycho' and `psycho+' UPA to PCI bridge and 39 * UltraSPARC IIi and IIe `sabre' PCI controllers. 40 */ 41 42 #ifdef DEBUG 43 #define PDB_PROM 0x01 44 #define PDB_BUSMAP 0x02 45 #define PDB_INTR 0x04 46 int psycho_debug = 0x0; 47 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 48 #else 49 #define DPRINTF(l, s) 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/device.h> 54 #include <sys/errno.h> 55 #include <sys/extent.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 #include <sys/reboot.h> 60 61 #include <uvm/uvm.h> 62 63 #define _SPARC_BUS_DMA_PRIVATE 64 #include <machine/bus.h> 65 #include <machine/autoconf.h> 66 #include <machine/psl.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/sysmon/sysmon_taskq.h> 71 72 #include <sparc64/dev/iommureg.h> 73 #include <sparc64/dev/iommuvar.h> 74 #include <sparc64/dev/psychoreg.h> 75 #include <sparc64/dev/psychovar.h> 76 #include <sparc64/sparc64/cache.h> 77 78 #include "ioconf.h" 79 80 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 81 pci_chipset_tag_t); 82 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 83 const char *); 84 static void psycho_get_bus_range(int, int *); 85 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 86 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 87 uint64_t *); 88 89 /* Interrupt handlers */ 90 static int psycho_ue(void *); 91 static int psycho_ce(void *); 92 static int psycho_bus_a(void *); 93 static int psycho_bus_b(void *); 94 static int psycho_powerfail(void *); 95 static int psycho_wakeup(void *); 96 97 98 /* IOMMU support */ 99 static void psycho_iommu_init(struct psycho_softc *, int); 100 101 /* 102 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 103 * of the bus DMA support is provided by the iommu dvma controller. 104 */ 105 static int get_childspace(int); 106 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 107 108 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 109 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 110 vaddr_t, bus_space_handle_t *); 111 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 112 void *, void(*)(void)); 113 114 static int psycho_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t, 115 struct proc *, int); 116 static void psycho_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 117 static int psycho_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, 118 bus_dma_segment_t *, int, bus_size_t, int); 119 static void psycho_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 120 bus_size_t, int); 121 int psycho_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 122 bus_dma_segment_t *, int, int *, int); 123 void psycho_dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int); 124 int psycho_dmamem_map(bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 125 void **, int); 126 void psycho_dmamem_unmap(bus_dma_tag_t, void *, size_t); 127 128 /* base pci_chipset */ 129 extern struct sparc_pci_chipset _sparc_pci_chipset; 130 131 /* power button handlers */ 132 static void psycho_register_power_button(struct psycho_softc *sc); 133 static void psycho_power_button_pressed(void *arg); 134 135 /* 136 * autoconfiguration 137 */ 138 static int psycho_match(struct device *, struct cfdata *, void *); 139 static void psycho_attach(struct device *, struct device *, void *); 140 static int psycho_print(void *aux, const char *p); 141 142 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 143 psycho_match, psycho_attach, NULL, NULL); 144 145 /* 146 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 147 * single PCI bus and does not have a streaming buffer. It often has an APB 148 * (advanced PCI bridge) connected to it, which was designed specifically for 149 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 150 * appears as two "simba"'s underneath the sabre. 151 * 152 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 153 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 154 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 155 * will usually find a "psycho+" since I don't think the original "psycho" 156 * ever shipped, and if it did it would be in the U30. 157 * 158 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 159 * both part of the same IC, they only have a single register space. As such, 160 * they need to be configured together, even though the autoconfiguration will 161 * attach them separately. 162 * 163 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 164 * as pci1 and pci2, although they have been implemented with other PCI bus 165 * numbers on some machines. 166 * 167 * On UltraII machines, there can be any number of "psycho+" ICs, each 168 * providing two PCI buses. 169 * 170 * 171 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 172 * the values of the following interrupts in this order: 173 * 174 * PCI Bus Error (30) 175 * DMA UE (2e) 176 * DMA CE (2f) 177 * Power Fail (25) 178 * 179 * We really should attach handlers for each. 180 * 181 */ 182 183 #define ROM_PCI_NAME "pci" 184 185 struct psycho_names { 186 const char *p_name; 187 int p_type; 188 } psycho_names[] = { 189 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 190 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 191 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 192 { "pci108e,a000", PSYCHO_MODE_SABRE }, 193 { "pci108e,a001", PSYCHO_MODE_SABRE }, 194 { NULL, 0 } 195 }; 196 197 static int 198 psycho_match(struct device *parent, struct cfdata *match, void *aux) 199 { 200 struct mainbus_attach_args *ma = aux; 201 char *model = prom_getpropstring(ma->ma_node, "model"); 202 int i; 203 204 /* match on a name of "pci" and a sabre or a psycho */ 205 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 206 for (i=0; psycho_names[i].p_name; i++) 207 if (strcmp(model, psycho_names[i].p_name) == 0) 208 return (1); 209 210 model = prom_getpropstring(ma->ma_node, "compatible"); 211 for (i=0; psycho_names[i].p_name; i++) 212 if (strcmp(model, psycho_names[i].p_name) == 0) 213 return (1); 214 } 215 return (0); 216 } 217 218 #ifdef DEBUG 219 static void psycho_dump_intmap(struct psycho_softc *sc); 220 static void 221 psycho_dump_intmap(struct psycho_softc *sc) 222 { 223 volatile uint64_t *intrmapptr = NULL; 224 225 printf("psycho_dump_intmap: OBIO\n"); 226 227 for (intrmapptr = &sc->sc_regs->scsi_int_map; 228 intrmapptr < &sc->sc_regs->ue_int_map; 229 intrmapptr++) 230 printf("%p: %llx\n", intrmapptr, 231 (unsigned long long)*intrmapptr); 232 233 printf("\tintmap:pci\n"); 234 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 235 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 236 intrmapptr++) 237 printf("%p: %llx\n", intrmapptr, 238 (unsigned long long)*intrmapptr); 239 240 printf("\tintmap:ffb\n"); 241 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 242 intrmapptr <= &sc->sc_regs->ffb1_int_map; 243 intrmapptr++) 244 printf("%p: %llx\n", intrmapptr, 245 (unsigned long long)*intrmapptr); 246 } 247 #endif 248 249 /* 250 * SUNW,psycho initialisation .. 251 * - find the per-psycho registers 252 * - figure out the IGN. 253 * - find our partner psycho 254 * - configure ourselves 255 * - bus range, bus, 256 * - get interrupt-map and interrupt-map-mask 257 * - setup the chipsets. 258 * - if we're the first of the pair, initialise the IOMMU, otherwise 259 * just copy it's tags and addresses. 260 */ 261 static void 262 psycho_attach(struct device *parent, struct device *self, void *aux) 263 { 264 struct psycho_softc *sc = (struct psycho_softc *)self; 265 struct psycho_softc *osc = NULL; 266 struct psycho_pbm *pp; 267 struct pcibus_attach_args pba; 268 struct mainbus_attach_args *ma = aux; 269 struct psycho_ranges *pr; 270 prop_dictionary_t dict; 271 bus_space_handle_t bh; 272 uint64_t csr, mem_base; 273 int psycho_br[2], n, i; 274 bus_space_handle_t pci_ctl; 275 char *model = prom_getpropstring(ma->ma_node, "model"); 276 277 aprint_normal("\n"); 278 279 sc->sc_node = ma->ma_node; 280 sc->sc_bustag = ma->ma_bustag; 281 sc->sc_dmatag = ma->ma_dmatag; 282 283 /* 284 * Identify the device. 285 */ 286 for (i=0; psycho_names[i].p_name; i++) 287 if (strcmp(model, psycho_names[i].p_name) == 0) { 288 sc->sc_mode = psycho_names[i].p_type; 289 goto found; 290 } 291 292 model = prom_getpropstring(ma->ma_node, "compatible"); 293 for (i=0; psycho_names[i].p_name; i++) 294 if (strcmp(model, psycho_names[i].p_name) == 0) { 295 sc->sc_mode = psycho_names[i].p_type; 296 goto found; 297 } 298 299 panic("unknown psycho model %s", model); 300 found: 301 302 /* 303 * The psycho gets three register banks: 304 * (0) per-PBM configuration and status registers 305 * (1) per-PBM PCI configuration space, containing only the 306 * PBM 256-byte PCI header 307 * (2) the shared psycho configuration registers (struct psychoreg) 308 */ 309 310 /* Register layouts are different. stuupid. */ 311 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 312 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 313 314 if (ma->ma_naddress > 2) { 315 sparc_promaddr_to_handle(sc->sc_bustag, 316 ma->ma_address[2], &sc->sc_bh); 317 sparc_promaddr_to_handle(sc->sc_bustag, 318 ma->ma_address[0], &pci_ctl); 319 320 sc->sc_regs = (struct psychoreg *) 321 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 322 } else if (ma->ma_nreg > 2) { 323 324 /* We need to map this in ourselves. */ 325 if (bus_space_map(sc->sc_bustag, 326 ma->ma_reg[2].ur_paddr, 327 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 328 &sc->sc_bh)) 329 panic("psycho_attach: cannot map regs"); 330 sc->sc_regs = (struct psychoreg *) 331 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 332 333 if (bus_space_map(sc->sc_bustag, 334 ma->ma_reg[0].ur_paddr, 335 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 336 &pci_ctl)) 337 panic("psycho_attach: cannot map ctl"); 338 } else 339 panic("psycho_attach: %d not enough registers", 340 ma->ma_nreg); 341 342 } else { 343 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 344 345 if (ma->ma_naddress) { 346 sparc_promaddr_to_handle(sc->sc_bustag, 347 ma->ma_address[0], &sc->sc_bh); 348 sc->sc_regs = (struct psychoreg *) 349 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 350 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 351 offsetof(struct psychoreg, psy_pcictl), 352 sizeof(struct pci_ctl), &pci_ctl); 353 } else if (ma->ma_nreg) { 354 355 /* We need to map this in ourselves. */ 356 if (bus_space_map(sc->sc_bustag, 357 ma->ma_reg[0].ur_paddr, 358 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 359 &sc->sc_bh)) 360 panic("psycho_attach: cannot map regs"); 361 sc->sc_regs = (struct psychoreg *) 362 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 363 364 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 365 offsetof(struct psychoreg, psy_pcictl), 366 sizeof(struct pci_ctl), &pci_ctl); 367 } else 368 panic("psycho_attach: %d not enough registers", 369 ma->ma_nreg); 370 } 371 372 373 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 374 offsetof(struct psychoreg, psy_csr)); 375 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 376 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 377 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 378 379 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 380 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 381 sc->sc_ign); 382 /* 383 * Match other psycho's that are already configured against 384 * the base physical address. This will be the same for a 385 * pair of devices that share register space. 386 */ 387 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 388 389 struct psycho_softc *asc = 390 (struct psycho_softc *)psycho_cd.cd_devs[n]; 391 392 if (asc == NULL || asc == sc) 393 /* This entry is not there or it is me */ 394 continue; 395 396 if (asc->sc_basepaddr != sc->sc_basepaddr) 397 /* This is an unrelated psycho */ 398 continue; 399 400 /* Found partner */ 401 osc = asc; 402 break; 403 } 404 405 406 /* Oh, dear. OK, lets get started */ 407 408 /* 409 * Setup the PCI control register 410 */ 411 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 412 offsetof(struct pci_ctl, pci_csr)); 413 csr |= PCICTL_MRLM | 414 PCICTL_ARB_PARK | 415 PCICTL_ERRINTEN | 416 PCICTL_4ENABLE; 417 csr &= ~(PCICTL_SERR | 418 PCICTL_CPU_PRIO | 419 PCICTL_ARB_PRIO | 420 PCICTL_RTRYWAIT); 421 bus_space_write_8(sc->sc_bustag, pci_ctl, 422 offsetof(struct pci_ctl, pci_csr), csr); 423 424 425 /* 426 * Allocate our psycho_pbm 427 */ 428 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 429 M_NOWAIT | M_ZERO); 430 if (pp == NULL) 431 panic("could not allocate psycho pbm"); 432 433 pp->pp_sc = sc; 434 435 /* grab the psycho ranges */ 436 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 437 438 /* get the bus-range for the psycho */ 439 psycho_get_bus_range(sc->sc_node, psycho_br); 440 441 pba.pba_bus = psycho_br[0]; 442 pba.pba_bridgetag = NULL; 443 pp->pp_busmax = psycho_br[1]; 444 445 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 446 aprint_normal("; PCI bus %d", psycho_br[0]); 447 448 pp->pp_pcictl = pci_ctl; 449 450 /* allocate our tags */ 451 pp->pp_memt = psycho_alloc_mem_tag(pp); 452 pp->pp_iot = psycho_alloc_io_tag(pp); 453 pp->pp_dmat = psycho_alloc_dma_tag(pp); 454 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 455 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 456 457 /* allocate a chipset for this */ 458 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 459 460 /* setup the rest of the psycho pbm */ 461 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 462 463 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 464 case 0x2000: 465 pp->pp_id = PSYCHO_PBM_A; 466 break; 467 case 0x4000: 468 pp->pp_id = PSYCHO_PBM_B; 469 break; 470 } 471 472 aprint_normal("\n"); 473 474 /* allocate extents for free bus space */ 475 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 476 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 477 478 #ifdef DEBUG 479 if (psycho_debug & PDB_INTR) 480 psycho_dump_intmap(sc); 481 #endif 482 483 /* 484 * And finally, if we're a sabre or the first of a pair of psycho's to 485 * arrive here, start up the IOMMU and get a config space tag. 486 */ 487 if (osc == NULL) { 488 uint64_t timeo; 489 490 /* 491 * Establish handlers for interesting interrupts.... 492 * 493 * XXX We need to remember these and remove this to support 494 * hotplug on the UPA/FHC bus. 495 * 496 * XXX Not all controllers have these, but installing them 497 * is better than trying to sort through this mess. 498 */ 499 psycho_set_intr(sc, 15, psycho_ue, 500 &sc->sc_regs->ue_int_map, 501 &sc->sc_regs->ue_clr_int); 502 psycho_set_intr(sc, 1, psycho_ce, 503 &sc->sc_regs->ce_int_map, 504 &sc->sc_regs->ce_clr_int); 505 psycho_set_intr(sc, 15, psycho_bus_a, 506 &sc->sc_regs->pciaerr_int_map, 507 &sc->sc_regs->pciaerr_clr_int); 508 psycho_set_intr(sc, 15, psycho_powerfail, 509 &sc->sc_regs->power_int_map, 510 &sc->sc_regs->power_clr_int); 511 psycho_register_power_button(sc); 512 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 513 /* sabre doesn't have these interrupts */ 514 psycho_set_intr(sc, 15, psycho_bus_b, 515 &sc->sc_regs->pciberr_int_map, 516 &sc->sc_regs->pciberr_clr_int); 517 psycho_set_intr(sc, 1, psycho_wakeup, 518 &sc->sc_regs->pwrmgt_int_map, 519 &sc->sc_regs->pwrmgt_clr_int); 520 } 521 522 /* 523 * Apparently a number of machines with psycho and psycho+ 524 * controllers have interrupt latency issues. We'll try 525 * setting the interrupt retry timeout to 0xff which gives us 526 * a retry of 3-6 usec (which is what sysio is set to) for the 527 * moment, which seems to help alleviate this problem. 528 */ 529 timeo = sc->sc_regs->intr_retry_timer; 530 if (timeo > 0xfff) { 531 #ifdef DEBUG 532 printf("decreasing interrupt retry timeout " 533 "from %lx to 0xff\n", (long)timeo); 534 #endif 535 sc->sc_regs->intr_retry_timer = 0xff; 536 } 537 538 /* 539 * Allocate bus node, this contains a prom node per bus. 540 */ 541 pp->pp_busnode = malloc(sizeof(*pp->pp_busnode), M_DEVBUF, 542 M_NOWAIT | M_ZERO); 543 if (pp->pp_busnode == NULL) 544 panic("psycho_attach: malloc pp->pp_busnode"); 545 546 /* 547 * Setup IOMMU and PCI configuration if we're the first 548 * of a pair of psycho's to arrive here. 549 * 550 * We should calculate a TSB size based on amount of RAM 551 * and number of bus controllers and number an type of 552 * child devices. 553 * 554 * For the moment, 32KB should be more than enough. 555 */ 556 sc->sc_is = malloc(sizeof(struct iommu_state), 557 M_DEVBUF, M_NOWAIT); 558 if (sc->sc_is == NULL) 559 panic("psycho_attach: malloc iommu_state"); 560 561 /* Point the strbuf_ctl at the iommu_state */ 562 pp->pp_sb.sb_is = sc->sc_is; 563 564 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 565 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 566 struct strbuf_ctl *sb = &pp->pp_sb; 567 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 568 569 /* 570 * Initialize the strbuf_ctl. 571 * 572 * The flush sync buffer must be 64-byte aligned. 573 */ 574 sb->sb_flush = (void *)(va & ~0x3f); 575 576 bus_space_subregion(sc->sc_bustag, pci_ctl, 577 offsetof(struct pci_ctl, pci_strbuf), 578 sizeof (struct iommu_strbuf), &sb->sb_sb); 579 580 /* Point our iommu at the strbuf_ctl */ 581 sc->sc_is->is_sb[0] = sb; 582 } 583 584 psycho_iommu_init(sc, 2); 585 586 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 587 588 /* 589 * XXX This is a really ugly hack because PCI config space 590 * is explicitly handled with unmapped accesses. 591 */ 592 i = sc->sc_bustag->type; 593 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 594 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 595 0x01000000, 0, &bh)) 596 panic("could not map psycho PCI configuration space"); 597 sc->sc_bustag->type = i; 598 sc->sc_configaddr = bh; 599 } else { 600 /* Share bus numbers with the pair of mine */ 601 pp->pp_busnode = osc->sc_psycho_this->pp_busnode; 602 603 /* Just copy IOMMU state, config tag and address */ 604 sc->sc_is = osc->sc_is; 605 sc->sc_configtag = osc->sc_configtag; 606 sc->sc_configaddr = osc->sc_configaddr; 607 608 /* Point the strbuf_ctl at the iommu_state */ 609 pp->pp_sb.sb_is = sc->sc_is; 610 611 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 612 struct strbuf_ctl *sb = &pp->pp_sb; 613 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 614 615 /* 616 * Initialize the strbuf_ctl. 617 * 618 * The flush sync buffer must be 64-byte aligned. 619 */ 620 sb->sb_flush = (void *)(va & ~0x3f); 621 622 bus_space_subregion(sc->sc_bustag, pci_ctl, 623 offsetof(struct pci_ctl, pci_strbuf), 624 sizeof (struct iommu_strbuf), &sb->sb_sb); 625 626 /* Point our iommu at the strbuf_ctl */ 627 sc->sc_is->is_sb[1] = sb; 628 } 629 iommu_reset(sc->sc_is); 630 } 631 632 dict = device_properties(self); 633 pr = get_psychorange(pp, 2); /* memory range */ 634 #ifdef DEBUG 635 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 636 #endif 637 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 638 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 639 640 /* 641 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 642 */ 643 pba.pba_flags = sc->sc_psycho_this->pp_flags; 644 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 645 pba.pba_dmat64 = NULL; 646 pba.pba_iot = sc->sc_psycho_this->pp_iot; 647 pba.pba_memt = sc->sc_psycho_this->pp_memt; 648 649 config_found_ia(self, "pcibus", &pba, psycho_print); 650 } 651 652 static int 653 psycho_print(void *aux, const char *p) 654 { 655 656 if (p == NULL) 657 return (UNCONF); 658 return (QUIET); 659 } 660 661 static void 662 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 663 uint64_t *mapper, uint64_t *clearer) 664 { 665 struct intrhand *ih; 666 667 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 668 M_DEVBUF, M_NOWAIT); 669 ih->ih_arg = sc; 670 ih->ih_map = mapper; 671 ih->ih_clr = clearer; 672 ih->ih_fun = handler; 673 ih->ih_pil = (1<<ipl); 674 ih->ih_number = INTVEC(*(ih->ih_map)); 675 intr_establish(ipl, ih); 676 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 677 } 678 679 /* 680 * power button handlers 681 */ 682 static void 683 psycho_register_power_button(struct psycho_softc *sc) 684 { 685 sysmon_task_queue_init(); 686 687 sc->sc_powerpressed = 0; 688 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 689 if (!sc->sc_smcontext) { 690 aprint_error_dev(&sc->sc_dev, "could not allocate power button context\n"); 691 return; 692 } 693 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 694 sc->sc_smcontext->smpsw_name = device_xname(&sc->sc_dev); 695 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 696 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 697 aprint_error_dev(&sc->sc_dev, "unable to register power button with sysmon\n"); 698 } 699 700 static void 701 psycho_power_button_pressed(void *arg) 702 { 703 struct psycho_softc *sc = arg; 704 705 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 706 sc->sc_powerpressed = 0; 707 } 708 709 /* 710 * PCI bus support 711 */ 712 713 /* 714 * allocate a PCI chipset tag and set it's cookie. 715 */ 716 static pci_chipset_tag_t 717 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 718 { 719 pci_chipset_tag_t npc; 720 721 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 722 if (npc == NULL) 723 panic("could not allocate pci_chipset_tag_t"); 724 memcpy(npc, pc, sizeof *pc); 725 npc->cookie = pp; 726 npc->rootnode = node; 727 728 return (npc); 729 } 730 731 /* 732 * create extent for free bus space, then allocate assigned regions. 733 */ 734 static struct extent * 735 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 736 { 737 struct psycho_registers *pa = NULL; 738 struct psycho_ranges *pr; 739 struct extent *ex; 740 bus_addr_t baddr, addr; 741 bus_size_t bsize, size; 742 int i, num; 743 744 /* get bus space size */ 745 pr = get_psychorange(pp, ss); 746 if (pr == NULL) { 747 printf("psycho_alloc_extent: get_psychorange failed\n"); 748 return NULL; 749 } 750 baddr = 0x00000000; 751 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 752 753 /* get available lists */ 754 num = 0; 755 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 756 printf("psycho_alloc_extent: no \"available\" property\n"); 757 return NULL; 758 } 759 760 /* create extent */ 761 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 762 EX_NOWAIT); 763 if (ex == NULL) { 764 printf("psycho_alloc_extent: extent_create failed\n"); 765 goto ret; 766 } 767 768 /* allocate assigned regions */ 769 for (i = 0; i < num; i++) 770 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 771 /* allocate bus space */ 772 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 773 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 774 if (extent_alloc_region(ex, baddr, addr - baddr, 775 EX_NOWAIT)) { 776 printf("psycho_alloc_extent: " 777 "extent_alloc_region %" PRIx64 "-%" 778 PRIx64 " failed\n", baddr, addr); 779 extent_destroy(ex); 780 ex = NULL; 781 goto ret; 782 } 783 baddr = addr + size; 784 } 785 /* allocate left region if available */ 786 if (baddr < bsize) 787 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 788 printf("psycho_alloc_extent: extent_alloc_region %" 789 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 790 extent_destroy(ex); 791 ex = NULL; 792 goto ret; 793 } 794 795 #ifdef DEBUG 796 /* print extent */ 797 extent_print(ex); 798 #endif 799 800 ret: 801 /* return extent */ 802 free(pa, M_DEVBUF); 803 return ex; 804 } 805 806 /* 807 * grovel the OBP for various psycho properties 808 */ 809 static void 810 psycho_get_bus_range(int node, int *brp) 811 { 812 int n, error; 813 814 n = 2; 815 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 816 if (error) 817 panic("could not get psycho bus-range, error %d", error); 818 if (n != 2) 819 panic("broken psycho bus-range"); 820 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 821 node, brp[0], brp[1])); 822 } 823 824 static void 825 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 826 { 827 828 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 829 panic("could not get psycho ranges"); 830 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 831 } 832 833 /* 834 * Interrupt handlers. 835 */ 836 837 static int 838 psycho_ue(void *arg) 839 { 840 struct psycho_softc *sc = (struct psycho_softc *)arg; 841 struct psychoreg *regs = sc->sc_regs; 842 long long afsr = regs->psy_ue_afsr; 843 long long afar = regs->psy_ue_afar; 844 long size = PAGE_SIZE<<(sc->sc_is->is_tsbsize); 845 struct iommu_state *is = sc->sc_is; 846 char bits[128]; 847 848 /* 849 * It's uncorrectable. Dump the regs and panic. 850 */ 851 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 852 device_xname(&sc->sc_dev), afar, 853 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 854 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 855 bits, sizeof(bits))); 856 857 /* Sometimes the AFAR points to an IOTSB entry */ 858 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 859 printf("IOVA %llx IOTTE %llx\n", 860 (long long)((afar - is->is_ptsb) * PAGE_SIZE + is->is_dvmabase), 861 (long long)ldxa(afar, ASI_PHYS_CACHED)); 862 } 863 #ifdef DDB 864 Debugger(); 865 #endif 866 regs->psy_ue_afar = 0; 867 regs->psy_ue_afsr = 0; 868 return (1); 869 } 870 static int 871 psycho_ce(void *arg) 872 { 873 struct psycho_softc *sc = (struct psycho_softc *)arg; 874 struct psychoreg *regs = sc->sc_regs; 875 876 /* 877 * It's correctable. Dump the regs and continue. 878 */ 879 880 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 881 device_xname(&sc->sc_dev), 882 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 883 return (1); 884 } 885 static int 886 psycho_bus_a(void *arg) 887 { 888 struct psycho_softc *sc = (struct psycho_softc *)arg; 889 struct psychoreg *regs = sc->sc_regs; 890 891 /* 892 * It's uncorrectable. Dump the regs and panic. 893 */ 894 895 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 896 device_xname(&sc->sc_dev), 897 (long long)regs->psy_pcictl[0].pci_afar, 898 (long long)regs->psy_pcictl[0].pci_afsr); 899 return (1); 900 } 901 static int 902 psycho_bus_b(void *arg) 903 { 904 struct psycho_softc *sc = (struct psycho_softc *)arg; 905 struct psychoreg *regs = sc->sc_regs; 906 907 /* 908 * It's uncorrectable. Dump the regs and panic. 909 */ 910 911 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 912 device_xname(&sc->sc_dev), 913 (long long)regs->psy_pcictl[0].pci_afar, 914 (long long)regs->psy_pcictl[0].pci_afsr); 915 return (1); 916 } 917 918 static int 919 psycho_powerfail(void *arg) 920 { 921 struct psycho_softc *sc = (struct psycho_softc *)arg; 922 923 /* 924 * We lost power. Queue a callback with thread context to 925 * handle all the real work. 926 */ 927 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 928 sc->sc_powerpressed = 1; 929 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 930 } 931 return (1); 932 } 933 934 static 935 int psycho_wakeup(void *arg) 936 { 937 struct psycho_softc *sc = (struct psycho_softc *)arg; 938 939 /* 940 * Gee, we don't really have a framework to deal with this 941 * properly. 942 */ 943 printf("%s: power management wakeup\n", device_xname(&sc->sc_dev)); 944 return (1); 945 } 946 947 948 949 /* 950 * initialise the IOMMU.. 951 */ 952 void 953 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 954 { 955 char *name; 956 struct iommu_state *is = sc->sc_is; 957 uint32_t iobase = -1; 958 int *vdma = NULL; 959 int nitem; 960 961 /* punch in our copies */ 962 is->is_bustag = sc->sc_bustag; 963 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 964 offsetof(struct psychoreg, psy_iommu), 965 sizeof (struct iommureg), 966 &is->is_iommu); 967 968 /* 969 * Separate the men from the boys. Get the `virtual-dma' 970 * property for sabre and use that to make sure the damn 971 * iommu works. 972 * 973 * We could query the `#virtual-dma-size-cells' and 974 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 975 */ 976 nitem = 0; 977 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 978 &vdma)) { 979 /* Damn. Gotta use these values. */ 980 iobase = vdma[0]; 981 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 982 switch (vdma[1]) { 983 TSBCASE(1); TSBCASE(2); TSBCASE(3); 984 TSBCASE(4); TSBCASE(5); TSBCASE(6); 985 default: 986 printf("bogus tsb size %x, using 7\n", vdma[1]); 987 TSBCASE(7); 988 } 989 #undef TSBCASE 990 } 991 992 /* give us a nice name.. */ 993 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 994 if (name == 0) 995 panic("couldn't malloc iommu name"); 996 snprintf(name, 32, "%s dvma", device_xname(&sc->sc_dev)); 997 998 iommu_init(name, is, tsbsize, iobase); 999 } 1000 1001 /* 1002 * below here is bus space and bus DMA support 1003 */ 1004 bus_space_tag_t 1005 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1006 { 1007 struct psycho_softc *sc = pp->pp_sc; 1008 bus_space_tag_t bt; 1009 1010 bt = (bus_space_tag_t) 1011 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 1012 if (bt == NULL) 1013 panic("could not allocate psycho bus tag"); 1014 1015 memset(bt, 0, sizeof *bt); 1016 bt->cookie = pp; 1017 bt->parent = sc->sc_bustag; 1018 bt->type = type; 1019 bt->sparc_bus_map = _psycho_bus_map; 1020 bt->sparc_bus_mmap = psycho_bus_mmap; 1021 bt->sparc_intr_establish = psycho_intr_establish; 1022 return (bt); 1023 } 1024 1025 bus_dma_tag_t 1026 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1027 { 1028 struct psycho_softc *sc = pp->pp_sc; 1029 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1030 1031 dt = (bus_dma_tag_t) 1032 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1033 if (dt == NULL) 1034 panic("could not allocate psycho DMA tag"); 1035 1036 memset(dt, 0, sizeof *dt); 1037 dt->_cookie = pp; 1038 dt->_parent = pdt; 1039 #define PCOPY(x) dt->x = pdt->x 1040 PCOPY(_dmamap_create); 1041 PCOPY(_dmamap_destroy); 1042 dt->_dmamap_load = psycho_dmamap_load; 1043 PCOPY(_dmamap_load_mbuf); 1044 PCOPY(_dmamap_load_uio); 1045 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 1046 dt->_dmamap_unload = psycho_dmamap_unload; 1047 dt->_dmamap_sync = psycho_dmamap_sync; 1048 dt->_dmamem_alloc = psycho_dmamem_alloc; 1049 dt->_dmamem_free = psycho_dmamem_free; 1050 dt->_dmamem_map = psycho_dmamem_map; 1051 dt->_dmamem_unmap = psycho_dmamem_unmap; 1052 PCOPY(_dmamem_mmap); 1053 #undef PCOPY 1054 return (dt); 1055 } 1056 1057 /* 1058 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1059 * PCI physical addresses. 1060 */ 1061 1062 static int 1063 get_childspace(int type) 1064 { 1065 int ss; 1066 1067 switch (type) { 1068 case PCI_CONFIG_BUS_SPACE: 1069 ss = 0x00; 1070 break; 1071 case PCI_IO_BUS_SPACE: 1072 ss = 0x01; 1073 break; 1074 case PCI_MEMORY_BUS_SPACE: 1075 ss = 0x02; 1076 break; 1077 #if 0 1078 /* we don't do 64 bit memory space */ 1079 case PCI_MEMORY64_BUS_SPACE: 1080 ss = 0x03; 1081 break; 1082 #endif 1083 default: 1084 panic("get_childspace: unknown bus type"); 1085 } 1086 1087 return (ss); 1088 } 1089 1090 static struct psycho_ranges * 1091 get_psychorange(struct psycho_pbm *pp, int ss) 1092 { 1093 int i; 1094 1095 for (i = 0; i < pp->pp_nrange; i++) { 1096 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1097 return (&pp->pp_range[i]); 1098 } 1099 /* not found */ 1100 return (NULL); 1101 } 1102 1103 static int 1104 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1105 int flags, vaddr_t unused, bus_space_handle_t *hp) 1106 { 1107 struct psycho_pbm *pp = t->cookie; 1108 struct psycho_softc *sc = pp->pp_sc; 1109 struct psycho_ranges *pr; 1110 bus_addr_t paddr; 1111 int ss; 1112 1113 DPRINTF(PDB_BUSMAP, 1114 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1115 t->type, (unsigned long long)offset, 1116 (unsigned long long)size, flags)); 1117 1118 ss = get_childspace(t->type); 1119 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1120 1121 pr = get_psychorange(pp, ss); 1122 if (pr != NULL) { 1123 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1124 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1125 "space %lx offset %lx paddr %qx\n", 1126 (long)ss, (long)offset, 1127 (unsigned long long)paddr)); 1128 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1129 flags, 0, hp)); 1130 } 1131 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1132 return (EINVAL); 1133 } 1134 1135 static paddr_t 1136 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1137 int flags) 1138 { 1139 bus_addr_t offset = paddr; 1140 struct psycho_pbm *pp = t->cookie; 1141 struct psycho_softc *sc = pp->pp_sc; 1142 struct psycho_ranges *pr; 1143 int ss; 1144 1145 ss = get_childspace(t->type); 1146 1147 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1148 prot, flags, (unsigned long long)paddr)); 1149 1150 pr = get_psychorange(pp, ss); 1151 if (pr != NULL) { 1152 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1153 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1154 "space %lx offset %lx paddr %qx\n", 1155 (long)ss, (long)offset, 1156 (unsigned long long)paddr)); 1157 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1158 prot, flags)); 1159 } 1160 1161 return (-1); 1162 } 1163 1164 /* 1165 * Get a PCI offset address from bus_space_handle_t. 1166 */ 1167 bus_addr_t 1168 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1169 { 1170 struct psycho_pbm *pp = t->cookie; 1171 struct psycho_ranges *pr; 1172 bus_addr_t addr, offset; 1173 vaddr_t va; 1174 int ss; 1175 1176 addr = hp->_ptr; 1177 ss = get_childspace(t->type); 1178 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1179 " cspace %d", t->type, addr, ss)); 1180 1181 pr = get_psychorange(pp, ss); 1182 if (pr != NULL) { 1183 if (!PHYS_ASI(hp->_asi)) { 1184 va = trunc_page((vaddr_t)addr); 1185 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1186 DPRINTF(PDB_BUSMAP, 1187 ("\n pmap_extract FAILED\n")); 1188 return (-1); 1189 } 1190 addr += hp->_ptr & PGOFSET; 1191 } 1192 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1193 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1194 " offset %" PRIx64 "\n", addr, offset)); 1195 return (offset); 1196 } 1197 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1198 return (-1); 1199 } 1200 1201 1202 /* 1203 * install an interrupt handler for a PCI device 1204 */ 1205 void * 1206 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1207 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1208 { 1209 struct psycho_pbm *pp = t->cookie; 1210 struct psycho_softc *sc = pp->pp_sc; 1211 struct intrhand *ih; 1212 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1213 int64_t imap = 0; 1214 int ino; 1215 long vec = INTVEC(ihandle); 1216 1217 ih = (struct intrhand *) 1218 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1219 if (ih == NULL) 1220 return (NULL); 1221 1222 /* 1223 * Hunt through all the interrupt mapping regs to look for our 1224 * interrupt vector. 1225 * 1226 * XXX We only compare INOs rather than IGNs since the firmware may 1227 * not provide the IGN and the IGN is constant for all device on that 1228 * PCI controller. This could cause problems for the FFB/external 1229 * interrupt which has a full vector that can be set arbitrarily. 1230 */ 1231 1232 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1233 ino = INTINO(vec); 1234 DPRINTF(PDB_INTR, (" ino %x", ino)); 1235 1236 /* If the device didn't ask for an IPL, use the one encoded. */ 1237 if (level == IPL_NONE) level = INTLEV(vec); 1238 /* If it still has no level, print a warning and assign IPL 2 */ 1239 if (level == IPL_NONE) { 1240 printf("ERROR: no IPL, setting IPL 2.\n"); 1241 level = 2; 1242 } 1243 1244 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1245 (long)ino, intrlev[ino])); 1246 1247 /* 1248 * First look for PCI interrupts, otherwise the PCI A slot 0 1249 * INTA# interrupt might match an unused non-PCI (obio) 1250 * interrupt. 1251 */ 1252 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1253 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1254 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1255 intrmapptr++, intrclrptr += 4) { 1256 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1257 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1258 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1259 continue; 1260 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1261 intrclrptr += vec & 0x3; 1262 goto found; 1263 } 1264 } 1265 1266 /* Now hunt thru obio. */ 1267 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1268 intrclrptr = &sc->sc_regs->scsi_clr_int; 1269 intrmapptr < &sc->sc_regs->ue_int_map; 1270 intrmapptr++, intrclrptr++) { 1271 if (INTINO(*intrmapptr) == ino) 1272 goto found; 1273 } 1274 1275 /* Finally check the two FFB slots */ 1276 intrclrptr = NULL; /* XXX? */ 1277 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1278 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1279 intrmapptr++) { 1280 if (INTVEC(*intrmapptr) == ino) 1281 goto found; 1282 } 1283 1284 printf("Cannot find interrupt vector %lx\n", vec); 1285 return (NULL); 1286 1287 found: 1288 /* Register the map and clear intr registers */ 1289 ih->ih_map = intrmapptr; 1290 ih->ih_clr = intrclrptr; 1291 1292 ih->ih_fun = handler; 1293 ih->ih_arg = arg; 1294 ih->ih_pil = level; 1295 ih->ih_number = ino | sc->sc_ign; 1296 1297 DPRINTF(PDB_INTR, ( 1298 "; installing handler %p arg %p with ino %u pil %u\n", 1299 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1300 1301 intr_establish(ih->ih_pil, ih); 1302 1303 /* 1304 * Enable the interrupt now we have the handler installed. 1305 * Read the current value as we can't change it besides the 1306 * valid bit so so make sure only this bit is changed. 1307 * 1308 * XXXX --- we really should use bus_space for this. 1309 */ 1310 if (intrmapptr) { 1311 imap = *intrmapptr; 1312 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1313 (unsigned long long)imap)); 1314 1315 /* Enable the interrupt */ 1316 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1317 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1318 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1319 (unsigned long long)imap)); 1320 *intrmapptr = imap; 1321 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1322 (unsigned long long)(imap = *intrmapptr))); 1323 } 1324 if (intrclrptr) { 1325 /* set state to IDLE */ 1326 *intrclrptr = 0; 1327 } 1328 return (ih); 1329 } 1330 1331 /* 1332 * hooks into the iommu dvma calls. 1333 */ 1334 int 1335 psycho_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf, 1336 bus_size_t buflen, struct proc *p, int flags) 1337 { 1338 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1339 1340 return (iommu_dvmamap_load(t, &pp->pp_sb, map, buf, buflen, p, flags)); 1341 } 1342 1343 void 1344 psycho_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map) 1345 { 1346 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1347 1348 iommu_dvmamap_unload(t, &pp->pp_sb, map); 1349 } 1350 1351 int 1352 psycho_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, 1353 bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags) 1354 { 1355 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1356 1357 return (iommu_dvmamap_load_raw(t, &pp->pp_sb, map, segs, nsegs, flags, size)); 1358 } 1359 1360 void 1361 psycho_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1362 bus_size_t len, int ops) 1363 { 1364 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1365 1366 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1367 /* Flush the CPU then the IOMMU */ 1368 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1369 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1370 } 1371 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1372 /* Flush the IOMMU then the CPU */ 1373 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1374 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1375 } 1376 1377 } 1378 1379 int 1380 psycho_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, 1381 bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs, 1382 int flags) 1383 { 1384 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1385 1386 return (iommu_dvmamem_alloc(t, &pp->pp_sb, size, alignment, boundary, 1387 segs, nsegs, rsegs, flags)); 1388 } 1389 1390 void 1391 psycho_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs) 1392 { 1393 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1394 1395 iommu_dvmamem_free(t, &pp->pp_sb, segs, nsegs); 1396 } 1397 1398 int 1399 psycho_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, 1400 size_t size, void **kvap, int flags) 1401 { 1402 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1403 1404 return (iommu_dvmamem_map(t, &pp->pp_sb, segs, nsegs, size, kvap, flags)); 1405 } 1406 1407 void 1408 psycho_dmamem_unmap(bus_dma_tag_t t, void *kva, size_t size) 1409 { 1410 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1411 1412 iommu_dvmamem_unmap(t, &pp->pp_sb, kva, size); 1413 } 1414
Indexes created Thu Sep 25 16:09:42 GMT 2025