psycho.c revision 1.88
1 /* $NetBSD: psycho.c,v 1.88 2008/06/13 13:10:49 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.88 2008/06/13 13:10:49 cegger Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 int psycho_debug = 0x0; 72 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 73 #else 74 #define DPRINTF(l, s) 75 #endif 76 77 #include <sys/param.h> 78 #include <sys/device.h> 79 #include <sys/errno.h> 80 #include <sys/extent.h> 81 #include <sys/malloc.h> 82 #include <sys/systm.h> 83 #include <sys/time.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #define _SPARC_BUS_DMA_PRIVATE 89 #include <machine/bus.h> 90 #include <machine/autoconf.h> 91 #include <machine/psl.h> 92 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcireg.h> 95 #include <dev/sysmon/sysmon_taskq.h> 96 97 #include <sparc64/dev/iommureg.h> 98 #include <sparc64/dev/iommuvar.h> 99 #include <sparc64/dev/psychoreg.h> 100 #include <sparc64/dev/psychovar.h> 101 #include <sparc64/sparc64/cache.h> 102 103 #include "ioconf.h" 104 105 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 106 pci_chipset_tag_t); 107 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 108 const char *); 109 static void psycho_get_bus_range(int, int *); 110 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 111 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 112 uint64_t *); 113 114 /* Interrupt handlers */ 115 static int psycho_ue(void *); 116 static int psycho_ce(void *); 117 static int psycho_bus_a(void *); 118 static int psycho_bus_b(void *); 119 static int psycho_powerfail(void *); 120 static int psycho_wakeup(void *); 121 122 123 /* IOMMU support */ 124 static void psycho_iommu_init(struct psycho_softc *, int); 125 126 /* 127 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 128 * of the bus DMA support is provided by the iommu dvma controller. 129 */ 130 static int get_childspace(int); 131 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 132 133 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 134 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 135 vaddr_t, bus_space_handle_t *); 136 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 137 void *, void(*)(void)); 138 139 static int psycho_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t, 140 struct proc *, int); 141 static void psycho_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 142 static int psycho_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, 143 bus_dma_segment_t *, int, bus_size_t, int); 144 static void psycho_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 145 bus_size_t, int); 146 int psycho_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 147 bus_dma_segment_t *, int, int *, int); 148 void psycho_dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int); 149 int psycho_dmamem_map(bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 150 void **, int); 151 void psycho_dmamem_unmap(bus_dma_tag_t, void *, size_t); 152 153 /* base pci_chipset */ 154 extern struct sparc_pci_chipset _sparc_pci_chipset; 155 156 /* power button handlers */ 157 static void psycho_register_power_button(struct psycho_softc *sc); 158 static void psycho_power_button_pressed(void *arg); 159 160 /* 161 * autoconfiguration 162 */ 163 static int psycho_match(struct device *, struct cfdata *, void *); 164 static void psycho_attach(struct device *, struct device *, void *); 165 static int psycho_print(void *aux, const char *p); 166 167 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 168 psycho_match, psycho_attach, NULL, NULL); 169 170 /* 171 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 172 * single PCI bus and does not have a streaming buffer. It often has an APB 173 * (advanced PCI bridge) connected to it, which was designed specifically for 174 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 175 * appears as two "simba"'s underneath the sabre. 176 * 177 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 178 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 179 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 180 * will usually find a "psycho+" since I don't think the original "psycho" 181 * ever shipped, and if it did it would be in the U30. 182 * 183 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 184 * both part of the same IC, they only have a single register space. As such, 185 * they need to be configured together, even though the autoconfiguration will 186 * attach them separately. 187 * 188 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 189 * as pci1 and pci2, although they have been implemented with other PCI bus 190 * numbers on some machines. 191 * 192 * On UltraII machines, there can be any number of "psycho+" ICs, each 193 * providing two PCI buses. 194 * 195 * 196 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 197 * the values of the following interrupts in this order: 198 * 199 * PCI Bus Error (30) 200 * DMA UE (2e) 201 * DMA CE (2f) 202 * Power Fail (25) 203 * 204 * We really should attach handlers for each. 205 * 206 */ 207 208 #define ROM_PCI_NAME "pci" 209 210 struct psycho_names { 211 const char *p_name; 212 int p_type; 213 } psycho_names[] = { 214 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 215 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 216 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 217 { "pci108e,a000", PSYCHO_MODE_SABRE }, 218 { "pci108e,a001", PSYCHO_MODE_SABRE }, 219 { NULL, 0 } 220 }; 221 222 static int 223 psycho_match(struct device *parent, struct cfdata *match, void *aux) 224 { 225 struct mainbus_attach_args *ma = aux; 226 char *model = prom_getpropstring(ma->ma_node, "model"); 227 int i; 228 229 /* match on a name of "pci" and a sabre or a psycho */ 230 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 231 for (i=0; psycho_names[i].p_name; i++) 232 if (strcmp(model, psycho_names[i].p_name) == 0) 233 return (1); 234 235 model = prom_getpropstring(ma->ma_node, "compatible"); 236 for (i=0; psycho_names[i].p_name; i++) 237 if (strcmp(model, psycho_names[i].p_name) == 0) 238 return (1); 239 } 240 return (0); 241 } 242 243 #ifdef DEBUG 244 static void psycho_dump_intmap(struct psycho_softc *sc); 245 static void 246 psycho_dump_intmap(struct psycho_softc *sc) 247 { 248 volatile uint64_t *intrmapptr = NULL; 249 250 printf("psycho_dump_intmap: OBIO\n"); 251 252 for (intrmapptr = &sc->sc_regs->scsi_int_map; 253 intrmapptr < &sc->sc_regs->ue_int_map; 254 intrmapptr++) 255 printf("%p: %llx\n", intrmapptr, 256 (unsigned long long)*intrmapptr); 257 258 printf("\tintmap:pci\n"); 259 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 260 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 261 intrmapptr++) 262 printf("%p: %llx\n", intrmapptr, 263 (unsigned long long)*intrmapptr); 264 265 printf("\tintmap:ffb\n"); 266 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 267 intrmapptr <= &sc->sc_regs->ffb1_int_map; 268 intrmapptr++) 269 printf("%p: %llx\n", intrmapptr, 270 (unsigned long long)*intrmapptr); 271 } 272 #endif 273 274 /* 275 * SUNW,psycho initialisation .. 276 * - find the per-psycho registers 277 * - figure out the IGN. 278 * - find our partner psycho 279 * - configure ourselves 280 * - bus range, bus, 281 * - get interrupt-map and interrupt-map-mask 282 * - setup the chipsets. 283 * - if we're the first of the pair, initialise the IOMMU, otherwise 284 * just copy it's tags and addresses. 285 */ 286 static void 287 psycho_attach(struct device *parent, struct device *self, void *aux) 288 { 289 struct psycho_softc *sc = (struct psycho_softc *)self; 290 struct psycho_softc *osc = NULL; 291 struct psycho_pbm *pp; 292 struct pcibus_attach_args pba; 293 struct mainbus_attach_args *ma = aux; 294 struct psycho_ranges *pr; 295 prop_dictionary_t dict; 296 bus_space_handle_t bh; 297 uint64_t csr, mem_base; 298 int psycho_br[2], n, i; 299 bus_space_handle_t pci_ctl; 300 char *model = prom_getpropstring(ma->ma_node, "model"); 301 302 aprint_normal("\n"); 303 304 sc->sc_node = ma->ma_node; 305 sc->sc_bustag = ma->ma_bustag; 306 sc->sc_dmatag = ma->ma_dmatag; 307 308 /* 309 * Identify the device. 310 */ 311 for (i=0; psycho_names[i].p_name; i++) 312 if (strcmp(model, psycho_names[i].p_name) == 0) { 313 sc->sc_mode = psycho_names[i].p_type; 314 goto found; 315 } 316 317 model = prom_getpropstring(ma->ma_node, "compatible"); 318 for (i=0; psycho_names[i].p_name; i++) 319 if (strcmp(model, psycho_names[i].p_name) == 0) { 320 sc->sc_mode = psycho_names[i].p_type; 321 goto found; 322 } 323 324 panic("unknown psycho model %s", model); 325 found: 326 327 /* 328 * The psycho gets three register banks: 329 * (0) per-PBM configuration and status registers 330 * (1) per-PBM PCI configuration space, containing only the 331 * PBM 256-byte PCI header 332 * (2) the shared psycho configuration registers (struct psychoreg) 333 */ 334 335 /* Register layouts are different. stuupid. */ 336 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 337 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 338 339 if (ma->ma_naddress > 2) { 340 sparc_promaddr_to_handle(sc->sc_bustag, 341 ma->ma_address[2], &sc->sc_bh); 342 sparc_promaddr_to_handle(sc->sc_bustag, 343 ma->ma_address[0], &pci_ctl); 344 345 sc->sc_regs = (struct psychoreg *) 346 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 347 } else if (ma->ma_nreg > 2) { 348 349 /* We need to map this in ourselves. */ 350 if (bus_space_map(sc->sc_bustag, 351 ma->ma_reg[2].ur_paddr, 352 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 353 &sc->sc_bh)) 354 panic("psycho_attach: cannot map regs"); 355 sc->sc_regs = (struct psychoreg *) 356 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 357 358 if (bus_space_map(sc->sc_bustag, 359 ma->ma_reg[0].ur_paddr, 360 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 361 &pci_ctl)) 362 panic("psycho_attach: cannot map ctl"); 363 } else 364 panic("psycho_attach: %d not enough registers", 365 ma->ma_nreg); 366 367 } else { 368 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 369 370 if (ma->ma_naddress) { 371 sparc_promaddr_to_handle(sc->sc_bustag, 372 ma->ma_address[0], &sc->sc_bh); 373 sc->sc_regs = (struct psychoreg *) 374 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 375 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 376 offsetof(struct psychoreg, psy_pcictl), 377 sizeof(struct pci_ctl), &pci_ctl); 378 } else if (ma->ma_nreg) { 379 380 /* We need to map this in ourselves. */ 381 if (bus_space_map(sc->sc_bustag, 382 ma->ma_reg[0].ur_paddr, 383 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 384 &sc->sc_bh)) 385 panic("psycho_attach: cannot map regs"); 386 sc->sc_regs = (struct psychoreg *) 387 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 388 389 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 390 offsetof(struct psychoreg, psy_pcictl), 391 sizeof(struct pci_ctl), &pci_ctl); 392 } else 393 panic("psycho_attach: %d not enough registers", 394 ma->ma_nreg); 395 } 396 397 398 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 399 offsetof(struct psychoreg, psy_csr)); 400 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 401 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 402 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 403 404 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 405 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 406 sc->sc_ign); 407 /* 408 * Match other psycho's that are already configured against 409 * the base physical address. This will be the same for a 410 * pair of devices that share register space. 411 */ 412 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 413 414 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 415 416 if (asc == NULL || asc == sc) 417 /* This entry is not there or it is me */ 418 continue; 419 420 if (asc->sc_basepaddr != sc->sc_basepaddr) 421 /* This is an unrelated psycho */ 422 continue; 423 424 /* Found partner */ 425 osc = asc; 426 break; 427 } 428 429 430 /* Oh, dear. OK, lets get started */ 431 432 /* 433 * Setup the PCI control register 434 */ 435 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 436 offsetof(struct pci_ctl, pci_csr)); 437 csr |= PCICTL_MRLM | 438 PCICTL_ARB_PARK | 439 PCICTL_ERRINTEN | 440 PCICTL_4ENABLE; 441 csr &= ~(PCICTL_SERR | 442 PCICTL_CPU_PRIO | 443 PCICTL_ARB_PRIO | 444 PCICTL_RTRYWAIT); 445 bus_space_write_8(sc->sc_bustag, pci_ctl, 446 offsetof(struct pci_ctl, pci_csr), csr); 447 448 449 /* 450 * Allocate our psycho_pbm 451 */ 452 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 453 M_NOWAIT | M_ZERO); 454 if (pp == NULL) 455 panic("could not allocate psycho pbm"); 456 457 pp->pp_sc = sc; 458 459 /* grab the psycho ranges */ 460 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 461 462 /* get the bus-range for the psycho */ 463 psycho_get_bus_range(sc->sc_node, psycho_br); 464 465 pba.pba_bus = psycho_br[0]; 466 pba.pba_bridgetag = NULL; 467 pp->pp_busmax = psycho_br[1]; 468 469 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 470 aprint_normal("; PCI bus %d", psycho_br[0]); 471 472 pp->pp_pcictl = pci_ctl; 473 474 /* allocate our tags */ 475 pp->pp_memt = psycho_alloc_mem_tag(pp); 476 pp->pp_iot = psycho_alloc_io_tag(pp); 477 pp->pp_dmat = psycho_alloc_dma_tag(pp); 478 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 479 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 480 481 /* allocate a chipset for this */ 482 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 483 484 /* setup the rest of the psycho pbm */ 485 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 486 487 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 488 case 0x2000: 489 pp->pp_id = PSYCHO_PBM_A; 490 break; 491 case 0x4000: 492 pp->pp_id = PSYCHO_PBM_B; 493 break; 494 } 495 496 aprint_normal("\n"); 497 498 /* allocate extents for free bus space */ 499 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 500 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 501 502 #ifdef DEBUG 503 if (psycho_debug & PDB_INTR) 504 psycho_dump_intmap(sc); 505 #endif 506 507 /* 508 * And finally, if we're a sabre or the first of a pair of psycho's to 509 * arrive here, start up the IOMMU and get a config space tag. 510 */ 511 if (osc == NULL) { 512 uint64_t timeo; 513 514 /* 515 * Establish handlers for interesting interrupts.... 516 * 517 * XXX We need to remember these and remove this to support 518 * hotplug on the UPA/FHC bus. 519 * 520 * XXX Not all controllers have these, but installing them 521 * is better than trying to sort through this mess. 522 */ 523 psycho_set_intr(sc, 15, psycho_ue, 524 &sc->sc_regs->ue_int_map, 525 &sc->sc_regs->ue_clr_int); 526 psycho_set_intr(sc, 1, psycho_ce, 527 &sc->sc_regs->ce_int_map, 528 &sc->sc_regs->ce_clr_int); 529 psycho_set_intr(sc, 15, psycho_bus_a, 530 &sc->sc_regs->pciaerr_int_map, 531 &sc->sc_regs->pciaerr_clr_int); 532 psycho_set_intr(sc, 15, psycho_powerfail, 533 &sc->sc_regs->power_int_map, 534 &sc->sc_regs->power_clr_int); 535 psycho_register_power_button(sc); 536 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 537 /* sabre doesn't have these interrupts */ 538 psycho_set_intr(sc, 15, psycho_bus_b, 539 &sc->sc_regs->pciberr_int_map, 540 &sc->sc_regs->pciberr_clr_int); 541 psycho_set_intr(sc, 1, psycho_wakeup, 542 &sc->sc_regs->pwrmgt_int_map, 543 &sc->sc_regs->pwrmgt_clr_int); 544 } 545 546 /* 547 * Apparently a number of machines with psycho and psycho+ 548 * controllers have interrupt latency issues. We'll try 549 * setting the interrupt retry timeout to 0xff which gives us 550 * a retry of 3-6 usec (which is what sysio is set to) for the 551 * moment, which seems to help alleviate this problem. 552 */ 553 timeo = sc->sc_regs->intr_retry_timer; 554 if (timeo > 0xfff) { 555 #ifdef DEBUG 556 printf("decreasing interrupt retry timeout " 557 "from %lx to 0xff\n", (long)timeo); 558 #endif 559 sc->sc_regs->intr_retry_timer = 0xff; 560 } 561 562 /* 563 * Allocate bus node, this contains a prom node per bus. 564 */ 565 pp->pp_busnode = malloc(sizeof(*pp->pp_busnode), M_DEVBUF, 566 M_NOWAIT | M_ZERO); 567 if (pp->pp_busnode == NULL) 568 panic("psycho_attach: malloc pp->pp_busnode"); 569 570 /* 571 * Setup IOMMU and PCI configuration if we're the first 572 * of a pair of psycho's to arrive here. 573 * 574 * We should calculate a TSB size based on amount of RAM 575 * and number of bus controllers and number an type of 576 * child devices. 577 * 578 * For the moment, 32KB should be more than enough. 579 */ 580 sc->sc_is = malloc(sizeof(struct iommu_state), 581 M_DEVBUF, M_NOWAIT); 582 if (sc->sc_is == NULL) 583 panic("psycho_attach: malloc iommu_state"); 584 585 /* Point the strbuf_ctl at the iommu_state */ 586 pp->pp_sb.sb_is = sc->sc_is; 587 588 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 589 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 590 struct strbuf_ctl *sb = &pp->pp_sb; 591 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 592 593 /* 594 * Initialize the strbuf_ctl. 595 * 596 * The flush sync buffer must be 64-byte aligned. 597 */ 598 sb->sb_flush = (void *)(va & ~0x3f); 599 600 bus_space_subregion(sc->sc_bustag, pci_ctl, 601 offsetof(struct pci_ctl, pci_strbuf), 602 sizeof (struct iommu_strbuf), &sb->sb_sb); 603 604 /* Point our iommu at the strbuf_ctl */ 605 sc->sc_is->is_sb[0] = sb; 606 } 607 608 psycho_iommu_init(sc, 2); 609 610 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 611 612 /* 613 * XXX This is a really ugly hack because PCI config space 614 * is explicitly handled with unmapped accesses. 615 */ 616 i = sc->sc_bustag->type; 617 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 618 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 619 0x01000000, 0, &bh)) 620 panic("could not map psycho PCI configuration space"); 621 sc->sc_bustag->type = i; 622 sc->sc_configaddr = bh; 623 } else { 624 /* Share bus numbers with the pair of mine */ 625 pp->pp_busnode = osc->sc_psycho_this->pp_busnode; 626 627 /* Just copy IOMMU state, config tag and address */ 628 sc->sc_is = osc->sc_is; 629 sc->sc_configtag = osc->sc_configtag; 630 sc->sc_configaddr = osc->sc_configaddr; 631 632 /* Point the strbuf_ctl at the iommu_state */ 633 pp->pp_sb.sb_is = sc->sc_is; 634 635 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 636 struct strbuf_ctl *sb = &pp->pp_sb; 637 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 638 639 /* 640 * Initialize the strbuf_ctl. 641 * 642 * The flush sync buffer must be 64-byte aligned. 643 */ 644 sb->sb_flush = (void *)(va & ~0x3f); 645 646 bus_space_subregion(sc->sc_bustag, pci_ctl, 647 offsetof(struct pci_ctl, pci_strbuf), 648 sizeof (struct iommu_strbuf), &sb->sb_sb); 649 650 /* Point our iommu at the strbuf_ctl */ 651 sc->sc_is->is_sb[1] = sb; 652 } 653 iommu_reset(sc->sc_is); 654 } 655 656 dict = device_properties(self); 657 pr = get_psychorange(pp, 2); /* memory range */ 658 #ifdef DEBUG 659 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 660 #endif 661 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 662 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 663 664 /* 665 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 666 */ 667 pba.pba_flags = sc->sc_psycho_this->pp_flags; 668 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 669 pba.pba_dmat64 = NULL; 670 pba.pba_iot = sc->sc_psycho_this->pp_iot; 671 pba.pba_memt = sc->sc_psycho_this->pp_memt; 672 673 config_found_ia(self, "pcibus", &pba, psycho_print); 674 } 675 676 static int 677 psycho_print(void *aux, const char *p) 678 { 679 680 if (p == NULL) 681 return (UNCONF); 682 return (QUIET); 683 } 684 685 static void 686 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 687 uint64_t *mapper, uint64_t *clearer) 688 { 689 struct intrhand *ih; 690 691 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 692 M_DEVBUF, M_NOWAIT); 693 ih->ih_arg = sc; 694 ih->ih_map = mapper; 695 ih->ih_clr = clearer; 696 ih->ih_fun = handler; 697 ih->ih_pil = (1<<ipl); 698 ih->ih_number = INTVEC(*(ih->ih_map)); 699 intr_establish(ipl, ipl != IPL_VM, ih); 700 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 701 } 702 703 /* 704 * power button handlers 705 */ 706 static void 707 psycho_register_power_button(struct psycho_softc *sc) 708 { 709 sysmon_task_queue_init(); 710 711 sc->sc_powerpressed = 0; 712 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 713 if (!sc->sc_smcontext) { 714 aprint_error_dev(&sc->sc_dev, "could not allocate power button context\n"); 715 return; 716 } 717 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 718 sc->sc_smcontext->smpsw_name = device_xname(&sc->sc_dev); 719 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 720 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 721 aprint_error_dev(&sc->sc_dev, "unable to register power button with sysmon\n"); 722 } 723 724 static void 725 psycho_power_button_pressed(void *arg) 726 { 727 struct psycho_softc *sc = arg; 728 729 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 730 sc->sc_powerpressed = 0; 731 } 732 733 /* 734 * PCI bus support 735 */ 736 737 /* 738 * allocate a PCI chipset tag and set it's cookie. 739 */ 740 static pci_chipset_tag_t 741 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 742 { 743 pci_chipset_tag_t npc; 744 745 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 746 if (npc == NULL) 747 panic("could not allocate pci_chipset_tag_t"); 748 memcpy(npc, pc, sizeof *pc); 749 npc->cookie = pp; 750 npc->rootnode = node; 751 752 return (npc); 753 } 754 755 /* 756 * create extent for free bus space, then allocate assigned regions. 757 */ 758 static struct extent * 759 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 760 { 761 struct psycho_registers *pa = NULL; 762 struct psycho_ranges *pr; 763 struct extent *ex; 764 bus_addr_t baddr, addr; 765 bus_size_t bsize, size; 766 int i, num; 767 768 /* get bus space size */ 769 pr = get_psychorange(pp, ss); 770 if (pr == NULL) { 771 printf("psycho_alloc_extent: get_psychorange failed\n"); 772 return NULL; 773 } 774 baddr = 0x00000000; 775 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 776 777 /* get available lists */ 778 num = 0; 779 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 780 printf("psycho_alloc_extent: no \"available\" property\n"); 781 return NULL; 782 } 783 784 /* create extent */ 785 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 786 EX_NOWAIT); 787 if (ex == NULL) { 788 printf("psycho_alloc_extent: extent_create failed\n"); 789 goto ret; 790 } 791 792 /* allocate assigned regions */ 793 for (i = 0; i < num; i++) 794 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 795 /* allocate bus space */ 796 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 797 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 798 if (extent_alloc_region(ex, baddr, addr - baddr, 799 EX_NOWAIT)) { 800 printf("psycho_alloc_extent: " 801 "extent_alloc_region %" PRIx64 "-%" 802 PRIx64 " failed\n", baddr, addr); 803 extent_destroy(ex); 804 ex = NULL; 805 goto ret; 806 } 807 baddr = addr + size; 808 } 809 /* allocate left region if available */ 810 if (baddr < bsize) 811 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 812 printf("psycho_alloc_extent: extent_alloc_region %" 813 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 814 extent_destroy(ex); 815 ex = NULL; 816 goto ret; 817 } 818 819 #ifdef DEBUG 820 /* print extent */ 821 extent_print(ex); 822 #endif 823 824 ret: 825 /* return extent */ 826 free(pa, M_DEVBUF); 827 return ex; 828 } 829 830 /* 831 * grovel the OBP for various psycho properties 832 */ 833 static void 834 psycho_get_bus_range(int node, int *brp) 835 { 836 int n, error; 837 838 n = 2; 839 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 840 if (error) 841 panic("could not get psycho bus-range, error %d", error); 842 if (n != 2) 843 panic("broken psycho bus-range"); 844 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 845 node, brp[0], brp[1])); 846 } 847 848 static void 849 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 850 { 851 852 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 853 panic("could not get psycho ranges"); 854 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 855 } 856 857 /* 858 * Interrupt handlers. 859 */ 860 861 static int 862 psycho_ue(void *arg) 863 { 864 struct psycho_softc *sc = (struct psycho_softc *)arg; 865 struct psychoreg *regs = sc->sc_regs; 866 long long afsr = regs->psy_ue_afsr; 867 long long afar = regs->psy_ue_afar; 868 long size = PAGE_SIZE<<(sc->sc_is->is_tsbsize); 869 struct iommu_state *is = sc->sc_is; 870 char bits[128]; 871 872 /* 873 * It's uncorrectable. Dump the regs and panic. 874 */ 875 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 876 device_xname(&sc->sc_dev), afar, 877 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 878 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 879 bits, sizeof(bits))); 880 881 /* Sometimes the AFAR points to an IOTSB entry */ 882 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 883 printf("IOVA %llx IOTTE %llx\n", 884 (long long)((afar - is->is_ptsb) * PAGE_SIZE + is->is_dvmabase), 885 (long long)ldxa(afar, ASI_PHYS_CACHED)); 886 } 887 #ifdef DDB 888 Debugger(); 889 #endif 890 regs->psy_ue_afar = 0; 891 regs->psy_ue_afsr = 0; 892 return (1); 893 } 894 static int 895 psycho_ce(void *arg) 896 { 897 struct psycho_softc *sc = (struct psycho_softc *)arg; 898 struct psychoreg *regs = sc->sc_regs; 899 900 /* 901 * It's correctable. Dump the regs and continue. 902 */ 903 904 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 905 device_xname(&sc->sc_dev), 906 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 907 return (1); 908 } 909 static int 910 psycho_bus_a(void *arg) 911 { 912 struct psycho_softc *sc = (struct psycho_softc *)arg; 913 struct psychoreg *regs = sc->sc_regs; 914 915 /* 916 * It's uncorrectable. Dump the regs and panic. 917 */ 918 919 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 920 device_xname(&sc->sc_dev), 921 (long long)regs->psy_pcictl[0].pci_afar, 922 (long long)regs->psy_pcictl[0].pci_afsr); 923 return (1); 924 } 925 static int 926 psycho_bus_b(void *arg) 927 { 928 struct psycho_softc *sc = (struct psycho_softc *)arg; 929 struct psychoreg *regs = sc->sc_regs; 930 931 /* 932 * It's uncorrectable. Dump the regs and panic. 933 */ 934 935 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 936 device_xname(&sc->sc_dev), 937 (long long)regs->psy_pcictl[0].pci_afar, 938 (long long)regs->psy_pcictl[0].pci_afsr); 939 return (1); 940 } 941 942 static int 943 psycho_powerfail(void *arg) 944 { 945 struct psycho_softc *sc = (struct psycho_softc *)arg; 946 947 /* 948 * We lost power. Queue a callback with thread context to 949 * handle all the real work. 950 */ 951 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 952 sc->sc_powerpressed = 1; 953 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 954 } 955 return (1); 956 } 957 958 static 959 int psycho_wakeup(void *arg) 960 { 961 struct psycho_softc *sc = (struct psycho_softc *)arg; 962 963 /* 964 * Gee, we don't really have a framework to deal with this 965 * properly. 966 */ 967 printf("%s: power management wakeup\n", device_xname(&sc->sc_dev)); 968 return (1); 969 } 970 971 972 973 /* 974 * initialise the IOMMU.. 975 */ 976 void 977 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 978 { 979 char *name; 980 struct iommu_state *is = sc->sc_is; 981 uint32_t iobase = -1; 982 int *vdma = NULL; 983 int nitem; 984 985 /* punch in our copies */ 986 is->is_bustag = sc->sc_bustag; 987 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 988 offsetof(struct psychoreg, psy_iommu), 989 sizeof (struct iommureg), 990 &is->is_iommu); 991 992 /* 993 * Separate the men from the boys. Get the `virtual-dma' 994 * property for sabre and use that to make sure the damn 995 * iommu works. 996 * 997 * We could query the `#virtual-dma-size-cells' and 998 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 999 */ 1000 nitem = 0; 1001 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1002 &vdma)) { 1003 /* Damn. Gotta use these values. */ 1004 iobase = vdma[0]; 1005 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1006 switch (vdma[1]) { 1007 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1008 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1009 default: 1010 printf("bogus tsb size %x, using 7\n", vdma[1]); 1011 TSBCASE(7); 1012 } 1013 #undef TSBCASE 1014 } 1015 1016 /* give us a nice name.. */ 1017 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1018 if (name == 0) 1019 panic("couldn't malloc iommu name"); 1020 snprintf(name, 32, "%s dvma", device_xname(&sc->sc_dev)); 1021 1022 iommu_init(name, is, tsbsize, iobase); 1023 } 1024 1025 /* 1026 * below here is bus space and bus DMA support 1027 */ 1028 bus_space_tag_t 1029 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1030 { 1031 struct psycho_softc *sc = pp->pp_sc; 1032 bus_space_tag_t bt; 1033 1034 bt = (bus_space_tag_t) 1035 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 1036 if (bt == NULL) 1037 panic("could not allocate psycho bus tag"); 1038 1039 memset(bt, 0, sizeof *bt); 1040 bt->cookie = pp; 1041 bt->parent = sc->sc_bustag; 1042 bt->type = type; 1043 bt->sparc_bus_map = _psycho_bus_map; 1044 bt->sparc_bus_mmap = psycho_bus_mmap; 1045 bt->sparc_intr_establish = psycho_intr_establish; 1046 return (bt); 1047 } 1048 1049 bus_dma_tag_t 1050 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1051 { 1052 struct psycho_softc *sc = pp->pp_sc; 1053 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1054 1055 dt = (bus_dma_tag_t) 1056 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1057 if (dt == NULL) 1058 panic("could not allocate psycho DMA tag"); 1059 1060 memset(dt, 0, sizeof *dt); 1061 dt->_cookie = pp; 1062 dt->_parent = pdt; 1063 #define PCOPY(x) dt->x = pdt->x 1064 PCOPY(_dmamap_create); 1065 PCOPY(_dmamap_destroy); 1066 dt->_dmamap_load = psycho_dmamap_load; 1067 PCOPY(_dmamap_load_mbuf); 1068 PCOPY(_dmamap_load_uio); 1069 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 1070 dt->_dmamap_unload = psycho_dmamap_unload; 1071 dt->_dmamap_sync = psycho_dmamap_sync; 1072 dt->_dmamem_alloc = psycho_dmamem_alloc; 1073 dt->_dmamem_free = psycho_dmamem_free; 1074 dt->_dmamem_map = psycho_dmamem_map; 1075 dt->_dmamem_unmap = psycho_dmamem_unmap; 1076 PCOPY(_dmamem_mmap); 1077 #undef PCOPY 1078 return (dt); 1079 } 1080 1081 /* 1082 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1083 * PCI physical addresses. 1084 */ 1085 1086 static int 1087 get_childspace(int type) 1088 { 1089 int ss; 1090 1091 switch (type) { 1092 case PCI_CONFIG_BUS_SPACE: 1093 ss = 0x00; 1094 break; 1095 case PCI_IO_BUS_SPACE: 1096 ss = 0x01; 1097 break; 1098 case PCI_MEMORY_BUS_SPACE: 1099 ss = 0x02; 1100 break; 1101 #if 0 1102 /* we don't do 64 bit memory space */ 1103 case PCI_MEMORY64_BUS_SPACE: 1104 ss = 0x03; 1105 break; 1106 #endif 1107 default: 1108 panic("get_childspace: unknown bus type"); 1109 } 1110 1111 return (ss); 1112 } 1113 1114 static struct psycho_ranges * 1115 get_psychorange(struct psycho_pbm *pp, int ss) 1116 { 1117 int i; 1118 1119 for (i = 0; i < pp->pp_nrange; i++) { 1120 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1121 return (&pp->pp_range[i]); 1122 } 1123 /* not found */ 1124 return (NULL); 1125 } 1126 1127 static int 1128 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1129 int flags, vaddr_t unused, bus_space_handle_t *hp) 1130 { 1131 struct psycho_pbm *pp = t->cookie; 1132 struct psycho_softc *sc = pp->pp_sc; 1133 struct psycho_ranges *pr; 1134 bus_addr_t paddr; 1135 int ss; 1136 1137 DPRINTF(PDB_BUSMAP, 1138 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1139 t->type, (unsigned long long)offset, 1140 (unsigned long long)size, flags)); 1141 1142 ss = get_childspace(t->type); 1143 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1144 1145 pr = get_psychorange(pp, ss); 1146 if (pr != NULL) { 1147 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1148 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1149 "space %lx offset %lx paddr %qx\n", 1150 (long)ss, (long)offset, 1151 (unsigned long long)paddr)); 1152 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1153 flags, 0, hp)); 1154 } 1155 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1156 return (EINVAL); 1157 } 1158 1159 static paddr_t 1160 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1161 int flags) 1162 { 1163 bus_addr_t offset = paddr; 1164 struct psycho_pbm *pp = t->cookie; 1165 struct psycho_softc *sc = pp->pp_sc; 1166 struct psycho_ranges *pr; 1167 int ss; 1168 1169 ss = get_childspace(t->type); 1170 1171 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1172 prot, flags, (unsigned long long)paddr)); 1173 1174 pr = get_psychorange(pp, ss); 1175 if (pr != NULL) { 1176 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1177 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1178 "space %lx offset %lx paddr %qx\n", 1179 (long)ss, (long)offset, 1180 (unsigned long long)paddr)); 1181 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1182 prot, flags)); 1183 } 1184 1185 return (-1); 1186 } 1187 1188 /* 1189 * Get a PCI offset address from bus_space_handle_t. 1190 */ 1191 bus_addr_t 1192 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1193 { 1194 struct psycho_pbm *pp = t->cookie; 1195 struct psycho_ranges *pr; 1196 bus_addr_t addr, offset; 1197 vaddr_t va; 1198 int ss; 1199 1200 addr = hp->_ptr; 1201 ss = get_childspace(t->type); 1202 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1203 " cspace %d", t->type, addr, ss)); 1204 1205 pr = get_psychorange(pp, ss); 1206 if (pr != NULL) { 1207 if (!PHYS_ASI(hp->_asi)) { 1208 va = trunc_page((vaddr_t)addr); 1209 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1210 DPRINTF(PDB_BUSMAP, 1211 ("\n pmap_extract FAILED\n")); 1212 return (-1); 1213 } 1214 addr += hp->_ptr & PGOFSET; 1215 } 1216 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1217 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1218 " offset %" PRIx64 "\n", addr, offset)); 1219 return (offset); 1220 } 1221 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1222 return (-1); 1223 } 1224 1225 1226 /* 1227 * install an interrupt handler for a PCI device 1228 */ 1229 void * 1230 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1231 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1232 { 1233 struct psycho_pbm *pp = t->cookie; 1234 struct psycho_softc *sc = pp->pp_sc; 1235 struct intrhand *ih; 1236 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1237 int64_t imap = 0; 1238 int ino; 1239 long vec = INTVEC(ihandle); 1240 1241 ih = (struct intrhand *) 1242 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1243 if (ih == NULL) 1244 return (NULL); 1245 1246 /* 1247 * Hunt through all the interrupt mapping regs to look for our 1248 * interrupt vector. 1249 * 1250 * XXX We only compare INOs rather than IGNs since the firmware may 1251 * not provide the IGN and the IGN is constant for all device on that 1252 * PCI controller. This could cause problems for the FFB/external 1253 * interrupt which has a full vector that can be set arbitrarily. 1254 */ 1255 1256 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1257 ino = INTINO(vec); 1258 DPRINTF(PDB_INTR, (" ino %x", ino)); 1259 1260 /* If the device didn't ask for an IPL, use the one encoded. */ 1261 if (level == IPL_NONE) level = INTLEV(vec); 1262 /* If it still has no level, print a warning and assign IPL 2 */ 1263 if (level == IPL_NONE) { 1264 printf("ERROR: no IPL, setting IPL 2.\n"); 1265 level = 2; 1266 } 1267 1268 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1269 (long)ino, intrlev[ino])); 1270 1271 /* 1272 * First look for PCI interrupts, otherwise the PCI A slot 0 1273 * INTA# interrupt might match an unused non-PCI (obio) 1274 * interrupt. 1275 */ 1276 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1277 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1278 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1279 intrmapptr++, intrclrptr += 4) { 1280 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1281 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1282 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1283 continue; 1284 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1285 intrclrptr += vec & 0x3; 1286 goto found; 1287 } 1288 } 1289 1290 /* Now hunt thru obio. */ 1291 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1292 intrclrptr = &sc->sc_regs->scsi_clr_int; 1293 intrmapptr < &sc->sc_regs->ue_int_map; 1294 intrmapptr++, intrclrptr++) { 1295 if (INTINO(*intrmapptr) == ino) 1296 goto found; 1297 } 1298 1299 /* Finally check the two FFB slots */ 1300 intrclrptr = NULL; /* XXX? */ 1301 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1302 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1303 intrmapptr++) { 1304 if (INTVEC(*intrmapptr) == ino) 1305 goto found; 1306 } 1307 1308 printf("Cannot find interrupt vector %lx\n", vec); 1309 return (NULL); 1310 1311 found: 1312 /* Register the map and clear intr registers */ 1313 ih->ih_map = intrmapptr; 1314 ih->ih_clr = intrclrptr; 1315 1316 ih->ih_fun = handler; 1317 ih->ih_arg = arg; 1318 ih->ih_pil = level; 1319 ih->ih_number = ino | sc->sc_ign; 1320 1321 DPRINTF(PDB_INTR, ( 1322 "; installing handler %p arg %p with ino %u pil %u\n", 1323 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1324 1325 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1326 1327 /* 1328 * Enable the interrupt now we have the handler installed. 1329 * Read the current value as we can't change it besides the 1330 * valid bit so so make sure only this bit is changed. 1331 * 1332 * XXXX --- we really should use bus_space for this. 1333 */ 1334 if (intrmapptr) { 1335 imap = *intrmapptr; 1336 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1337 (unsigned long long)imap)); 1338 1339 /* Enable the interrupt */ 1340 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1341 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1342 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1343 (unsigned long long)imap)); 1344 *intrmapptr = imap; 1345 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1346 (unsigned long long)(imap = *intrmapptr))); 1347 } 1348 if (intrclrptr) { 1349 /* set state to IDLE */ 1350 *intrclrptr = 0; 1351 } 1352 return (ih); 1353 } 1354 1355 /* 1356 * hooks into the iommu dvma calls. 1357 */ 1358 int 1359 psycho_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf, 1360 bus_size_t buflen, struct proc *p, int flags) 1361 { 1362 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1363 1364 return (iommu_dvmamap_load(t, &pp->pp_sb, map, buf, buflen, p, flags)); 1365 } 1366 1367 void 1368 psycho_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map) 1369 { 1370 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1371 1372 iommu_dvmamap_unload(t, &pp->pp_sb, map); 1373 } 1374 1375 int 1376 psycho_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, 1377 bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags) 1378 { 1379 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1380 1381 return (iommu_dvmamap_load_raw(t, &pp->pp_sb, map, segs, nsegs, flags, size)); 1382 } 1383 1384 void 1385 psycho_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1386 bus_size_t len, int ops) 1387 { 1388 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1389 1390 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1391 /* Flush the CPU then the IOMMU */ 1392 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1393 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1394 } 1395 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1396 /* Flush the IOMMU then the CPU */ 1397 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1398 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1399 } 1400 1401 } 1402 1403 int 1404 psycho_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, 1405 bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs, 1406 int flags) 1407 { 1408 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1409 1410 return (iommu_dvmamem_alloc(t, &pp->pp_sb, size, alignment, boundary, 1411 segs, nsegs, rsegs, flags)); 1412 } 1413 1414 void 1415 psycho_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs) 1416 { 1417 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1418 1419 iommu_dvmamem_free(t, &pp->pp_sb, segs, nsegs); 1420 } 1421 1422 int 1423 psycho_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, 1424 size_t size, void **kvap, int flags) 1425 { 1426 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1427 1428 return (iommu_dvmamem_map(t, &pp->pp_sb, segs, nsegs, size, kvap, flags)); 1429 } 1430 1431 void 1432 psycho_dmamem_unmap(bus_dma_tag_t t, void *kva, size_t size) 1433 { 1434 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1435 1436 iommu_dvmamem_unmap(t, &pp->pp_sb, kva, size); 1437 } 1438
Indexes created Wed Sep 24 22:09:59 GMT 2025