psycho.c revision 1.90
1 /* $NetBSD: psycho.c,v 1.90 2008/10/18 03:10:53 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.90 2008/10/18 03:10:53 nakayama Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 int psycho_debug = 0x0; 72 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 73 #else 74 #define DPRINTF(l, s) 75 #endif 76 77 #include <sys/param.h> 78 #include <sys/device.h> 79 #include <sys/errno.h> 80 #include <sys/extent.h> 81 #include <sys/malloc.h> 82 #include <sys/systm.h> 83 #include <sys/time.h> 84 #include <sys/reboot.h> 85 86 #include <uvm/uvm.h> 87 88 #define _SPARC_BUS_DMA_PRIVATE 89 #include <machine/bus.h> 90 #include <machine/autoconf.h> 91 #include <machine/psl.h> 92 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcireg.h> 95 #include <dev/sysmon/sysmon_taskq.h> 96 97 #include <sparc64/dev/iommureg.h> 98 #include <sparc64/dev/iommuvar.h> 99 #include <sparc64/dev/psychoreg.h> 100 #include <sparc64/dev/psychovar.h> 101 102 #include "ioconf.h" 103 104 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 105 pci_chipset_tag_t); 106 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 107 const char *); 108 static void psycho_get_bus_range(int, int *); 109 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 110 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 111 uint64_t *); 112 113 /* Interrupt handlers */ 114 static int psycho_ue(void *); 115 static int psycho_ce(void *); 116 static int psycho_bus_a(void *); 117 static int psycho_bus_b(void *); 118 static int psycho_powerfail(void *); 119 static int psycho_wakeup(void *); 120 121 122 /* IOMMU support */ 123 static void psycho_iommu_init(struct psycho_softc *, int); 124 125 /* 126 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 127 * of the bus DMA support is provided by the iommu dvma controller. 128 */ 129 static int get_childspace(int); 130 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 131 132 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 133 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 134 vaddr_t, bus_space_handle_t *); 135 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 136 void *, void(*)(void)); 137 138 static int psycho_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t, 139 struct proc *, int); 140 static void psycho_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 141 static int psycho_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, 142 bus_dma_segment_t *, int, bus_size_t, int); 143 static void psycho_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 144 bus_size_t, int); 145 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 146 bus_size_t, int); 147 int psycho_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 148 bus_dma_segment_t *, int, int *, int); 149 void psycho_dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int); 150 int psycho_dmamem_map(bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 151 void **, int); 152 void psycho_dmamem_unmap(bus_dma_tag_t, void *, size_t); 153 154 /* base pci_chipset */ 155 extern struct sparc_pci_chipset _sparc_pci_chipset; 156 157 /* power button handlers */ 158 static void psycho_register_power_button(struct psycho_softc *sc); 159 static void psycho_power_button_pressed(void *arg); 160 161 /* 162 * autoconfiguration 163 */ 164 static int psycho_match(struct device *, struct cfdata *, void *); 165 static void psycho_attach(struct device *, struct device *, void *); 166 static int psycho_print(void *aux, const char *p); 167 168 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 169 psycho_match, psycho_attach, NULL, NULL); 170 171 /* 172 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 173 * single PCI bus and does not have a streaming buffer. It often has an APB 174 * (advanced PCI bridge) connected to it, which was designed specifically for 175 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 176 * appears as two "simba"'s underneath the sabre. 177 * 178 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 179 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 180 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 181 * will usually find a "psycho+" since I don't think the original "psycho" 182 * ever shipped, and if it did it would be in the U30. 183 * 184 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 185 * both part of the same IC, they only have a single register space. As such, 186 * they need to be configured together, even though the autoconfiguration will 187 * attach them separately. 188 * 189 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 190 * as pci1 and pci2, although they have been implemented with other PCI bus 191 * numbers on some machines. 192 * 193 * On UltraII machines, there can be any number of "psycho+" ICs, each 194 * providing two PCI buses. 195 * 196 * 197 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 198 * the values of the following interrupts in this order: 199 * 200 * PCI Bus Error (30) 201 * DMA UE (2e) 202 * DMA CE (2f) 203 * Power Fail (25) 204 * 205 * We really should attach handlers for each. 206 * 207 */ 208 209 #define ROM_PCI_NAME "pci" 210 211 struct psycho_names { 212 const char *p_name; 213 int p_type; 214 } psycho_names[] = { 215 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 216 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 217 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 218 { "pci108e,a000", PSYCHO_MODE_SABRE }, 219 { "pci108e,a001", PSYCHO_MODE_SABRE }, 220 { NULL, 0 } 221 }; 222 223 static int 224 psycho_match(struct device *parent, struct cfdata *match, void *aux) 225 { 226 struct mainbus_attach_args *ma = aux; 227 char *model = prom_getpropstring(ma->ma_node, "model"); 228 int i; 229 230 /* match on a name of "pci" and a sabre or a psycho */ 231 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 232 for (i=0; psycho_names[i].p_name; i++) 233 if (strcmp(model, psycho_names[i].p_name) == 0) 234 return (1); 235 236 model = prom_getpropstring(ma->ma_node, "compatible"); 237 for (i=0; psycho_names[i].p_name; i++) 238 if (strcmp(model, psycho_names[i].p_name) == 0) 239 return (1); 240 } 241 return (0); 242 } 243 244 #ifdef DEBUG 245 static void psycho_dump_intmap(struct psycho_softc *sc); 246 static void 247 psycho_dump_intmap(struct psycho_softc *sc) 248 { 249 volatile uint64_t *intrmapptr = NULL; 250 251 printf("psycho_dump_intmap: OBIO\n"); 252 253 for (intrmapptr = &sc->sc_regs->scsi_int_map; 254 intrmapptr < &sc->sc_regs->ue_int_map; 255 intrmapptr++) 256 printf("%p: %llx\n", intrmapptr, 257 (unsigned long long)*intrmapptr); 258 259 printf("\tintmap:pci\n"); 260 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 261 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 262 intrmapptr++) 263 printf("%p: %llx\n", intrmapptr, 264 (unsigned long long)*intrmapptr); 265 266 printf("\tintmap:ffb\n"); 267 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 268 intrmapptr <= &sc->sc_regs->ffb1_int_map; 269 intrmapptr++) 270 printf("%p: %llx\n", intrmapptr, 271 (unsigned long long)*intrmapptr); 272 } 273 #endif 274 275 /* 276 * SUNW,psycho initialisation .. 277 * - find the per-psycho registers 278 * - figure out the IGN. 279 * - find our partner psycho 280 * - configure ourselves 281 * - bus range, bus, 282 * - get interrupt-map and interrupt-map-mask 283 * - setup the chipsets. 284 * - if we're the first of the pair, initialise the IOMMU, otherwise 285 * just copy it's tags and addresses. 286 */ 287 static void 288 psycho_attach(struct device *parent, struct device *self, void *aux) 289 { 290 struct psycho_softc *sc = (struct psycho_softc *)self; 291 struct psycho_softc *osc = NULL; 292 struct psycho_pbm *pp; 293 struct pcibus_attach_args pba; 294 struct mainbus_attach_args *ma = aux; 295 struct psycho_ranges *pr; 296 prop_dictionary_t dict; 297 bus_space_handle_t bh; 298 uint64_t csr, mem_base; 299 int psycho_br[2], n, i; 300 bus_space_handle_t pci_ctl; 301 char *model = prom_getpropstring(ma->ma_node, "model"); 302 303 aprint_normal("\n"); 304 305 sc->sc_node = ma->ma_node; 306 sc->sc_bustag = ma->ma_bustag; 307 sc->sc_dmatag = ma->ma_dmatag; 308 309 /* 310 * Identify the device. 311 */ 312 for (i=0; psycho_names[i].p_name; i++) 313 if (strcmp(model, psycho_names[i].p_name) == 0) { 314 sc->sc_mode = psycho_names[i].p_type; 315 goto found; 316 } 317 318 model = prom_getpropstring(ma->ma_node, "compatible"); 319 for (i=0; psycho_names[i].p_name; i++) 320 if (strcmp(model, psycho_names[i].p_name) == 0) { 321 sc->sc_mode = psycho_names[i].p_type; 322 goto found; 323 } 324 325 panic("unknown psycho model %s", model); 326 found: 327 328 /* 329 * The psycho gets three register banks: 330 * (0) per-PBM configuration and status registers 331 * (1) per-PBM PCI configuration space, containing only the 332 * PBM 256-byte PCI header 333 * (2) the shared psycho configuration registers (struct psychoreg) 334 */ 335 336 /* Register layouts are different. stuupid. */ 337 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 338 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 339 340 if (ma->ma_naddress > 2) { 341 sparc_promaddr_to_handle(sc->sc_bustag, 342 ma->ma_address[2], &sc->sc_bh); 343 sparc_promaddr_to_handle(sc->sc_bustag, 344 ma->ma_address[0], &pci_ctl); 345 346 sc->sc_regs = (struct psychoreg *) 347 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 348 } else if (ma->ma_nreg > 2) { 349 350 /* We need to map this in ourselves. */ 351 if (bus_space_map(sc->sc_bustag, 352 ma->ma_reg[2].ur_paddr, 353 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 354 &sc->sc_bh)) 355 panic("psycho_attach: cannot map regs"); 356 sc->sc_regs = (struct psychoreg *) 357 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 358 359 if (bus_space_map(sc->sc_bustag, 360 ma->ma_reg[0].ur_paddr, 361 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 362 &pci_ctl)) 363 panic("psycho_attach: cannot map ctl"); 364 } else 365 panic("psycho_attach: %d not enough registers", 366 ma->ma_nreg); 367 368 } else { 369 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 370 371 if (ma->ma_naddress) { 372 sparc_promaddr_to_handle(sc->sc_bustag, 373 ma->ma_address[0], &sc->sc_bh); 374 sc->sc_regs = (struct psychoreg *) 375 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 376 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 377 offsetof(struct psychoreg, psy_pcictl), 378 sizeof(struct pci_ctl), &pci_ctl); 379 } else if (ma->ma_nreg) { 380 381 /* We need to map this in ourselves. */ 382 if (bus_space_map(sc->sc_bustag, 383 ma->ma_reg[0].ur_paddr, 384 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 385 &sc->sc_bh)) 386 panic("psycho_attach: cannot map regs"); 387 sc->sc_regs = (struct psychoreg *) 388 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 389 390 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 391 offsetof(struct psychoreg, psy_pcictl), 392 sizeof(struct pci_ctl), &pci_ctl); 393 } else 394 panic("psycho_attach: %d not enough registers", 395 ma->ma_nreg); 396 } 397 398 399 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 400 offsetof(struct psychoreg, psy_csr)); 401 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 402 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 403 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 404 405 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 406 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 407 sc->sc_ign); 408 /* 409 * Match other psycho's that are already configured against 410 * the base physical address. This will be the same for a 411 * pair of devices that share register space. 412 */ 413 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 414 415 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 416 417 if (asc == NULL || asc == sc) 418 /* This entry is not there or it is me */ 419 continue; 420 421 if (asc->sc_basepaddr != sc->sc_basepaddr) 422 /* This is an unrelated psycho */ 423 continue; 424 425 /* Found partner */ 426 osc = asc; 427 break; 428 } 429 430 431 /* Oh, dear. OK, lets get started */ 432 433 /* 434 * Setup the PCI control register 435 */ 436 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 437 offsetof(struct pci_ctl, pci_csr)); 438 csr |= PCICTL_MRLM | 439 PCICTL_ARB_PARK | 440 PCICTL_ERRINTEN | 441 PCICTL_4ENABLE; 442 csr &= ~(PCICTL_SERR | 443 PCICTL_CPU_PRIO | 444 PCICTL_ARB_PRIO | 445 PCICTL_RTRYWAIT); 446 bus_space_write_8(sc->sc_bustag, pci_ctl, 447 offsetof(struct pci_ctl, pci_csr), csr); 448 449 450 /* 451 * Allocate our psycho_pbm 452 */ 453 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 454 M_NOWAIT | M_ZERO); 455 if (pp == NULL) 456 panic("could not allocate psycho pbm"); 457 458 pp->pp_sc = sc; 459 460 /* grab the psycho ranges */ 461 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 462 463 /* get the bus-range for the psycho */ 464 psycho_get_bus_range(sc->sc_node, psycho_br); 465 466 pba.pba_bus = psycho_br[0]; 467 pba.pba_bridgetag = NULL; 468 pp->pp_busmax = psycho_br[1]; 469 470 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 471 aprint_normal("; PCI bus %d", psycho_br[0]); 472 473 pp->pp_pcictl = pci_ctl; 474 475 /* allocate our tags */ 476 pp->pp_memt = psycho_alloc_mem_tag(pp); 477 pp->pp_iot = psycho_alloc_io_tag(pp); 478 pp->pp_dmat = psycho_alloc_dma_tag(pp); 479 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 480 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 481 482 /* allocate a chipset for this */ 483 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 484 485 /* setup the rest of the psycho pbm */ 486 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 487 488 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 489 case 0x2000: 490 pp->pp_id = PSYCHO_PBM_A; 491 break; 492 case 0x4000: 493 pp->pp_id = PSYCHO_PBM_B; 494 break; 495 } 496 497 aprint_normal("\n"); 498 499 /* allocate extents for free bus space */ 500 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 501 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 502 503 #ifdef DEBUG 504 if (psycho_debug & PDB_INTR) 505 psycho_dump_intmap(sc); 506 #endif 507 508 /* 509 * And finally, if we're a sabre or the first of a pair of psycho's to 510 * arrive here, start up the IOMMU and get a config space tag. 511 */ 512 if (osc == NULL) { 513 uint64_t timeo; 514 515 /* 516 * Establish handlers for interesting interrupts.... 517 * 518 * XXX We need to remember these and remove this to support 519 * hotplug on the UPA/FHC bus. 520 * 521 * XXX Not all controllers have these, but installing them 522 * is better than trying to sort through this mess. 523 */ 524 psycho_set_intr(sc, 15, psycho_ue, 525 &sc->sc_regs->ue_int_map, 526 &sc->sc_regs->ue_clr_int); 527 psycho_set_intr(sc, 1, psycho_ce, 528 &sc->sc_regs->ce_int_map, 529 &sc->sc_regs->ce_clr_int); 530 psycho_set_intr(sc, 15, psycho_bus_a, 531 &sc->sc_regs->pciaerr_int_map, 532 &sc->sc_regs->pciaerr_clr_int); 533 psycho_set_intr(sc, 15, psycho_powerfail, 534 &sc->sc_regs->power_int_map, 535 &sc->sc_regs->power_clr_int); 536 psycho_register_power_button(sc); 537 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 538 /* sabre doesn't have these interrupts */ 539 psycho_set_intr(sc, 15, psycho_bus_b, 540 &sc->sc_regs->pciberr_int_map, 541 &sc->sc_regs->pciberr_clr_int); 542 psycho_set_intr(sc, 1, psycho_wakeup, 543 &sc->sc_regs->pwrmgt_int_map, 544 &sc->sc_regs->pwrmgt_clr_int); 545 } 546 547 /* 548 * Apparently a number of machines with psycho and psycho+ 549 * controllers have interrupt latency issues. We'll try 550 * setting the interrupt retry timeout to 0xff which gives us 551 * a retry of 3-6 usec (which is what sysio is set to) for the 552 * moment, which seems to help alleviate this problem. 553 */ 554 timeo = sc->sc_regs->intr_retry_timer; 555 if (timeo > 0xfff) { 556 #ifdef DEBUG 557 printf("decreasing interrupt retry timeout " 558 "from %lx to 0xff\n", (long)timeo); 559 #endif 560 sc->sc_regs->intr_retry_timer = 0xff; 561 } 562 563 /* 564 * Allocate bus node, this contains a prom node per bus. 565 */ 566 pp->pp_busnode = malloc(sizeof(*pp->pp_busnode), M_DEVBUF, 567 M_NOWAIT | M_ZERO); 568 if (pp->pp_busnode == NULL) 569 panic("psycho_attach: malloc pp->pp_busnode"); 570 571 /* 572 * Setup IOMMU and PCI configuration if we're the first 573 * of a pair of psycho's to arrive here. 574 * 575 * We should calculate a TSB size based on amount of RAM 576 * and number of bus controllers and number an type of 577 * child devices. 578 * 579 * For the moment, 32KB should be more than enough. 580 */ 581 sc->sc_is = malloc(sizeof(struct iommu_state), 582 M_DEVBUF, M_NOWAIT); 583 if (sc->sc_is == NULL) 584 panic("psycho_attach: malloc iommu_state"); 585 586 /* Point the strbuf_ctl at the iommu_state */ 587 pp->pp_sb.sb_is = sc->sc_is; 588 589 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 590 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 591 struct strbuf_ctl *sb = &pp->pp_sb; 592 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 593 594 /* 595 * Initialize the strbuf_ctl. 596 * 597 * The flush sync buffer must be 64-byte aligned. 598 */ 599 sb->sb_flush = (void *)(va & ~0x3f); 600 601 bus_space_subregion(sc->sc_bustag, pci_ctl, 602 offsetof(struct pci_ctl, pci_strbuf), 603 sizeof (struct iommu_strbuf), &sb->sb_sb); 604 605 /* Point our iommu at the strbuf_ctl */ 606 sc->sc_is->is_sb[0] = sb; 607 } 608 609 psycho_iommu_init(sc, 2); 610 611 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 612 613 /* 614 * XXX This is a really ugly hack because PCI config space 615 * is explicitly handled with unmapped accesses. 616 */ 617 i = sc->sc_bustag->type; 618 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 619 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 620 0x01000000, 0, &bh)) 621 panic("could not map psycho PCI configuration space"); 622 sc->sc_bustag->type = i; 623 sc->sc_configaddr = bh; 624 } else { 625 /* Share bus numbers with the pair of mine */ 626 pp->pp_busnode = osc->sc_psycho_this->pp_busnode; 627 628 /* Just copy IOMMU state, config tag and address */ 629 sc->sc_is = osc->sc_is; 630 sc->sc_configtag = osc->sc_configtag; 631 sc->sc_configaddr = osc->sc_configaddr; 632 633 /* Point the strbuf_ctl at the iommu_state */ 634 pp->pp_sb.sb_is = sc->sc_is; 635 636 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 637 struct strbuf_ctl *sb = &pp->pp_sb; 638 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 639 640 /* 641 * Initialize the strbuf_ctl. 642 * 643 * The flush sync buffer must be 64-byte aligned. 644 */ 645 sb->sb_flush = (void *)(va & ~0x3f); 646 647 bus_space_subregion(sc->sc_bustag, pci_ctl, 648 offsetof(struct pci_ctl, pci_strbuf), 649 sizeof (struct iommu_strbuf), &sb->sb_sb); 650 651 /* Point our iommu at the strbuf_ctl */ 652 sc->sc_is->is_sb[1] = sb; 653 } 654 iommu_reset(sc->sc_is); 655 } 656 657 dict = device_properties(self); 658 pr = get_psychorange(pp, 2); /* memory range */ 659 #ifdef DEBUG 660 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 661 #endif 662 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 663 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 664 665 /* 666 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 667 */ 668 pba.pba_flags = sc->sc_psycho_this->pp_flags; 669 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 670 pba.pba_dmat64 = NULL; 671 pba.pba_iot = sc->sc_psycho_this->pp_iot; 672 pba.pba_memt = sc->sc_psycho_this->pp_memt; 673 674 config_found_ia(self, "pcibus", &pba, psycho_print); 675 } 676 677 static int 678 psycho_print(void *aux, const char *p) 679 { 680 681 if (p == NULL) 682 return (UNCONF); 683 return (QUIET); 684 } 685 686 static void 687 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 688 uint64_t *mapper, uint64_t *clearer) 689 { 690 struct intrhand *ih; 691 692 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 693 M_DEVBUF, M_NOWAIT); 694 ih->ih_arg = sc; 695 ih->ih_map = mapper; 696 ih->ih_clr = clearer; 697 ih->ih_fun = handler; 698 ih->ih_pil = (1<<ipl); 699 ih->ih_number = INTVEC(*(ih->ih_map)); 700 intr_establish(ipl, ipl != IPL_VM, ih); 701 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 702 } 703 704 /* 705 * power button handlers 706 */ 707 static void 708 psycho_register_power_button(struct psycho_softc *sc) 709 { 710 sysmon_task_queue_init(); 711 712 sc->sc_powerpressed = 0; 713 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 714 if (!sc->sc_smcontext) { 715 aprint_error_dev(&sc->sc_dev, "could not allocate power button context\n"); 716 return; 717 } 718 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 719 sc->sc_smcontext->smpsw_name = device_xname(&sc->sc_dev); 720 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 721 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 722 aprint_error_dev(&sc->sc_dev, "unable to register power button with sysmon\n"); 723 } 724 725 static void 726 psycho_power_button_pressed(void *arg) 727 { 728 struct psycho_softc *sc = arg; 729 730 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 731 sc->sc_powerpressed = 0; 732 } 733 734 /* 735 * PCI bus support 736 */ 737 738 /* 739 * allocate a PCI chipset tag and set it's cookie. 740 */ 741 static pci_chipset_tag_t 742 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 743 { 744 pci_chipset_tag_t npc; 745 746 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 747 if (npc == NULL) 748 panic("could not allocate pci_chipset_tag_t"); 749 memcpy(npc, pc, sizeof *pc); 750 npc->cookie = pp; 751 npc->rootnode = node; 752 753 return (npc); 754 } 755 756 /* 757 * create extent for free bus space, then allocate assigned regions. 758 */ 759 static struct extent * 760 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 761 { 762 struct psycho_registers *pa = NULL; 763 struct psycho_ranges *pr; 764 struct extent *ex; 765 bus_addr_t baddr, addr; 766 bus_size_t bsize, size; 767 int i, num; 768 769 /* get bus space size */ 770 pr = get_psychorange(pp, ss); 771 if (pr == NULL) { 772 printf("psycho_alloc_extent: get_psychorange failed\n"); 773 return NULL; 774 } 775 baddr = 0x00000000; 776 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 777 778 /* get available lists */ 779 num = 0; 780 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 781 printf("psycho_alloc_extent: no \"available\" property\n"); 782 return NULL; 783 } 784 785 /* create extent */ 786 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 787 EX_NOWAIT); 788 if (ex == NULL) { 789 printf("psycho_alloc_extent: extent_create failed\n"); 790 goto ret; 791 } 792 793 /* allocate assigned regions */ 794 for (i = 0; i < num; i++) 795 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 796 /* allocate bus space */ 797 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 798 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 799 if (extent_alloc_region(ex, baddr, addr - baddr, 800 EX_NOWAIT)) { 801 printf("psycho_alloc_extent: " 802 "extent_alloc_region %" PRIx64 "-%" 803 PRIx64 " failed\n", baddr, addr); 804 extent_destroy(ex); 805 ex = NULL; 806 goto ret; 807 } 808 baddr = addr + size; 809 } 810 /* allocate left region if available */ 811 if (baddr < bsize) 812 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 813 printf("psycho_alloc_extent: extent_alloc_region %" 814 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 815 extent_destroy(ex); 816 ex = NULL; 817 goto ret; 818 } 819 820 #ifdef DEBUG 821 /* print extent */ 822 extent_print(ex); 823 #endif 824 825 ret: 826 /* return extent */ 827 free(pa, M_DEVBUF); 828 return ex; 829 } 830 831 /* 832 * grovel the OBP for various psycho properties 833 */ 834 static void 835 psycho_get_bus_range(int node, int *brp) 836 { 837 int n, error; 838 839 n = 2; 840 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 841 if (error) 842 panic("could not get psycho bus-range, error %d", error); 843 if (n != 2) 844 panic("broken psycho bus-range"); 845 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 846 node, brp[0], brp[1])); 847 } 848 849 static void 850 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 851 { 852 853 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 854 panic("could not get psycho ranges"); 855 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 856 } 857 858 /* 859 * Interrupt handlers. 860 */ 861 862 static int 863 psycho_ue(void *arg) 864 { 865 struct psycho_softc *sc = (struct psycho_softc *)arg; 866 struct psychoreg *regs = sc->sc_regs; 867 long long afsr = regs->psy_ue_afsr; 868 long long afar = regs->psy_ue_afar; 869 long size = PAGE_SIZE<<(sc->sc_is->is_tsbsize); 870 struct iommu_state *is = sc->sc_is; 871 char bits[128]; 872 873 /* 874 * It's uncorrectable. Dump the regs and panic. 875 */ 876 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 877 device_xname(&sc->sc_dev), afar, 878 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 879 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 880 bits, sizeof(bits))); 881 882 /* Sometimes the AFAR points to an IOTSB entry */ 883 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 884 printf("IOVA %llx IOTTE %llx\n", 885 (long long)((afar - is->is_ptsb) * PAGE_SIZE + is->is_dvmabase), 886 (long long)ldxa(afar, ASI_PHYS_CACHED)); 887 } 888 #ifdef DDB 889 Debugger(); 890 #endif 891 regs->psy_ue_afar = 0; 892 regs->psy_ue_afsr = 0; 893 return (1); 894 } 895 static int 896 psycho_ce(void *arg) 897 { 898 struct psycho_softc *sc = (struct psycho_softc *)arg; 899 struct psychoreg *regs = sc->sc_regs; 900 901 /* 902 * It's correctable. Dump the regs and continue. 903 */ 904 905 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 906 device_xname(&sc->sc_dev), 907 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 908 return (1); 909 } 910 static int 911 psycho_bus_a(void *arg) 912 { 913 struct psycho_softc *sc = (struct psycho_softc *)arg; 914 struct psychoreg *regs = sc->sc_regs; 915 916 /* 917 * It's uncorrectable. Dump the regs and panic. 918 */ 919 920 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 921 device_xname(&sc->sc_dev), 922 (long long)regs->psy_pcictl[0].pci_afar, 923 (long long)regs->psy_pcictl[0].pci_afsr); 924 return (1); 925 } 926 static int 927 psycho_bus_b(void *arg) 928 { 929 struct psycho_softc *sc = (struct psycho_softc *)arg; 930 struct psychoreg *regs = sc->sc_regs; 931 932 /* 933 * It's uncorrectable. Dump the regs and panic. 934 */ 935 936 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 937 device_xname(&sc->sc_dev), 938 (long long)regs->psy_pcictl[0].pci_afar, 939 (long long)regs->psy_pcictl[0].pci_afsr); 940 return (1); 941 } 942 943 static int 944 psycho_powerfail(void *arg) 945 { 946 struct psycho_softc *sc = (struct psycho_softc *)arg; 947 948 /* 949 * We lost power. Queue a callback with thread context to 950 * handle all the real work. 951 */ 952 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 953 sc->sc_powerpressed = 1; 954 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 955 } 956 return (1); 957 } 958 959 static 960 int psycho_wakeup(void *arg) 961 { 962 struct psycho_softc *sc = (struct psycho_softc *)arg; 963 964 /* 965 * Gee, we don't really have a framework to deal with this 966 * properly. 967 */ 968 printf("%s: power management wakeup\n", device_xname(&sc->sc_dev)); 969 return (1); 970 } 971 972 973 974 /* 975 * initialise the IOMMU.. 976 */ 977 void 978 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 979 { 980 char *name; 981 struct iommu_state *is = sc->sc_is; 982 uint32_t iobase = -1; 983 int *vdma = NULL; 984 int nitem; 985 986 /* punch in our copies */ 987 is->is_bustag = sc->sc_bustag; 988 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 989 offsetof(struct psychoreg, psy_iommu), 990 sizeof (struct iommureg), 991 &is->is_iommu); 992 993 /* 994 * Separate the men from the boys. Get the `virtual-dma' 995 * property for sabre and use that to make sure the damn 996 * iommu works. 997 * 998 * We could query the `#virtual-dma-size-cells' and 999 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1000 */ 1001 nitem = 0; 1002 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1003 &vdma)) { 1004 /* Damn. Gotta use these values. */ 1005 iobase = vdma[0]; 1006 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1007 switch (vdma[1]) { 1008 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1009 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1010 default: 1011 printf("bogus tsb size %x, using 7\n", vdma[1]); 1012 TSBCASE(7); 1013 } 1014 #undef TSBCASE 1015 } 1016 1017 /* give us a nice name.. */ 1018 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1019 if (name == 0) 1020 panic("couldn't malloc iommu name"); 1021 snprintf(name, 32, "%s dvma", device_xname(&sc->sc_dev)); 1022 1023 iommu_init(name, is, tsbsize, iobase); 1024 } 1025 1026 /* 1027 * below here is bus space and bus DMA support 1028 */ 1029 bus_space_tag_t 1030 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1031 { 1032 struct psycho_softc *sc = pp->pp_sc; 1033 bus_space_tag_t bt; 1034 1035 bt = (bus_space_tag_t) 1036 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 1037 if (bt == NULL) 1038 panic("could not allocate psycho bus tag"); 1039 1040 memset(bt, 0, sizeof *bt); 1041 bt->cookie = pp; 1042 bt->parent = sc->sc_bustag; 1043 bt->type = type; 1044 bt->sparc_bus_map = _psycho_bus_map; 1045 bt->sparc_bus_mmap = psycho_bus_mmap; 1046 bt->sparc_intr_establish = psycho_intr_establish; 1047 return (bt); 1048 } 1049 1050 bus_dma_tag_t 1051 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1052 { 1053 struct psycho_softc *sc = pp->pp_sc; 1054 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1055 1056 dt = (bus_dma_tag_t) 1057 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1058 if (dt == NULL) 1059 panic("could not allocate psycho DMA tag"); 1060 1061 memset(dt, 0, sizeof *dt); 1062 dt->_cookie = pp; 1063 dt->_parent = pdt; 1064 #define PCOPY(x) dt->x = pdt->x 1065 PCOPY(_dmamap_create); 1066 PCOPY(_dmamap_destroy); 1067 dt->_dmamap_load = psycho_dmamap_load; 1068 PCOPY(_dmamap_load_mbuf); 1069 PCOPY(_dmamap_load_uio); 1070 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 1071 dt->_dmamap_unload = psycho_dmamap_unload; 1072 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1073 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1074 else 1075 dt->_dmamap_sync = psycho_dmamap_sync; 1076 dt->_dmamem_alloc = psycho_dmamem_alloc; 1077 dt->_dmamem_free = psycho_dmamem_free; 1078 dt->_dmamem_map = psycho_dmamem_map; 1079 dt->_dmamem_unmap = psycho_dmamem_unmap; 1080 PCOPY(_dmamem_mmap); 1081 #undef PCOPY 1082 return (dt); 1083 } 1084 1085 /* 1086 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1087 * PCI physical addresses. 1088 */ 1089 1090 static int 1091 get_childspace(int type) 1092 { 1093 int ss; 1094 1095 switch (type) { 1096 case PCI_CONFIG_BUS_SPACE: 1097 ss = 0x00; 1098 break; 1099 case PCI_IO_BUS_SPACE: 1100 ss = 0x01; 1101 break; 1102 case PCI_MEMORY_BUS_SPACE: 1103 ss = 0x02; 1104 break; 1105 #if 0 1106 /* we don't do 64 bit memory space */ 1107 case PCI_MEMORY64_BUS_SPACE: 1108 ss = 0x03; 1109 break; 1110 #endif 1111 default: 1112 panic("get_childspace: unknown bus type"); 1113 } 1114 1115 return (ss); 1116 } 1117 1118 static struct psycho_ranges * 1119 get_psychorange(struct psycho_pbm *pp, int ss) 1120 { 1121 int i; 1122 1123 for (i = 0; i < pp->pp_nrange; i++) { 1124 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1125 return (&pp->pp_range[i]); 1126 } 1127 /* not found */ 1128 return (NULL); 1129 } 1130 1131 static int 1132 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1133 int flags, vaddr_t unused, bus_space_handle_t *hp) 1134 { 1135 struct psycho_pbm *pp = t->cookie; 1136 struct psycho_softc *sc = pp->pp_sc; 1137 struct psycho_ranges *pr; 1138 bus_addr_t paddr; 1139 int ss; 1140 1141 DPRINTF(PDB_BUSMAP, 1142 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1143 t->type, (unsigned long long)offset, 1144 (unsigned long long)size, flags)); 1145 1146 ss = get_childspace(t->type); 1147 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1148 1149 pr = get_psychorange(pp, ss); 1150 if (pr != NULL) { 1151 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1152 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1153 "space %lx offset %lx paddr %qx\n", 1154 (long)ss, (long)offset, 1155 (unsigned long long)paddr)); 1156 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1157 flags, 0, hp)); 1158 } 1159 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1160 return (EINVAL); 1161 } 1162 1163 static paddr_t 1164 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1165 int flags) 1166 { 1167 bus_addr_t offset = paddr; 1168 struct psycho_pbm *pp = t->cookie; 1169 struct psycho_softc *sc = pp->pp_sc; 1170 struct psycho_ranges *pr; 1171 int ss; 1172 1173 ss = get_childspace(t->type); 1174 1175 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1176 prot, flags, (unsigned long long)paddr)); 1177 1178 pr = get_psychorange(pp, ss); 1179 if (pr != NULL) { 1180 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1181 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1182 "space %lx offset %lx paddr %qx\n", 1183 (long)ss, (long)offset, 1184 (unsigned long long)paddr)); 1185 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1186 prot, flags)); 1187 } 1188 1189 return (-1); 1190 } 1191 1192 /* 1193 * Get a PCI offset address from bus_space_handle_t. 1194 */ 1195 bus_addr_t 1196 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1197 { 1198 struct psycho_pbm *pp = t->cookie; 1199 struct psycho_ranges *pr; 1200 bus_addr_t addr, offset; 1201 vaddr_t va; 1202 int ss; 1203 1204 addr = hp->_ptr; 1205 ss = get_childspace(t->type); 1206 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1207 " cspace %d", t->type, addr, ss)); 1208 1209 pr = get_psychorange(pp, ss); 1210 if (pr != NULL) { 1211 if (!PHYS_ASI(hp->_asi)) { 1212 va = trunc_page((vaddr_t)addr); 1213 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1214 DPRINTF(PDB_BUSMAP, 1215 ("\n pmap_extract FAILED\n")); 1216 return (-1); 1217 } 1218 addr += hp->_ptr & PGOFSET; 1219 } 1220 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1221 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1222 " offset %" PRIx64 "\n", addr, offset)); 1223 return (offset); 1224 } 1225 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1226 return (-1); 1227 } 1228 1229 1230 /* 1231 * install an interrupt handler for a PCI device 1232 */ 1233 void * 1234 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1235 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1236 { 1237 struct psycho_pbm *pp = t->cookie; 1238 struct psycho_softc *sc = pp->pp_sc; 1239 struct intrhand *ih; 1240 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1241 int64_t imap = 0; 1242 int ino; 1243 long vec = INTVEC(ihandle); 1244 1245 ih = (struct intrhand *) 1246 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1247 if (ih == NULL) 1248 return (NULL); 1249 1250 /* 1251 * Hunt through all the interrupt mapping regs to look for our 1252 * interrupt vector. 1253 * 1254 * XXX We only compare INOs rather than IGNs since the firmware may 1255 * not provide the IGN and the IGN is constant for all device on that 1256 * PCI controller. This could cause problems for the FFB/external 1257 * interrupt which has a full vector that can be set arbitrarily. 1258 */ 1259 1260 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1261 ino = INTINO(vec); 1262 DPRINTF(PDB_INTR, (" ino %x", ino)); 1263 1264 /* If the device didn't ask for an IPL, use the one encoded. */ 1265 if (level == IPL_NONE) level = INTLEV(vec); 1266 /* If it still has no level, print a warning and assign IPL 2 */ 1267 if (level == IPL_NONE) { 1268 printf("ERROR: no IPL, setting IPL 2.\n"); 1269 level = 2; 1270 } 1271 1272 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1273 (long)ino, intrlev[ino])); 1274 1275 /* 1276 * First look for PCI interrupts, otherwise the PCI A slot 0 1277 * INTA# interrupt might match an unused non-PCI (obio) 1278 * interrupt. 1279 */ 1280 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1281 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1282 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1283 intrmapptr++, intrclrptr += 4) { 1284 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1285 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1286 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1287 continue; 1288 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1289 intrclrptr += vec & 0x3; 1290 goto found; 1291 } 1292 } 1293 1294 /* Now hunt thru obio. */ 1295 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1296 intrclrptr = &sc->sc_regs->scsi_clr_int; 1297 intrmapptr < &sc->sc_regs->ue_int_map; 1298 intrmapptr++, intrclrptr++) { 1299 if (INTINO(*intrmapptr) == ino) 1300 goto found; 1301 } 1302 1303 /* Finally check the two FFB slots */ 1304 intrclrptr = NULL; /* XXX? */ 1305 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1306 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1307 intrmapptr++) { 1308 if (INTVEC(*intrmapptr) == ino) 1309 goto found; 1310 } 1311 1312 printf("Cannot find interrupt vector %lx\n", vec); 1313 return (NULL); 1314 1315 found: 1316 /* Register the map and clear intr registers */ 1317 ih->ih_map = intrmapptr; 1318 ih->ih_clr = intrclrptr; 1319 1320 ih->ih_fun = handler; 1321 ih->ih_arg = arg; 1322 ih->ih_pil = level; 1323 ih->ih_number = ino | sc->sc_ign; 1324 1325 DPRINTF(PDB_INTR, ( 1326 "; installing handler %p arg %p with ino %u pil %u\n", 1327 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1328 1329 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1330 1331 /* 1332 * Enable the interrupt now we have the handler installed. 1333 * Read the current value as we can't change it besides the 1334 * valid bit so so make sure only this bit is changed. 1335 * 1336 * XXXX --- we really should use bus_space for this. 1337 */ 1338 if (intrmapptr) { 1339 imap = *intrmapptr; 1340 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1341 (unsigned long long)imap)); 1342 1343 /* Enable the interrupt */ 1344 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1345 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1346 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1347 (unsigned long long)imap)); 1348 *intrmapptr = imap; 1349 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1350 (unsigned long long)(imap = *intrmapptr))); 1351 } 1352 if (intrclrptr) { 1353 /* set state to IDLE */ 1354 *intrclrptr = 0; 1355 } 1356 return (ih); 1357 } 1358 1359 /* 1360 * hooks into the iommu dvma calls. 1361 */ 1362 int 1363 psycho_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf, 1364 bus_size_t buflen, struct proc *p, int flags) 1365 { 1366 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1367 1368 return (iommu_dvmamap_load(t, &pp->pp_sb, map, buf, buflen, p, flags)); 1369 } 1370 1371 void 1372 psycho_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map) 1373 { 1374 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1375 1376 iommu_dvmamap_unload(t, &pp->pp_sb, map); 1377 } 1378 1379 int 1380 psycho_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, 1381 bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags) 1382 { 1383 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1384 1385 return (iommu_dvmamap_load_raw(t, &pp->pp_sb, map, segs, nsegs, flags, size)); 1386 } 1387 1388 void 1389 psycho_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1390 bus_size_t len, int ops) 1391 { 1392 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1393 1394 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1395 /* Flush the CPU then the IOMMU */ 1396 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1397 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1398 } 1399 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1400 /* Flush the IOMMU then the CPU */ 1401 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1402 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1403 } 1404 1405 } 1406 1407 int 1408 psycho_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, 1409 bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs, 1410 int flags) 1411 { 1412 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1413 1414 return (iommu_dvmamem_alloc(t, &pp->pp_sb, size, alignment, boundary, 1415 segs, nsegs, rsegs, flags)); 1416 } 1417 1418 void 1419 psycho_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs) 1420 { 1421 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1422 1423 iommu_dvmamem_free(t, &pp->pp_sb, segs, nsegs); 1424 } 1425 1426 int 1427 psycho_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, 1428 size_t size, void **kvap, int flags) 1429 { 1430 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1431 1432 return (iommu_dvmamem_map(t, &pp->pp_sb, segs, nsegs, size, kvap, flags)); 1433 } 1434 1435 void 1436 psycho_dmamem_unmap(bus_dma_tag_t t, void *kva, size_t size) 1437 { 1438 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1439 1440 iommu_dvmamem_unmap(t, &pp->pp_sb, kva, size); 1441 } 1442 1443 /* 1444 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1445 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1446 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1447 */ 1448 static void 1449 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1450 bus_size_t len, int ops) 1451 { 1452 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1453 struct psycho_softc *sc = pp->pp_sc; 1454 1455 if (ops & BUS_DMASYNC_POSTREAD) 1456 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1457 offsetof(struct psychoreg, pci_dma_write_sync)); 1458 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1459 } 1460
Indexes created Fri Sep 26 20:09:58 GMT 2025