psycho.c revision 1.93
1 /* $NetBSD: psycho.c,v 1.93 2008/12/09 13:14:38 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.93 2008/12/09 13:14:38 nakayama Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 int psycho_debug = 0x0; 74 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 75 #else 76 #define DPRINTF(l, s) 77 #endif 78 79 #include <sys/param.h> 80 #include <sys/device.h> 81 #include <sys/errno.h> 82 #include <sys/extent.h> 83 #include <sys/malloc.h> 84 #include <sys/systm.h> 85 #include <sys/time.h> 86 #include <sys/reboot.h> 87 88 #include <uvm/uvm.h> 89 90 #define _SPARC_BUS_DMA_PRIVATE 91 #include <machine/bus.h> 92 #include <machine/autoconf.h> 93 #include <machine/psl.h> 94 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/sysmon/sysmon_taskq.h> 98 99 #include <sparc64/dev/iommureg.h> 100 #include <sparc64/dev/iommuvar.h> 101 #include <sparc64/dev/psychoreg.h> 102 #include <sparc64/dev/psychovar.h> 103 104 #include "ioconf.h" 105 106 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 107 pci_chipset_tag_t); 108 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 109 const char *); 110 static void psycho_get_bus_range(int, int *); 111 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 112 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 113 uint64_t *); 114 115 /* chipset handlers */ 116 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 117 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 118 pcireg_t); 119 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 120 pci_intr_handle_t, 121 int, int (*)(void *), void *); 122 static int psycho_pci_find_ino(struct pci_attach_args *, 123 pci_intr_handle_t *); 124 125 /* Interrupt handlers */ 126 static int psycho_ue(void *); 127 static int psycho_ce(void *); 128 static int psycho_bus_a(void *); 129 static int psycho_bus_b(void *); 130 static int psycho_powerfail(void *); 131 static int psycho_wakeup(void *); 132 133 134 /* IOMMU support */ 135 static void psycho_iommu_init(struct psycho_softc *, int); 136 137 /* 138 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 139 * of the bus DMA support is provided by the iommu dvma controller. 140 */ 141 static int get_childspace(int); 142 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 143 144 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 145 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 146 vaddr_t, bus_space_handle_t *); 147 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 148 void *, void(*)(void)); 149 150 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 151 bus_size_t, int, bus_dmamap_t *); 152 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 153 bus_size_t, int); 154 155 /* base pci_chipset */ 156 extern struct sparc_pci_chipset _sparc_pci_chipset; 157 158 /* power button handlers */ 159 static void psycho_register_power_button(struct psycho_softc *sc); 160 static void psycho_power_button_pressed(void *arg); 161 162 /* 163 * autoconfiguration 164 */ 165 static int psycho_match(struct device *, struct cfdata *, void *); 166 static void psycho_attach(struct device *, struct device *, void *); 167 static int psycho_print(void *aux, const char *p); 168 169 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 170 psycho_match, psycho_attach, NULL, NULL); 171 172 /* 173 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 174 * single PCI bus and does not have a streaming buffer. It often has an APB 175 * (advanced PCI bridge) connected to it, which was designed specifically for 176 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 177 * appears as two "simba"'s underneath the sabre. 178 * 179 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 180 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 181 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 182 * will usually find a "psycho+" since I don't think the original "psycho" 183 * ever shipped, and if it did it would be in the U30. 184 * 185 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 186 * both part of the same IC, they only have a single register space. As such, 187 * they need to be configured together, even though the autoconfiguration will 188 * attach them separately. 189 * 190 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 191 * as pci1 and pci2, although they have been implemented with other PCI bus 192 * numbers on some machines. 193 * 194 * On UltraII machines, there can be any number of "psycho+" ICs, each 195 * providing two PCI buses. 196 * 197 * 198 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 199 * the values of the following interrupts in this order: 200 * 201 * PCI Bus Error (30) 202 * DMA UE (2e) 203 * DMA CE (2f) 204 * Power Fail (25) 205 * 206 * We really should attach handlers for each. 207 * 208 */ 209 210 #define ROM_PCI_NAME "pci" 211 212 struct psycho_names { 213 const char *p_name; 214 int p_type; 215 } psycho_names[] = { 216 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 217 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 218 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 219 { "pci108e,a000", PSYCHO_MODE_SABRE }, 220 { "pci108e,a001", PSYCHO_MODE_SABRE }, 221 { NULL, 0 } 222 }; 223 224 static int 225 psycho_match(struct device *parent, struct cfdata *match, void *aux) 226 { 227 struct mainbus_attach_args *ma = aux; 228 char *model = prom_getpropstring(ma->ma_node, "model"); 229 int i; 230 231 /* match on a name of "pci" and a sabre or a psycho */ 232 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 233 for (i=0; psycho_names[i].p_name; i++) 234 if (strcmp(model, psycho_names[i].p_name) == 0) 235 return (1); 236 237 model = prom_getpropstring(ma->ma_node, "compatible"); 238 for (i=0; psycho_names[i].p_name; i++) 239 if (strcmp(model, psycho_names[i].p_name) == 0) 240 return (1); 241 } 242 return (0); 243 } 244 245 #ifdef DEBUG 246 static void psycho_dump_intmap(struct psycho_softc *sc); 247 static void 248 psycho_dump_intmap(struct psycho_softc *sc) 249 { 250 volatile uint64_t *intrmapptr = NULL; 251 252 printf("psycho_dump_intmap: OBIO\n"); 253 254 for (intrmapptr = &sc->sc_regs->scsi_int_map; 255 intrmapptr < &sc->sc_regs->ue_int_map; 256 intrmapptr++) 257 printf("%p: %llx\n", intrmapptr, 258 (unsigned long long)*intrmapptr); 259 260 printf("\tintmap:pci\n"); 261 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 262 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 263 intrmapptr++) 264 printf("%p: %llx\n", intrmapptr, 265 (unsigned long long)*intrmapptr); 266 267 printf("\tintmap:ffb\n"); 268 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 269 intrmapptr <= &sc->sc_regs->ffb1_int_map; 270 intrmapptr++) 271 printf("%p: %llx\n", intrmapptr, 272 (unsigned long long)*intrmapptr); 273 } 274 #endif 275 276 /* 277 * SUNW,psycho initialisation .. 278 * - find the per-psycho registers 279 * - figure out the IGN. 280 * - find our partner psycho 281 * - configure ourselves 282 * - bus range, bus, 283 * - get interrupt-map and interrupt-map-mask 284 * - setup the chipsets. 285 * - if we're the first of the pair, initialise the IOMMU, otherwise 286 * just copy it's tags and addresses. 287 */ 288 static void 289 psycho_attach(struct device *parent, struct device *self, void *aux) 290 { 291 struct psycho_softc *sc = (struct psycho_softc *)self; 292 struct psycho_softc *osc = NULL; 293 struct psycho_pbm *pp; 294 struct pcibus_attach_args pba; 295 struct mainbus_attach_args *ma = aux; 296 struct psycho_ranges *pr; 297 prop_dictionary_t dict; 298 bus_space_handle_t bh; 299 uint64_t csr, mem_base; 300 int psycho_br[2], n, i; 301 bus_space_handle_t pci_ctl; 302 char *model = prom_getpropstring(ma->ma_node, "model"); 303 304 aprint_normal("\n"); 305 306 sc->sc_node = ma->ma_node; 307 sc->sc_bustag = ma->ma_bustag; 308 sc->sc_dmatag = ma->ma_dmatag; 309 310 /* 311 * Identify the device. 312 */ 313 for (i=0; psycho_names[i].p_name; i++) 314 if (strcmp(model, psycho_names[i].p_name) == 0) { 315 sc->sc_mode = psycho_names[i].p_type; 316 goto found; 317 } 318 319 model = prom_getpropstring(ma->ma_node, "compatible"); 320 for (i=0; psycho_names[i].p_name; i++) 321 if (strcmp(model, psycho_names[i].p_name) == 0) { 322 sc->sc_mode = psycho_names[i].p_type; 323 goto found; 324 } 325 326 panic("unknown psycho model %s", model); 327 found: 328 329 /* 330 * The psycho gets three register banks: 331 * (0) per-PBM configuration and status registers 332 * (1) per-PBM PCI configuration space, containing only the 333 * PBM 256-byte PCI header 334 * (2) the shared psycho configuration registers (struct psychoreg) 335 */ 336 337 /* Register layouts are different. stuupid. */ 338 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 339 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 340 341 if (ma->ma_naddress > 2) { 342 sparc_promaddr_to_handle(sc->sc_bustag, 343 ma->ma_address[2], &sc->sc_bh); 344 sparc_promaddr_to_handle(sc->sc_bustag, 345 ma->ma_address[0], &pci_ctl); 346 347 sc->sc_regs = (struct psychoreg *) 348 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 349 } else if (ma->ma_nreg > 2) { 350 351 /* We need to map this in ourselves. */ 352 if (bus_space_map(sc->sc_bustag, 353 ma->ma_reg[2].ur_paddr, 354 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 355 &sc->sc_bh)) 356 panic("psycho_attach: cannot map regs"); 357 sc->sc_regs = (struct psychoreg *) 358 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 359 360 if (bus_space_map(sc->sc_bustag, 361 ma->ma_reg[0].ur_paddr, 362 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 363 &pci_ctl)) 364 panic("psycho_attach: cannot map ctl"); 365 } else 366 panic("psycho_attach: %d not enough registers", 367 ma->ma_nreg); 368 369 } else { 370 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 371 372 if (ma->ma_naddress) { 373 sparc_promaddr_to_handle(sc->sc_bustag, 374 ma->ma_address[0], &sc->sc_bh); 375 sc->sc_regs = (struct psychoreg *) 376 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 377 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 378 offsetof(struct psychoreg, psy_pcictl), 379 sizeof(struct pci_ctl), &pci_ctl); 380 } else if (ma->ma_nreg) { 381 382 /* We need to map this in ourselves. */ 383 if (bus_space_map(sc->sc_bustag, 384 ma->ma_reg[0].ur_paddr, 385 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 386 &sc->sc_bh)) 387 panic("psycho_attach: cannot map regs"); 388 sc->sc_regs = (struct psychoreg *) 389 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 390 391 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 392 offsetof(struct psychoreg, psy_pcictl), 393 sizeof(struct pci_ctl), &pci_ctl); 394 } else 395 panic("psycho_attach: %d not enough registers", 396 ma->ma_nreg); 397 } 398 399 400 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 401 offsetof(struct psychoreg, psy_csr)); 402 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 403 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 404 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 405 406 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 407 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 408 sc->sc_ign); 409 /* 410 * Match other psycho's that are already configured against 411 * the base physical address. This will be the same for a 412 * pair of devices that share register space. 413 */ 414 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 415 416 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 417 418 if (asc == NULL || asc == sc) 419 /* This entry is not there or it is me */ 420 continue; 421 422 if (asc->sc_basepaddr != sc->sc_basepaddr) 423 /* This is an unrelated psycho */ 424 continue; 425 426 /* Found partner */ 427 osc = asc; 428 break; 429 } 430 431 432 /* Oh, dear. OK, lets get started */ 433 434 /* 435 * Setup the PCI control register 436 */ 437 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 438 offsetof(struct pci_ctl, pci_csr)); 439 csr |= PCICTL_MRLM | 440 PCICTL_ARB_PARK | 441 PCICTL_ERRINTEN | 442 PCICTL_4ENABLE; 443 csr &= ~(PCICTL_SERR | 444 PCICTL_CPU_PRIO | 445 PCICTL_ARB_PRIO | 446 PCICTL_RTRYWAIT); 447 bus_space_write_8(sc->sc_bustag, pci_ctl, 448 offsetof(struct pci_ctl, pci_csr), csr); 449 450 451 /* 452 * Allocate our psycho_pbm 453 */ 454 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 455 M_NOWAIT | M_ZERO); 456 if (pp == NULL) 457 panic("could not allocate psycho pbm"); 458 459 pp->pp_sc = sc; 460 461 /* grab the psycho ranges */ 462 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 463 464 /* get the bus-range for the psycho */ 465 psycho_get_bus_range(sc->sc_node, psycho_br); 466 467 pba.pba_bus = psycho_br[0]; 468 pba.pba_bridgetag = NULL; 469 470 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 471 aprint_normal("; PCI bus %d", psycho_br[0]); 472 473 pp->pp_pcictl = pci_ctl; 474 475 /* allocate our tags */ 476 pp->pp_memt = psycho_alloc_mem_tag(pp); 477 pp->pp_iot = psycho_alloc_io_tag(pp); 478 pp->pp_dmat = psycho_alloc_dma_tag(pp); 479 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 480 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 481 482 /* allocate a chipset for this */ 483 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 484 pp->pp_pc->spc_busmax = psycho_br[1]; 485 486 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 487 case 0x2000: 488 pp->pp_id = PSYCHO_PBM_A; 489 break; 490 case 0x4000: 491 pp->pp_id = PSYCHO_PBM_B; 492 break; 493 } 494 495 aprint_normal("\n"); 496 497 /* allocate extents for free bus space */ 498 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 499 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 500 501 #ifdef DEBUG 502 if (psycho_debug & PDB_INTR) 503 psycho_dump_intmap(sc); 504 #endif 505 506 /* 507 * And finally, if we're a sabre or the first of a pair of psycho's to 508 * arrive here, start up the IOMMU and get a config space tag. 509 */ 510 if (osc == NULL) { 511 uint64_t timeo; 512 513 /* 514 * Establish handlers for interesting interrupts.... 515 * 516 * XXX We need to remember these and remove this to support 517 * hotplug on the UPA/FHC bus. 518 * 519 * XXX Not all controllers have these, but installing them 520 * is better than trying to sort through this mess. 521 */ 522 psycho_set_intr(sc, 15, psycho_ue, 523 &sc->sc_regs->ue_int_map, 524 &sc->sc_regs->ue_clr_int); 525 psycho_set_intr(sc, 1, psycho_ce, 526 &sc->sc_regs->ce_int_map, 527 &sc->sc_regs->ce_clr_int); 528 psycho_set_intr(sc, 15, psycho_bus_a, 529 &sc->sc_regs->pciaerr_int_map, 530 &sc->sc_regs->pciaerr_clr_int); 531 psycho_set_intr(sc, 15, psycho_powerfail, 532 &sc->sc_regs->power_int_map, 533 &sc->sc_regs->power_clr_int); 534 psycho_register_power_button(sc); 535 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 536 /* sabre doesn't have these interrupts */ 537 psycho_set_intr(sc, 15, psycho_bus_b, 538 &sc->sc_regs->pciberr_int_map, 539 &sc->sc_regs->pciberr_clr_int); 540 psycho_set_intr(sc, 1, psycho_wakeup, 541 &sc->sc_regs->pwrmgt_int_map, 542 &sc->sc_regs->pwrmgt_clr_int); 543 } 544 545 /* 546 * Apparently a number of machines with psycho and psycho+ 547 * controllers have interrupt latency issues. We'll try 548 * setting the interrupt retry timeout to 0xff which gives us 549 * a retry of 3-6 usec (which is what sysio is set to) for the 550 * moment, which seems to help alleviate this problem. 551 */ 552 timeo = sc->sc_regs->intr_retry_timer; 553 if (timeo > 0xfff) { 554 #ifdef DEBUG 555 printf("decreasing interrupt retry timeout " 556 "from %lx to 0xff\n", (long)timeo); 557 #endif 558 sc->sc_regs->intr_retry_timer = 0xff; 559 } 560 561 /* 562 * Allocate bus node, this contains a prom node per bus. 563 */ 564 pp->pp_pc->spc_busnode = 565 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 566 M_NOWAIT | M_ZERO); 567 if (pp->pp_pc->spc_busnode == NULL) 568 panic("psycho_attach: malloc busnode"); 569 570 /* 571 * Setup IOMMU and PCI configuration if we're the first 572 * of a pair of psycho's to arrive here. 573 * 574 * We should calculate a TSB size based on amount of RAM 575 * and number of bus controllers and number an type of 576 * child devices. 577 * 578 * For the moment, 32KB should be more than enough. 579 */ 580 sc->sc_is = malloc(sizeof(struct iommu_state), 581 M_DEVBUF, M_NOWAIT); 582 if (sc->sc_is == NULL) 583 panic("psycho_attach: malloc iommu_state"); 584 585 /* Point the strbuf_ctl at the iommu_state */ 586 pp->pp_sb.sb_is = sc->sc_is; 587 588 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 589 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 590 struct strbuf_ctl *sb = &pp->pp_sb; 591 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 592 593 /* 594 * Initialize the strbuf_ctl. 595 * 596 * The flush sync buffer must be 64-byte aligned. 597 */ 598 sb->sb_flush = (void *)(va & ~0x3f); 599 600 bus_space_subregion(sc->sc_bustag, pci_ctl, 601 offsetof(struct pci_ctl, pci_strbuf), 602 sizeof (struct iommu_strbuf), &sb->sb_sb); 603 604 /* Point our iommu at the strbuf_ctl */ 605 sc->sc_is->is_sb[0] = sb; 606 } 607 608 psycho_iommu_init(sc, 2); 609 610 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 611 612 /* 613 * XXX This is a really ugly hack because PCI config space 614 * is explicitly handled with unmapped accesses. 615 */ 616 i = sc->sc_bustag->type; 617 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 618 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 619 0x01000000, 0, &bh)) 620 panic("could not map psycho PCI configuration space"); 621 sc->sc_bustag->type = i; 622 sc->sc_configaddr = bh; 623 } else { 624 /* Share bus numbers with the pair of mine */ 625 pp->pp_pc->spc_busnode = 626 osc->sc_psycho_this->pp_pc->spc_busnode; 627 628 /* Just copy IOMMU state, config tag and address */ 629 sc->sc_is = osc->sc_is; 630 sc->sc_configtag = osc->sc_configtag; 631 sc->sc_configaddr = osc->sc_configaddr; 632 633 /* Point the strbuf_ctl at the iommu_state */ 634 pp->pp_sb.sb_is = sc->sc_is; 635 636 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 637 struct strbuf_ctl *sb = &pp->pp_sb; 638 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 639 640 /* 641 * Initialize the strbuf_ctl. 642 * 643 * The flush sync buffer must be 64-byte aligned. 644 */ 645 sb->sb_flush = (void *)(va & ~0x3f); 646 647 bus_space_subregion(sc->sc_bustag, pci_ctl, 648 offsetof(struct pci_ctl, pci_strbuf), 649 sizeof (struct iommu_strbuf), &sb->sb_sb); 650 651 /* Point our iommu at the strbuf_ctl */ 652 sc->sc_is->is_sb[1] = sb; 653 } 654 iommu_reset(sc->sc_is); 655 } 656 657 dict = device_properties(self); 658 pr = get_psychorange(pp, 2); /* memory range */ 659 #ifdef DEBUG 660 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 661 #endif 662 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 663 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 664 665 /* 666 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 667 */ 668 pba.pba_flags = sc->sc_psycho_this->pp_flags; 669 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 670 pba.pba_dmat64 = NULL; 671 pba.pba_iot = sc->sc_psycho_this->pp_iot; 672 pba.pba_memt = sc->sc_psycho_this->pp_memt; 673 pba.pba_pc = pp->pp_pc; 674 675 config_found_ia(self, "pcibus", &pba, psycho_print); 676 } 677 678 static int 679 psycho_print(void *aux, const char *p) 680 { 681 682 if (p == NULL) 683 return (UNCONF); 684 return (QUIET); 685 } 686 687 static void 688 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 689 uint64_t *mapper, uint64_t *clearer) 690 { 691 struct intrhand *ih; 692 693 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 694 M_DEVBUF, M_NOWAIT); 695 ih->ih_arg = sc; 696 ih->ih_map = mapper; 697 ih->ih_clr = clearer; 698 ih->ih_fun = handler; 699 ih->ih_pil = (1<<ipl); 700 ih->ih_number = INTVEC(*(ih->ih_map)); 701 intr_establish(ipl, ipl != IPL_VM, ih); 702 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 703 } 704 705 /* 706 * power button handlers 707 */ 708 static void 709 psycho_register_power_button(struct psycho_softc *sc) 710 { 711 sysmon_task_queue_init(); 712 713 sc->sc_powerpressed = 0; 714 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 715 if (!sc->sc_smcontext) { 716 aprint_error_dev(&sc->sc_dev, "could not allocate power button context\n"); 717 return; 718 } 719 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 720 sc->sc_smcontext->smpsw_name = device_xname(&sc->sc_dev); 721 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 722 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 723 aprint_error_dev(&sc->sc_dev, "unable to register power button with sysmon\n"); 724 } 725 726 static void 727 psycho_power_button_pressed(void *arg) 728 { 729 struct psycho_softc *sc = arg; 730 731 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 732 sc->sc_powerpressed = 0; 733 } 734 735 /* 736 * PCI bus support 737 */ 738 739 /* 740 * allocate a PCI chipset tag and set it's cookie. 741 */ 742 static pci_chipset_tag_t 743 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 744 { 745 pci_chipset_tag_t npc; 746 747 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 748 if (npc == NULL) 749 panic("could not allocate pci_chipset_tag_t"); 750 memcpy(npc, pc, sizeof *pc); 751 npc->cookie = pp; 752 npc->rootnode = node; 753 npc->spc_conf_read = psycho_pci_conf_read; 754 npc->spc_conf_write = psycho_pci_conf_write; 755 npc->spc_intr_establish = psycho_pci_intr_establish; 756 npc->spc_find_ino = psycho_pci_find_ino; 757 758 return (npc); 759 } 760 761 /* 762 * create extent for free bus space, then allocate assigned regions. 763 */ 764 static struct extent * 765 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 766 { 767 struct psycho_registers *pa = NULL; 768 struct psycho_ranges *pr; 769 struct extent *ex; 770 bus_addr_t baddr, addr; 771 bus_size_t bsize, size; 772 int i, num; 773 774 /* get bus space size */ 775 pr = get_psychorange(pp, ss); 776 if (pr == NULL) { 777 printf("psycho_alloc_extent: get_psychorange failed\n"); 778 return NULL; 779 } 780 baddr = 0x00000000; 781 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 782 783 /* get available lists */ 784 num = 0; 785 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 786 printf("psycho_alloc_extent: no \"available\" property\n"); 787 return NULL; 788 } 789 790 /* create extent */ 791 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 792 EX_NOWAIT); 793 if (ex == NULL) { 794 printf("psycho_alloc_extent: extent_create failed\n"); 795 goto ret; 796 } 797 798 /* allocate assigned regions */ 799 for (i = 0; i < num; i++) 800 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 801 /* allocate bus space */ 802 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 803 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 804 if (extent_alloc_region(ex, baddr, addr - baddr, 805 EX_NOWAIT)) { 806 printf("psycho_alloc_extent: " 807 "extent_alloc_region %" PRIx64 "-%" 808 PRIx64 " failed\n", baddr, addr); 809 extent_destroy(ex); 810 ex = NULL; 811 goto ret; 812 } 813 baddr = addr + size; 814 } 815 /* allocate left region if available */ 816 if (baddr < bsize) 817 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 818 printf("psycho_alloc_extent: extent_alloc_region %" 819 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 820 extent_destroy(ex); 821 ex = NULL; 822 goto ret; 823 } 824 825 #ifdef DEBUG 826 /* print extent */ 827 extent_print(ex); 828 #endif 829 830 ret: 831 /* return extent */ 832 free(pa, M_DEVBUF); 833 return ex; 834 } 835 836 /* 837 * grovel the OBP for various psycho properties 838 */ 839 static void 840 psycho_get_bus_range(int node, int *brp) 841 { 842 int n, error; 843 844 n = 2; 845 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 846 if (error) 847 panic("could not get psycho bus-range, error %d", error); 848 if (n != 2) 849 panic("broken psycho bus-range"); 850 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 851 node, brp[0], brp[1])); 852 } 853 854 static void 855 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 856 { 857 858 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 859 panic("could not get psycho ranges"); 860 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 861 } 862 863 /* 864 * Interrupt handlers. 865 */ 866 867 static int 868 psycho_ue(void *arg) 869 { 870 struct psycho_softc *sc = (struct psycho_softc *)arg; 871 struct psychoreg *regs = sc->sc_regs; 872 long long afsr = regs->psy_ue_afsr; 873 long long afar = regs->psy_ue_afar; 874 long size = PAGE_SIZE<<(sc->sc_is->is_tsbsize); 875 struct iommu_state *is = sc->sc_is; 876 char bits[128]; 877 878 /* 879 * It's uncorrectable. Dump the regs and panic. 880 */ 881 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 882 device_xname(&sc->sc_dev), afar, 883 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 884 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 885 bits, sizeof(bits))); 886 887 /* Sometimes the AFAR points to an IOTSB entry */ 888 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 889 printf("IOVA %llx IOTTE %llx\n", 890 (long long)((afar - is->is_ptsb) * PAGE_SIZE + is->is_dvmabase), 891 (long long)ldxa(afar, ASI_PHYS_CACHED)); 892 } 893 #ifdef DDB 894 Debugger(); 895 #endif 896 regs->psy_ue_afar = 0; 897 regs->psy_ue_afsr = 0; 898 return (1); 899 } 900 901 static int 902 psycho_ce(void *arg) 903 { 904 struct psycho_softc *sc = (struct psycho_softc *)arg; 905 struct psychoreg *regs = sc->sc_regs; 906 907 /* 908 * It's correctable. Dump the regs and continue. 909 */ 910 911 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 912 device_xname(&sc->sc_dev), 913 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 914 return (1); 915 } 916 917 static int 918 psycho_bus_a(void *arg) 919 { 920 struct psycho_softc *sc = (struct psycho_softc *)arg; 921 struct psychoreg *regs = sc->sc_regs; 922 923 /* 924 * It's uncorrectable. Dump the regs and panic. 925 */ 926 927 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 928 device_xname(&sc->sc_dev), 929 (long long)regs->psy_pcictl[0].pci_afar, 930 (long long)regs->psy_pcictl[0].pci_afsr); 931 return (1); 932 } 933 934 static int 935 psycho_bus_b(void *arg) 936 { 937 struct psycho_softc *sc = (struct psycho_softc *)arg; 938 struct psychoreg *regs = sc->sc_regs; 939 940 /* 941 * It's uncorrectable. Dump the regs and panic. 942 */ 943 944 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 945 device_xname(&sc->sc_dev), 946 (long long)regs->psy_pcictl[0].pci_afar, 947 (long long)regs->psy_pcictl[0].pci_afsr); 948 return (1); 949 } 950 951 static int 952 psycho_powerfail(void *arg) 953 { 954 struct psycho_softc *sc = (struct psycho_softc *)arg; 955 956 /* 957 * We lost power. Queue a callback with thread context to 958 * handle all the real work. 959 */ 960 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 961 sc->sc_powerpressed = 1; 962 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 963 } 964 return (1); 965 } 966 967 static 968 int psycho_wakeup(void *arg) 969 { 970 struct psycho_softc *sc = (struct psycho_softc *)arg; 971 972 /* 973 * Gee, we don't really have a framework to deal with this 974 * properly. 975 */ 976 printf("%s: power management wakeup\n", device_xname(&sc->sc_dev)); 977 return (1); 978 } 979 980 981 /* 982 * initialise the IOMMU.. 983 */ 984 void 985 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 986 { 987 char *name; 988 struct iommu_state *is = sc->sc_is; 989 uint32_t iobase = -1; 990 int *vdma = NULL; 991 int nitem; 992 993 /* punch in our copies */ 994 is->is_bustag = sc->sc_bustag; 995 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 996 offsetof(struct psychoreg, psy_iommu), 997 sizeof (struct iommureg), 998 &is->is_iommu); 999 1000 /* 1001 * Separate the men from the boys. Get the `virtual-dma' 1002 * property for sabre and use that to make sure the damn 1003 * iommu works. 1004 * 1005 * We could query the `#virtual-dma-size-cells' and 1006 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1007 */ 1008 nitem = 0; 1009 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1010 &vdma)) { 1011 /* Damn. Gotta use these values. */ 1012 iobase = vdma[0]; 1013 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1014 switch (vdma[1]) { 1015 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1016 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1017 default: 1018 printf("bogus tsb size %x, using 7\n", vdma[1]); 1019 TSBCASE(7); 1020 } 1021 #undef TSBCASE 1022 } 1023 1024 /* give us a nice name.. */ 1025 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1026 if (name == 0) 1027 panic("couldn't malloc iommu name"); 1028 snprintf(name, 32, "%s dvma", device_xname(&sc->sc_dev)); 1029 1030 iommu_init(name, is, tsbsize, iobase); 1031 } 1032 1033 /* 1034 * below here is bus space and bus DMA support 1035 */ 1036 bus_space_tag_t 1037 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1038 { 1039 struct psycho_softc *sc = pp->pp_sc; 1040 bus_space_tag_t bt; 1041 1042 bt = (bus_space_tag_t) 1043 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 1044 if (bt == NULL) 1045 panic("could not allocate psycho bus tag"); 1046 1047 memset(bt, 0, sizeof *bt); 1048 bt->cookie = pp; 1049 bt->parent = sc->sc_bustag; 1050 bt->type = type; 1051 bt->sparc_bus_map = _psycho_bus_map; 1052 bt->sparc_bus_mmap = psycho_bus_mmap; 1053 bt->sparc_intr_establish = psycho_intr_establish; 1054 return (bt); 1055 } 1056 1057 bus_dma_tag_t 1058 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1059 { 1060 struct psycho_softc *sc = pp->pp_sc; 1061 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1062 1063 dt = (bus_dma_tag_t) 1064 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1065 if (dt == NULL) 1066 panic("could not allocate psycho DMA tag"); 1067 1068 memset(dt, 0, sizeof *dt); 1069 dt->_cookie = pp; 1070 dt->_parent = pdt; 1071 #define PCOPY(x) dt->x = pdt->x 1072 dt->_dmamap_create = psycho_dmamap_create; 1073 PCOPY(_dmamap_destroy); 1074 dt->_dmamap_load = iommu_dvmamap_load; 1075 PCOPY(_dmamap_load_mbuf); 1076 PCOPY(_dmamap_load_uio); 1077 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1078 dt->_dmamap_unload = iommu_dvmamap_unload; 1079 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1080 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1081 else 1082 dt->_dmamap_sync = iommu_dvmamap_sync; 1083 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1084 dt->_dmamem_free = iommu_dvmamem_free; 1085 dt->_dmamem_map = iommu_dvmamem_map; 1086 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1087 PCOPY(_dmamem_mmap); 1088 #undef PCOPY 1089 return (dt); 1090 } 1091 1092 /* 1093 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1094 * PCI physical addresses. 1095 */ 1096 1097 static int 1098 get_childspace(int type) 1099 { 1100 int ss; 1101 1102 switch (type) { 1103 case PCI_CONFIG_BUS_SPACE: 1104 ss = 0x00; 1105 break; 1106 case PCI_IO_BUS_SPACE: 1107 ss = 0x01; 1108 break; 1109 case PCI_MEMORY_BUS_SPACE: 1110 ss = 0x02; 1111 break; 1112 #if 0 1113 /* we don't do 64 bit memory space */ 1114 case PCI_MEMORY64_BUS_SPACE: 1115 ss = 0x03; 1116 break; 1117 #endif 1118 default: 1119 panic("get_childspace: unknown bus type"); 1120 } 1121 1122 return (ss); 1123 } 1124 1125 static struct psycho_ranges * 1126 get_psychorange(struct psycho_pbm *pp, int ss) 1127 { 1128 int i; 1129 1130 for (i = 0; i < pp->pp_nrange; i++) { 1131 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1132 return (&pp->pp_range[i]); 1133 } 1134 /* not found */ 1135 return (NULL); 1136 } 1137 1138 static int 1139 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1140 int flags, vaddr_t unused, bus_space_handle_t *hp) 1141 { 1142 struct psycho_pbm *pp = t->cookie; 1143 struct psycho_softc *sc = pp->pp_sc; 1144 struct psycho_ranges *pr; 1145 bus_addr_t paddr; 1146 int ss; 1147 1148 DPRINTF(PDB_BUSMAP, 1149 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1150 t->type, (unsigned long long)offset, 1151 (unsigned long long)size, flags)); 1152 1153 ss = get_childspace(t->type); 1154 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1155 1156 pr = get_psychorange(pp, ss); 1157 if (pr != NULL) { 1158 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1159 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1160 "space %lx offset %lx paddr %qx\n", 1161 (long)ss, (long)offset, 1162 (unsigned long long)paddr)); 1163 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1164 flags, 0, hp)); 1165 } 1166 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1167 return (EINVAL); 1168 } 1169 1170 static paddr_t 1171 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1172 int flags) 1173 { 1174 bus_addr_t offset = paddr; 1175 struct psycho_pbm *pp = t->cookie; 1176 struct psycho_softc *sc = pp->pp_sc; 1177 struct psycho_ranges *pr; 1178 int ss; 1179 1180 ss = get_childspace(t->type); 1181 1182 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1183 prot, flags, (unsigned long long)paddr)); 1184 1185 pr = get_psychorange(pp, ss); 1186 if (pr != NULL) { 1187 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1188 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1189 "space %lx offset %lx paddr %qx\n", 1190 (long)ss, (long)offset, 1191 (unsigned long long)paddr)); 1192 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1193 prot, flags)); 1194 } 1195 1196 return (-1); 1197 } 1198 1199 /* 1200 * Get a PCI offset address from bus_space_handle_t. 1201 */ 1202 bus_addr_t 1203 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1204 { 1205 struct psycho_pbm *pp = t->cookie; 1206 struct psycho_ranges *pr; 1207 bus_addr_t addr, offset; 1208 vaddr_t va; 1209 int ss; 1210 1211 addr = hp->_ptr; 1212 ss = get_childspace(t->type); 1213 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1214 " cspace %d", t->type, addr, ss)); 1215 1216 pr = get_psychorange(pp, ss); 1217 if (pr != NULL) { 1218 if (!PHYS_ASI(hp->_asi)) { 1219 va = trunc_page((vaddr_t)addr); 1220 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1221 DPRINTF(PDB_BUSMAP, 1222 ("\n pmap_extract FAILED\n")); 1223 return (-1); 1224 } 1225 addr += hp->_ptr & PGOFSET; 1226 } 1227 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1228 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1229 " offset %" PRIx64 "\n", addr, offset)); 1230 return (offset); 1231 } 1232 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1233 return (-1); 1234 } 1235 1236 1237 /* 1238 * install an interrupt handler for a PCI device 1239 */ 1240 void * 1241 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1242 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1243 { 1244 struct psycho_pbm *pp = t->cookie; 1245 struct psycho_softc *sc = pp->pp_sc; 1246 struct intrhand *ih; 1247 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1248 int64_t imap = 0; 1249 int ino; 1250 long vec = INTVEC(ihandle); 1251 1252 ih = (struct intrhand *) 1253 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1254 if (ih == NULL) 1255 return (NULL); 1256 1257 /* 1258 * Hunt through all the interrupt mapping regs to look for our 1259 * interrupt vector. 1260 * 1261 * XXX We only compare INOs rather than IGNs since the firmware may 1262 * not provide the IGN and the IGN is constant for all device on that 1263 * PCI controller. This could cause problems for the FFB/external 1264 * interrupt which has a full vector that can be set arbitrarily. 1265 */ 1266 1267 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1268 ino = INTINO(vec); 1269 DPRINTF(PDB_INTR, (" ino %x", ino)); 1270 1271 /* If the device didn't ask for an IPL, use the one encoded. */ 1272 if (level == IPL_NONE) level = INTLEV(vec); 1273 /* If it still has no level, print a warning and assign IPL 2 */ 1274 if (level == IPL_NONE) { 1275 printf("ERROR: no IPL, setting IPL 2.\n"); 1276 level = 2; 1277 } 1278 1279 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1280 (long)ino, intrlev[ino])); 1281 1282 /* 1283 * First look for PCI interrupts, otherwise the PCI A slot 0 1284 * INTA# interrupt might match an unused non-PCI (obio) 1285 * interrupt. 1286 */ 1287 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1288 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1289 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1290 intrmapptr++, intrclrptr += 4) { 1291 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1292 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1293 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1294 continue; 1295 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1296 intrclrptr += vec & 0x3; 1297 goto found; 1298 } 1299 } 1300 1301 /* Now hunt thru obio. */ 1302 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1303 intrclrptr = &sc->sc_regs->scsi_clr_int; 1304 intrmapptr < &sc->sc_regs->ue_int_map; 1305 intrmapptr++, intrclrptr++) { 1306 if (INTINO(*intrmapptr) == ino) 1307 goto found; 1308 } 1309 1310 /* Finally check the two FFB slots */ 1311 intrclrptr = NULL; /* XXX? */ 1312 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1313 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1314 intrmapptr++) { 1315 if (INTVEC(*intrmapptr) == ino) 1316 goto found; 1317 } 1318 1319 printf("Cannot find interrupt vector %lx\n", vec); 1320 return (NULL); 1321 1322 found: 1323 /* Register the map and clear intr registers */ 1324 ih->ih_map = intrmapptr; 1325 ih->ih_clr = intrclrptr; 1326 1327 ih->ih_fun = handler; 1328 ih->ih_arg = arg; 1329 ih->ih_pil = level; 1330 ih->ih_number = ino | sc->sc_ign; 1331 1332 DPRINTF(PDB_INTR, ( 1333 "; installing handler %p arg %p with ino %u pil %u\n", 1334 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1335 1336 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1337 1338 /* 1339 * Enable the interrupt now we have the handler installed. 1340 * Read the current value as we can't change it besides the 1341 * valid bit so so make sure only this bit is changed. 1342 * 1343 * XXXX --- we really should use bus_space for this. 1344 */ 1345 if (intrmapptr) { 1346 imap = *intrmapptr; 1347 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1348 (unsigned long long)imap)); 1349 1350 /* Enable the interrupt */ 1351 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1352 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1353 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1354 (unsigned long long)imap)); 1355 *intrmapptr = imap; 1356 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1357 (unsigned long long)(imap = *intrmapptr))); 1358 } 1359 if (intrclrptr) { 1360 /* set state to IDLE */ 1361 *intrclrptr = 0; 1362 } 1363 return (ih); 1364 } 1365 1366 /* 1367 * per-controller driver calls 1368 */ 1369 1370 /* assume we are mapped little-endian/side-effect */ 1371 static pcireg_t 1372 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1373 { 1374 struct psycho_pbm *pp = pc->cookie; 1375 struct psycho_softc *sc = pp->pp_sc; 1376 pcireg_t val = (pcireg_t)~0; 1377 1378 DPRINTF(PDB_CONF, ("pci_conf_read: tag %lx reg %x ", 1379 (long)tag, reg)); 1380 if (PCITAG_NODE(tag) != -1) { 1381 1382 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1383 sc->sc_configaddr._asi, 1384 (long long)(sc->sc_configaddr._ptr + 1385 PCITAG_OFFSET(tag) + reg), 1386 (int)PCITAG_OFFSET(tag) + reg)); 1387 1388 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1389 PCITAG_OFFSET(tag) + reg); 1390 } 1391 #ifdef DEBUG 1392 else DPRINTF(PDB_CONF, ("pci_conf_read: bogus pcitag %x\n", 1393 (int)PCITAG_OFFSET(tag))); 1394 #endif 1395 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1396 1397 return (val); 1398 } 1399 1400 static void 1401 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1402 { 1403 struct psycho_pbm *pp = pc->cookie; 1404 struct psycho_softc *sc = pp->pp_sc; 1405 1406 DPRINTF(PDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", 1407 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1408 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1409 sc->sc_configaddr._asi, 1410 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1411 (int)PCITAG_OFFSET(tag) + reg)); 1412 1413 /* If we don't know it, just punt it. */ 1414 if (PCITAG_NODE(tag) == -1) { 1415 DPRINTF(PDB_CONF, ("pci_conf_write: bad addr")); 1416 return; 1417 } 1418 1419 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1420 PCITAG_OFFSET(tag) + reg, data); 1421 } 1422 1423 static void * 1424 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1425 int (*func)(void *), void *arg) 1426 { 1427 void *cookie; 1428 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1429 1430 DPRINTF(PDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 1431 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1432 1433 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1434 return (cookie); 1435 } 1436 1437 static int 1438 psycho_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1439 { 1440 struct psycho_pbm *pp = pa->pa_pc->cookie; 1441 struct psycho_softc *sc = pp->pp_sc; 1442 u_int bus; 1443 u_int dev; 1444 u_int pin; 1445 1446 DPRINTF(PDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 1447 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1448 (int)PCITAG_DEV(pa->pa_tag), 1449 (int)PCITAG_FUN(pa->pa_tag))); 1450 DPRINTF(PDB_INTMAP, 1451 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 1452 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1453 DPRINTF(PDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 1454 PCITAG_NODE(pa->pa_intrtag), 1455 (int)PCITAG_BUS(pa->pa_intrtag), 1456 (int)PCITAG_DEV(pa->pa_intrtag), 1457 (int)PCITAG_FUN(pa->pa_intrtag))); 1458 1459 bus = (pp->pp_id == PSYCHO_PBM_B); 1460 /* 1461 * If we are on a ppb, use the devno on the underlying bus when forming 1462 * the ivec. 1463 */ 1464 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1465 dev = PCITAG_DEV(pa->pa_intrtag); 1466 else 1467 dev = pa->pa_device; 1468 dev--; 1469 1470 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1471 pp->pp_id == PSYCHO_PBM_B) 1472 dev--; 1473 1474 pin = pa->pa_intrpin - 1; 1475 DPRINTF(PDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 1476 sc->sc_mode, pp->pp_id, dev, pin)); 1477 1478 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1479 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1480 1481 return (0); 1482 } 1483 1484 /* 1485 * hooks into the iommu dvma calls. 1486 */ 1487 static int 1488 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1489 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1490 bus_dmamap_t *dmamp) 1491 { 1492 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1493 int error; 1494 1495 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1496 boundary, flags, dmamp); 1497 if (error == 0) 1498 (*dmamp)->_dm_cookie = &pp->pp_sb; 1499 return error; 1500 } 1501 1502 /* 1503 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1504 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1505 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1506 */ 1507 static void 1508 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1509 bus_size_t len, int ops) 1510 { 1511 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1512 struct psycho_softc *sc = pp->pp_sc; 1513 1514 if (ops & BUS_DMASYNC_POSTREAD) 1515 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1516 offsetof(struct psychoreg, pci_dma_write_sync)); 1517 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1518 } 1519
Indexes created Thu Sep 25 06:09:39 GMT 2025