psychoreg.h revision 1.1
1 /* $NetBSD: psychoreg.h,v 1.1 1999/06/04 13:42:15 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 #ifndef _SPARC64_DEV_PSYCHOREG_H_ 48 #define _SPARC64_DEV_PSYCHOREG_H_ 49 50 /* 51 * Sun4u PCI definitions. Here's where we deal w/the machine 52 * dependencies of psycho and the PCI controller on the UltraIIi. 53 * 54 * All PCI registers are bit-swapped, however they are not byte-swapped. 55 * This means that they must be accessed using little-endian access modes, 56 * either map the pages little-endian or use little-endian ASIs. 57 * 58 * PSYCHO implements two PCI buses, A and B. 59 */ 60 61 struct psychoreg { 62 struct upareg { 63 u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */ 64 u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */ 65 } sys_upa; 66 67 u_int64_t psy_csr; /* PSYCHO control/status register */ /* 1fe.0000.0010 */ 68 u_int64_t pad0; 69 u_int64_t psy_ecccr; /* ECC control register */ /* 1fe.0000.0020 */ 70 u_int64_t reserved; /* 1fe.0000.0028 */ 71 u_int64_t psy_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */ 72 u_int64_t psy_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */ 73 u_int64_t psy_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */ 74 u_int64_t psy_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */ 75 76 u_int64_t pad1[22]; 77 78 struct perfmon { 79 u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */ 80 u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */ 81 } psy_pm; 82 83 u_int64_t pad2[30]; 84 85 struct iommureg psy_iommu; /* 1fe.0000.0200,0210 */ 86 87 u_int64_t pad3[317]; 88 89 u_int64_t pcia_slot0_int; /* PCI bus a slot 0 irq map reg */ /* 1fe.0000.0c00 */ 90 u_int64_t pcia_slot1_int; /* PCI bus a slot 1 irq map reg */ /* 1fe.0000.0c08 */ 91 u_int64_t pcia_slot2_int; /* PCI bus a slot 2 irq map reg (IIi)*/ /* 1fe.0000.0c10 */ 92 u_int64_t pcia_slot3_int; /* PCI bus a slot 3 irq map reg (IIi)*/ /* 1fe.0000.0c18 */ 93 u_int64_t pcib_slot0_int; /* PCI bus b slot 0 irq map reg */ /* 1fe.0000.0c20 */ 94 u_int64_t pcib_slot1_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c28 */ 95 u_int64_t pcib_slot2_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c30 */ 96 u_int64_t pcib_slot3_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c38 */ 97 98 u_int64_t pad5[120]; 99 100 u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.1000 */ 101 u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.1008 */ 102 u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.1010 */ 103 u_int64_t audior_int_map; /* audio record interrupt map reg */ /* 1fe.0000.1018 */ 104 u_int64_t audiop_int_map; /* audio playback interrupt map reg */ /* 1fe.0000.1020 */ 105 u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.1028 */ 106 u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.1030 */ 107 u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.1038 */ 108 u_int64_t spare_int_map; /* spare interrupt map reg */ /* 1fe.0000.1040 */ 109 u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.1048 */ 110 u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.1050 */ 111 u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.1058 */ 112 u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.1060 */ 113 u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.1068 */ 114 u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.1070 */ 115 u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.1078 */ 116 u_int64_t pciaerr_int_map; /* PCI bus a error interrupt map reg */ /* 1fe.0000.1080 */ 117 u_int64_t pciberr_int_map; /* PCI bus b error interrupt map reg */ /* 1fe.0000.1088 */ 118 u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.1090 */ 119 u_int64_t ffb0_int_map; /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */ 120 u_int64_t ffb1_int_map; /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */ 121 122 u_int64_t pad6[107]; 123 124 /* Note: clear interrupt 0 registers are not really used */ 125 u_int64_t pcia0_clr_int[4]; /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */ 126 u_int64_t pcia1_clr_int[4]; /* PCI a slot 1 clear int regs 0..7 */ /* 1fe.0000.1420-1438 */ 127 u_int64_t pcia2_clr_int[4]; /* PCI a slot 2 clear int regs 0..7 */ /* 1fe.0000.1440-1458 */ 128 u_int64_t pcia3_clr_int[4]; /* PCI a slot 3 clear int regs 0..7 */ /* 1fe.0000.1480-1478 */ 129 u_int64_t pcib0_clr_int[4]; /* PCI b slot 0 clear int regs 0..7 */ /* 1fe.0000.1480-1498 */ 130 u_int64_t pcib1_clr_int[4]; /* PCI b slot 1 clear int regs 0..7 */ /* 1fe.0000.14a0-14b8 */ 131 u_int64_t pcib2_clr_int[4]; /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */ 132 u_int64_t pcib3_clr_int[4]; /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */ 133 134 u_int64_t pad8[96]; 135 136 u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.1800 */ 137 u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.1808 */ 138 u_int64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.1810 */ 139 u_int64_t audior_clr_int; /* audio record clear int reg */ /* 1fe.0000.1818 */ 140 u_int64_t audiop_clr_int; /* audio playback clear int reg */ /* 1fe.0000.1820 */ 141 u_int64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.1828 */ 142 u_int64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.1830 */ 143 u_int64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.1838 */ 144 u_int64_t spare_clr_int; /* spare clear int reg */ /* 1fe.0000.1840 */ 145 u_int64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.1848 */ 146 u_int64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.1850 */ 147 u_int64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.1858 */ 148 u_int64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.1860 */ 149 u_int64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.1868 */ 150 u_int64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.1870 */ 151 u_int64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.1878 */ 152 u_int64_t pciaerr_clr_int; /* PCI bus a error clear int reg */ /* 1fe.0000.1880 */ 153 u_int64_t pciberr_clr_int; /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */ 154 u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */ 155 156 u_int64_t pad9[45]; 157 158 u_int64_t intr_retry_timer; /* interrupt retry timer */ /* 1fe.0000.1a00 */ 159 160 u_int64_t pad10[63]; 161 162 struct timer_counter { 163 u_int64_t tc_count; /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */ 164 u_int64_t tc_limit; /* timer/counter 0/1 limit register */ /* 1fe.0000.1c08,1c18 */ 165 } tc[2]; 166 167 u_int64_t pci_dma_write_sync; /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */ 168 169 u_int64_t pad11[123]; 170 171 struct pci_ctl { 172 u_int64_t pci_csr; /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */ 173 u_int64_t pci_afsr; /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */ 174 u_int64_t pci_afar; /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */ 175 u_int64_t pci_diag; /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */ 176 u_int64_t pci_tasr; /* PCI target address space reg (IIi)*/ /* 1fe.0000.2020,4028 */ 177 178 u_int64_t pad12[250]; 179 180 /* This is really the IOMMU's, not the PCI bus's */ 181 struct iommu_strbuf pci_strbuf; /* 1fe.0000.2800-210 */ 182 #define psy_iommu_strbuf psy_pcictl[0].pci_strbuf 183 184 u_int64_t pad13[765]; 185 } psy_pcictl[2]; /* For PCI a and b */ 186 187 /* NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 1fe.0000.8000 respectively */ 188 u_int64_t pad14[2048]; 189 190 u_int64_t dma_scb_diag0; /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */ 191 u_int64_t dma_scb_diag1; /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */ 192 193 u_int64_t pad15[126]; 194 195 u_int64_t iommu_svadiag; /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */ 196 u_int64_t iommu_tlb_comp_diag; /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */ 197 198 u_int64_t pad16[30]; 199 200 u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */ 201 u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */ 202 u_int64_t tlb_data_diag[16]; /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */ 203 204 u_int64_t pad17[48]; 205 206 u_int64_t pci_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.a800 */ 207 u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */ 208 209 u_int64_t pad18[254]; 210 211 struct strbuf_diag { 212 u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */ 213 u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */ 214 u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */ 215 u_int64_t pad19[16]; 216 u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */ 217 u_int64_t pad20[208]; 218 } psy_strbufdiag[2]; /* For PCI a and b */ 219 220 /* 221 * Here is the rest of the map, which we're not specifying: 222 * 223 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 224 * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header 225 * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header 226 * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space 227 * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space 228 * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space 229 * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space 230 * 231 * NB: config and I/O space can use 1-4 byte accesses, not 8 byte accesses. 232 * Memory space can use any sized accesses. 233 * 234 * Note that the SUNW,sabre (APB) has slightly differrent addresses 235 * than the above. This is mostly due to the fact that the APB is 236 * a multi-function PCI device with two PCI bridges, and the U2P is 237 * two separate PCI devices (also PCI bridges). It uses the same 238 * PCI configuration space, though the configuration header for each 239 * PCI bus is located differently due to the SUNW,simba PCI busses 240 * being function 0 and function 1 of the APB, whereas the psycho's 241 * are each their own PCI device. The I/O and memory spaces are each 242 * split into 8 equally sized areas (8x2MB blocks for I/O space, and 243 * 8x512MB blocks for memory space). These are allocated in to either 244 * PCI A or PCI B, or neither in the APB's `I/O Address Map Register 245 * A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) registers 246 * of each simba. We must ensure that both of the following are 247 * correct (the prom should do this for us): 248 * 249 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 250 * 251 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 252 * 253 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 254 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header 255 * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header 256 * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided) 257 * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided) 258 */ 259 }; 260 261 /* what the bits mean! */ 262 263 /* PCI [a|b] control/status register */ 264 /* note that the sabre only has one set of PCI control/status registers */ 265 #define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */ 266 #define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */ 267 #define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */ 268 #define PCICTL_4ENABLE 0x000000000000000f /* enable 4 PCI slots */ 269 #define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */ 270 271 /* 272 * these are the PROM structures we grovel 273 */ 274 275 /* 276 * For the physical adddresses split into 3 32 bit values, we deocde them 277 * like the following (PCI Bus binding 2.0, 2.2.1.1 Numerical Representation) 278 * 279 * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr 280 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 281 * phys.lo cell: llllllll llllllll llllllll llllllll 282 * 283 * where these bits affect the address' properties: 284 * n not-relocatable 285 * p prefetchable 286 * t aliased (non-relocatable IO), below 1MB (memory) or 287 * below 64KB (reloc. IO) 288 * ss address space code: 289 * 00 - configuration space 290 * 01 - I/O space 291 * 10 - 32 bit memory space 292 * 11 - 64 bit memory space 293 * bb..bb 8 bit bus number 294 * ddddd 5 bit device number 295 * fff 3 bit function number 296 * rr..rr 8 bit register number 297 * hh..hh 32 bit unsigned value 298 * ll..ll 32 bit unsigned value 299 * the values of hh..hh and ll..ll are combined to form a larger number. 300 * 301 * For config space, we don't have to do much special. For I/O space, 302 * hh..hh must be zero, and if n == 0 ll..ll is the offset from the 303 * start of I/O space, otherwise ll..ll is the I/O space. For memory 304 * space, hh..hh must be zero for the 32 bit space, and is the high 32 305 * bits in 64 bit space, with ll..ll being the low 32 bits in both cases, 306 * with offset handling being driver via `n == 0' as for I/O space. 307 */ 308 309 struct psycho_registers { 310 u_int32_t phys_hi; 311 u_int32_t phys_mid; 312 u_int32_t phys_lo; 313 u_int32_t size_hi; 314 u_int32_t size_lo; 315 }; 316 317 struct psycho_ranges { 318 u_int32_t cspace; 319 u_int32_t child_hi; 320 u_int32_t child_lo; 321 u_int32_t phys_hi; 322 u_int32_t phys_lo; 323 u_int32_t size_hi; 324 u_int32_t size_lo; 325 }; 326 327 struct psycho_interrupt_map { 328 u_int32_t phys_hi; 329 u_int32_t phys_mid; 330 u_int32_t phys_lo; 331 u_int32_t intr; 332 int32_t child_node; 333 u_int32_t child_intr; 334 }; 335 336 struct psycho_interrupt_map_mask { 337 u_int32_t phys_hi; 338 u_int32_t phys_mid; 339 u_int32_t phys_lo; 340 u_int32_t intr; 341 }; 342 343 #endif /* _SPARC64_DEV_PSYCHOREG_H_ */ 344
Indexes created Wed Oct 01 15:09:59 GMT 2025