psychoreg.h revision 1.4
1 /* $NetBSD: psychoreg.h,v 1.4 2000/05/24 20:27:52 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 Eduardo E. Horvath 5 * Copyright (c) 1999 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 #ifndef _SPARC64_DEV_PSYCHOREG_H_ 32 #define _SPARC64_DEV_PSYCHOREG_H_ 33 34 /* 35 * Sun4u PCI definitions. Here's where we deal w/the machine 36 * dependencies of psycho and the PCI controller on the UltraIIi. 37 * 38 * All PCI registers are bit-swapped, however they are not byte-swapped. 39 * This means that they must be accessed using little-endian access modes, 40 * either map the pages little-endian or use little-endian ASIs. 41 * 42 * PSYCHO implements two PCI buses, A and B. 43 */ 44 45 struct psychoreg { 46 struct upareg { 47 u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */ 48 u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */ 49 } sys_upa; 50 51 u_int64_t psy_csr; /* PSYCHO control/status register */ /* 1fe.0000.0010 */ 52 u_int64_t pad0; 53 u_int64_t psy_ecccr; /* ECC control register */ /* 1fe.0000.0020 */ 54 u_int64_t reserved; /* 1fe.0000.0028 */ 55 u_int64_t psy_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */ 56 u_int64_t psy_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */ 57 u_int64_t psy_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */ 58 u_int64_t psy_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */ 59 60 u_int64_t pad1[22]; 61 62 struct perfmon { 63 u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */ 64 u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */ 65 } psy_pm; 66 67 u_int64_t pad2[30]; 68 69 struct iommureg psy_iommu; /* 1fe.0000.0200,0210 */ 70 71 u_int64_t pad3[317]; 72 73 u_int64_t pcia_slot0_int; /* PCI bus a slot 0 irq map reg */ /* 1fe.0000.0c00 */ 74 u_int64_t pcia_slot1_int; /* PCI bus a slot 1 irq map reg */ /* 1fe.0000.0c08 */ 75 u_int64_t pcia_slot2_int; /* PCI bus a slot 2 irq map reg (IIi)*/ /* 1fe.0000.0c10 */ 76 u_int64_t pcia_slot3_int; /* PCI bus a slot 3 irq map reg (IIi)*/ /* 1fe.0000.0c18 */ 77 u_int64_t pcib_slot0_int; /* PCI bus b slot 0 irq map reg */ /* 1fe.0000.0c20 */ 78 u_int64_t pcib_slot1_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c28 */ 79 u_int64_t pcib_slot2_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c30 */ 80 u_int64_t pcib_slot3_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c38 */ 81 82 u_int64_t pad5[120]; 83 84 u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.1000 */ 85 u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.1008 */ 86 u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.1010 */ 87 u_int64_t audior_int_map; /* audio record interrupt map reg */ /* 1fe.0000.1018 */ 88 u_int64_t audiop_int_map; /* audio playback interrupt map reg */ /* 1fe.0000.1020 */ 89 u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.1028 */ 90 u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.1030 */ 91 u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.1038 */ 92 u_int64_t spare_int_map; /* spare interrupt map reg */ /* 1fe.0000.1040 */ 93 u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.1048 */ 94 u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.1050 */ 95 u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.1058 */ 96 u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.1060 */ 97 u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.1068 */ 98 u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.1070 */ 99 u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.1078 */ 100 u_int64_t pciaerr_int_map; /* PCI bus a error interrupt map reg */ /* 1fe.0000.1080 */ 101 u_int64_t pciberr_int_map; /* PCI bus b error interrupt map reg */ /* 1fe.0000.1088 */ 102 u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.1090 */ 103 u_int64_t ffb0_int_map; /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */ 104 u_int64_t ffb1_int_map; /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */ 105 106 u_int64_t pad6[107]; 107 108 /* Note: clear interrupt 0 registers are not really used */ 109 u_int64_t pcia0_clr_int[4]; /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */ 110 u_int64_t pcia1_clr_int[4]; /* PCI a slot 1 clear int regs 0..7 */ /* 1fe.0000.1420-1438 */ 111 u_int64_t pcia2_clr_int[4]; /* PCI a slot 2 clear int regs 0..7 */ /* 1fe.0000.1440-1458 */ 112 u_int64_t pcia3_clr_int[4]; /* PCI a slot 3 clear int regs 0..7 */ /* 1fe.0000.1480-1478 */ 113 u_int64_t pcib0_clr_int[4]; /* PCI b slot 0 clear int regs 0..7 */ /* 1fe.0000.1480-1498 */ 114 u_int64_t pcib1_clr_int[4]; /* PCI b slot 1 clear int regs 0..7 */ /* 1fe.0000.14a0-14b8 */ 115 u_int64_t pcib2_clr_int[4]; /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */ 116 u_int64_t pcib3_clr_int[4]; /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */ 117 118 u_int64_t pad8[96]; 119 120 u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.1800 */ 121 u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.1808 */ 122 u_int64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.1810 */ 123 u_int64_t audior_clr_int; /* audio record clear int reg */ /* 1fe.0000.1818 */ 124 u_int64_t audiop_clr_int; /* audio playback clear int reg */ /* 1fe.0000.1820 */ 125 u_int64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.1828 */ 126 u_int64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.1830 */ 127 u_int64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.1838 */ 128 u_int64_t spare_clr_int; /* spare clear int reg */ /* 1fe.0000.1840 */ 129 u_int64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.1848 */ 130 u_int64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.1850 */ 131 u_int64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.1858 */ 132 u_int64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.1860 */ 133 u_int64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.1868 */ 134 u_int64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.1870 */ 135 u_int64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.1878 */ 136 u_int64_t pciaerr_clr_int; /* PCI bus a error clear int reg */ /* 1fe.0000.1880 */ 137 u_int64_t pciberr_clr_int; /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */ 138 u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */ 139 140 u_int64_t pad9[45]; 141 142 u_int64_t intr_retry_timer; /* interrupt retry timer */ /* 1fe.0000.1a00 */ 143 144 u_int64_t pad10[63]; 145 146 struct timer_counter { 147 u_int64_t tc_count; /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */ 148 u_int64_t tc_limit; /* timer/counter 0/1 limit register */ /* 1fe.0000.1c08,1c18 */ 149 } tc[2]; 150 151 u_int64_t pci_dma_write_sync; /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */ 152 153 u_int64_t pad11[123]; 154 155 struct pci_ctl { 156 u_int64_t pci_csr; /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */ 157 u_int64_t pci_afsr; /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */ 158 u_int64_t pci_afar; /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */ 159 u_int64_t pci_diag; /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */ 160 u_int64_t pci_tasr; /* PCI target address space reg (IIi)*/ /* 1fe.0000.2020,4028 */ 161 162 u_int64_t pad12[250]; 163 164 /* This is really the IOMMU's, not the PCI bus's */ 165 struct iommu_strbuf pci_strbuf; /* 1fe.0000.2800-210 */ 166 #define psy_iommu_strbuf psy_pcictl[0].pci_strbuf 167 168 u_int64_t pad13[765]; 169 } psy_pcictl[2]; /* For PCI a and b */ 170 171 /* NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 1fe.0000.8000 respectively */ 172 u_int64_t pad14[2048]; 173 174 u_int64_t dma_scb_diag0; /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */ 175 u_int64_t dma_scb_diag1; /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */ 176 177 u_int64_t pad15[126]; 178 179 u_int64_t iommu_svadiag; /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */ 180 u_int64_t iommu_tlb_comp_diag; /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */ 181 182 u_int64_t pad16[30]; 183 184 u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */ 185 u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */ 186 u_int64_t tlb_data_diag[16]; /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */ 187 188 u_int64_t pad17[48]; 189 190 u_int64_t pci_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.a800 */ 191 u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */ 192 193 u_int64_t pad18[254]; 194 195 struct strbuf_diag { 196 u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */ 197 u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */ 198 u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */ 199 u_int64_t pad19[16]; 200 u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */ 201 u_int64_t pad20[208]; 202 } psy_strbufdiag[2]; /* For PCI a and b */ 203 204 /* 205 * Here is the rest of the map, which we're not specifying: 206 * 207 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 208 * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header 209 * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header 210 * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space 211 * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space 212 * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space 213 * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space 214 * 215 * NB: config and I/O space can use 1-4 byte accesses, not 8 byte accesses. 216 * Memory space can use any sized accesses. 217 * 218 * Note that the SUNW,sabre/SUNW,simba combinations found on the 219 * Ultra5 and Ultra10 machines uses slightly differrent addresses 220 * than the above. This is mostly due to the fact that the APB is 221 * a multi-function PCI device with two PCI bridges, and the U2P is 222 * two separate PCI bridges. It uses the same PCI configuration 223 * space, though the configuration header for each PCI bus is 224 * located differently due to the SUNW,simba PCI busses being 225 * function 0 and function 1 of the APB, whereas the psycho's are 226 * each their own PCI device. The I/O and memory spaces are each 227 * split into 8 equally sized areas (8x2MB blocks for I/O space, 228 * and 8x512MB blocks for memory space). These are allocated in to 229 * either PCI A or PCI B, or neither in the APB's `I/O Address Map 230 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) 231 * registers of each simba. We must ensure that both of the 232 * following are correct (the prom should do this for us): 233 * 234 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 235 * 236 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 237 * 238 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 239 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header 240 * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header 241 * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided) 242 * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided) 243 */ 244 }; 245 246 /* what the bits mean! */ 247 248 /* PCI [a|b] control/status register */ 249 /* note that the sabre only has one set of PCI control/status registers */ 250 #define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */ 251 #define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */ 252 #define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */ 253 #define PCICTL_CPU_PRIO 0x0000000000100000 /* PCI arbitration parking */ 254 #define PCICTL_ARB_PRIO 0x00000000000f0000 /* PCI arbitration parking */ 255 #define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */ 256 #define PCICTL_RTRYWAIT 0x0000000000000080 /* PCI error interrupt enable */ 257 #define PCICTL_4ENABLE 0x000000000000000f /* enable 4 PCI slots */ 258 #define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */ 259 260 /* 261 * these are the PROM structures we grovel 262 */ 263 264 /* 265 * For the physical adddresses split into 3 32 bit values, we deocde 266 * them like the following (IEEE1275 PCI Bus binding 2.0, 2.2.1.1 267 * Numerical Representation): 268 * 269 * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr 270 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 271 * phys.lo cell: llllllll llllllll llllllll llllllll 272 * 273 * where these bits affect the address' properties: 274 * n not-relocatable 275 * p prefetchable 276 * t aliased (non-relocatable IO), below 1MB (memory) or 277 * below 64KB (reloc. IO) 278 * ss address space code: 279 * 00 - configuration space 280 * 01 - I/O space 281 * 10 - 32 bit memory space 282 * 11 - 64 bit memory space 283 * bb..bb 8 bit bus number 284 * ddddd 5 bit device number 285 * fff 3 bit function number 286 * rr..rr 8 bit register number 287 * hh..hh 32 bit unsigned value 288 * ll..ll 32 bit unsigned value 289 * the values of hh..hh and ll..ll are combined to form a larger number. 290 * 291 * For config space, we don't have to do much special. For I/O space, 292 * hh..hh must be zero, and if n == 0 ll..ll is the offset from the 293 * start of I/O space, otherwise ll..ll is the I/O space. For memory 294 * space, hh..hh must be zero for the 32 bit space, and is the high 32 295 * bits in 64 bit space, with ll..ll being the low 32 bits in both cases, 296 * with offset handling being driver via `n == 0' as for I/O space. 297 */ 298 299 /* commonly used */ 300 #define TAG2BUS(tag) ((tag) >> 16) & 0xff; 301 #define TAG2DEV(tag) ((tag) >> 11) & 0x1f; 302 #define TAG2FN(tag) ((tag) >> 8) & 0x7; 303 304 struct psycho_registers { 305 u_int32_t phys_hi; 306 u_int32_t phys_mid; 307 u_int32_t phys_lo; 308 u_int32_t size_hi; 309 u_int32_t size_lo; 310 }; 311 312 struct psycho_ranges { 313 u_int32_t cspace; 314 u_int32_t child_hi; 315 u_int32_t child_lo; 316 u_int32_t phys_hi; 317 u_int32_t phys_lo; 318 u_int32_t size_hi; 319 u_int32_t size_lo; 320 }; 321 322 struct psycho_interrupt_map { 323 u_int32_t phys_hi; 324 u_int32_t phys_mid; 325 u_int32_t phys_lo; 326 u_int32_t intr; 327 int32_t child_node; 328 u_int32_t child_intr; 329 }; 330 331 struct psycho_interrupt_map_mask { 332 u_int32_t phys_hi; 333 u_int32_t phys_mid; 334 u_int32_t phys_lo; 335 u_int32_t intr; 336 }; 337 338 #endif /* _SPARC64_DEV_PSYCHOREG_H_ */ 339
Indexes created Wed Oct 01 15:09:59 GMT 2025