pyro.c revision 1.10
1 /* $NetBSD: pyro.c,v 1.10 2011/08/12 06:41:50 mrg Exp $ */ 2 /* from: $OpenBSD: pyro.c,v 1.20 2010/12/05 15:15:14 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2007 Mark Kettenis 8 * Copyright (c) 2011 Matthew R. Green 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/errno.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 39 #define _SPARC_BUS_DMA_PRIVATE 40 #include <sys/bus.h> 41 #include <machine/autoconf.h> 42 43 #ifdef DDB 44 #include <machine/db_machdep.h> 45 #endif 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include <sparc64/dev/iommureg.h> 51 #include <sparc64/dev/iommuvar.h> 52 #include <sparc64/dev/pyrovar.h> 53 54 #ifdef DEBUG 55 #define PDB_PROM 0x01 56 #define PDB_BUSMAP 0x02 57 #define PDB_INTR 0x04 58 #define PDB_CONF 0x08 59 int pyro_debug = 0x0 | PDB_INTR; 60 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0) 61 #else 62 #define DPRINTF(l, s) 63 #endif 64 65 #define FIRE_RESET_GEN 0x7010 66 67 #define FIRE_RESET_GEN_XIR 0x0000000000000002L 68 69 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 70 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 71 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 72 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 73 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 74 #define FIRE_INTRMAP_T_JPID_SHIFT 26 75 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 76 77 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 78 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 79 80 extern struct sparc_pci_chipset _sparc_pci_chipset; 81 82 int pyro_match(device_t, cfdata_t, void *); 83 void pyro_attach(device_t, device_t, void *); 84 int pyro_print(void *, const char *); 85 86 CFATTACH_DECL_NEW(pyro, sizeof(struct pyro_softc), 87 pyro_match, pyro_attach, NULL, NULL); 88 89 void pyro_init(struct pyro_softc *, int); 90 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *); 91 92 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int, 93 pci_chipset_tag_t); 94 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *); 95 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *); 96 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *); 97 bus_space_tag_t pyro_alloc_bus_tag(struct pyro_pbm *, const char *, int); 98 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *); 99 100 #if 0 101 int pyro_conf_size(pci_chipset_tag_t, pcitag_t); 102 #endif 103 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int); 104 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 105 106 static void * pyro_pci_intr_establish(pci_chipset_tag_t pc, 107 pci_intr_handle_t ih, int level, 108 int (*func)(void *), void *arg); 109 110 int pyro_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 111 int pyro_bus_map(bus_space_tag_t, bus_addr_t, 112 bus_size_t, int, vaddr_t, bus_space_handle_t *); 113 paddr_t pyro_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, 114 int, int); 115 void *pyro_intr_establish(bus_space_tag_t, int, int, 116 int (*)(void *), void *, void (*)(void)); 117 118 int pyro_dmamap_create(bus_dma_tag_t, bus_size_t, int, 119 bus_size_t, bus_size_t, int, bus_dmamap_t *); 120 121 int 122 pyro_match(struct device *parent, cfdata_t match, void *aux) 123 { 124 struct mainbus_attach_args *ma = aux; 125 char *str; 126 127 if (strcmp(ma->ma_name, "pci") != 0) 128 return (0); 129 130 str = prom_getpropstring(ma->ma_node, "compatible"); 131 if (strcmp(str, "pciex108e,80f0") == 0 || 132 strcmp(str, "pciex108e,80f8") == 0) 133 return (1); 134 135 return (0); 136 } 137 138 void 139 pyro_attach(struct device *parent, struct device *self, void *aux) 140 { 141 struct pyro_softc *sc = device_private(self); 142 struct mainbus_attach_args *ma = aux; 143 char *str; 144 int busa; 145 146 sc->sc_dev = self; 147 sc->sc_node = ma->ma_node; 148 sc->sc_dmat = ma->ma_dmatag; 149 sc->sc_bustag = ma->ma_bustag; 150 sc->sc_csr = ma->ma_reg[0].ur_paddr; 151 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 152 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 153 154 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 155 busa = 1; 156 else 157 busa = 0; 158 159 if (bus_space_map(sc->sc_bustag, sc->sc_csr, 160 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, &sc->sc_csrh)) { 161 printf(": failed to map csr registers\n"); 162 return; 163 } 164 165 if (bus_space_map(sc->sc_bustag, sc->sc_xbc, 166 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 167 printf(": failed to map xbc registers\n"); 168 return; 169 } 170 171 str = prom_getpropstring(ma->ma_node, "compatible"); 172 if (strcmp(str, "pciex108e,80f8") == 0) 173 sc->sc_oberon = 1; 174 175 pyro_init(sc, busa); 176 } 177 178 void 179 pyro_init(struct pyro_softc *sc, int busa) 180 { 181 struct pyro_pbm *pbm; 182 struct pcibus_attach_args pba; 183 int *busranges = NULL, nranges; 184 185 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 186 if (pbm == NULL) 187 panic("pyro: can't alloc pyro pbm"); 188 189 pbm->pp_sc = sc; 190 pbm->pp_bus_a = busa; 191 192 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct pyro_range), 193 &pbm->pp_nrange, (void **)&pbm->pp_range)) 194 panic("pyro: can't get ranges"); 195 196 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 197 (void **)&busranges)) 198 panic("pyro: can't get bus-range"); 199 200 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n", 201 sc->sc_oberon ? "Oberon" : "Fire", 202 prom_getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign, 203 busa ? 'A' : 'B', busranges[0], busranges[1]); 204 205 printf("%s: ", device_xname(sc->sc_dev)); 206 pyro_init_iommu(sc, pbm); 207 208 pbm->pp_memt = pyro_alloc_mem_tag(pbm); 209 pbm->pp_iot = pyro_alloc_io_tag(pbm); 210 pbm->pp_cfgt = pyro_alloc_config_tag(pbm); 211 pbm->pp_dmat = pyro_alloc_dma_tag(pbm); 212 pbm->pp_flags = (pbm->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 213 (pbm->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 214 215 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh)) 216 panic("pyro: can't map config space"); 217 218 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 219 pbm->pp_pc->spc_busmax = busranges[1]; 220 pbm->pp_pc->spc_busnode = malloc(sizeof(*pbm->pp_pc->spc_busnode), 221 M_DEVBUF, M_NOWAIT | M_ZERO); 222 if (pbm->pp_pc->spc_busnode == NULL) 223 panic("schizo: malloc busnode"); 224 225 #if 0 226 pbm->pp_pc->bustag = pbm->pp_cfgt; 227 pbm->pp_pc->bushandle = pbm->pp_cfgh; 228 #endif 229 230 bzero(&pba, sizeof(pba)); 231 pba.pba_bus = busranges[0]; 232 pba.pba_pc = pbm->pp_pc; 233 pba.pba_flags = pbm->pp_flags; 234 pba.pba_dmat = pbm->pp_dmat; 235 pba.pba_dmat64 = NULL; /* XXX */ 236 pba.pba_memt = pbm->pp_memt; 237 pba.pba_iot = pbm->pp_iot; 238 239 free(busranges, M_DEVBUF); 240 241 config_found(sc->sc_dev, &pba, pyro_print); 242 } 243 244 void 245 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm) 246 { 247 struct iommu_state *is = &pbm->pp_is; 248 int tsbsize = 7; 249 u_int32_t iobase = -1; 250 char *name; 251 252 pbm->pp_sb.sb_is = is; 253 is->is_bustag = sc->sc_bustag; 254 255 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 256 0x40000, 0x100, &is->is_iommu)) { 257 panic("pyro: unable to create iommu handle"); 258 } 259 260 /* We have no STC. */ 261 is->is_sb[0] = NULL; 262 263 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 264 if (name == NULL) 265 panic("couldn't malloc iommu name"); 266 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 267 268 /* Tell iommu how to set the TSB size. */ 269 is->is_flags = IOMMU_TSBSIZE_IN_PTSB; 270 271 /* On Oberon, we need to flush the cache. */ 272 if (sc->sc_oberon) 273 is->is_flags |= IOMMU_FLUSH_CACHE; 274 275 iommu_init(name, is, tsbsize, iobase); 276 } 277 278 int 279 pyro_print(void *aux, const char *p) 280 { 281 if (p == NULL) 282 return (UNCONF); 283 return (QUIET); 284 } 285 286 pcireg_t 287 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 288 { 289 struct pyro_pbm *pp = pc->cookie; 290 pcireg_t val = (pcireg_t)~0; 291 292 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 293 if (PCITAG_NODE(tag) != -1) 294 val = bus_space_read_4(pp->pp_cfgt, pp->pp_cfgh, 295 (PCITAG_OFFSET(tag) << 4) + reg); 296 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 297 return (val); 298 } 299 300 void 301 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 302 { 303 struct pyro_pbm *pp = pc->cookie; 304 305 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 306 (long)tag, reg, (int)data)); 307 308 /* If we don't know it, just punt it. */ 309 if (PCITAG_NODE(tag) == -1) { 310 DPRINTF(PDB_CONF, (" .. bad addr\n")); 311 return; 312 } 313 314 bus_space_write_4(pp->pp_cfgt, pp->pp_cfgh, 315 (PCITAG_OFFSET(tag) << 4) + reg, data); 316 DPRINTF(PDB_CONF, (" .. done\n")); 317 } 318 319 /* 320 * Bus-specific interrupt mapping 321 */ 322 int 323 pyro_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 324 { 325 struct pyro_pbm *pp = pa->pa_pc->cookie; 326 struct pyro_softc *sc = pp->pp_sc; 327 u_int dev; 328 329 if (*ihp != (pci_intr_handle_t)-1) { 330 *ihp |= sc->sc_ign; 331 DPRINTF(PDB_INTR, ("%s: not -1 -> ih %lx\n", __func__, (u_long)*ihp)); 332 return (0); 333 } 334 335 /* 336 * We didn't find a PROM mapping for this interrupt. Try to 337 * construct one ourselves based on the swizzled interrupt pin 338 * and the interrupt mapping for PCI slots documented in the 339 * UltraSPARC-IIi User's Manual. 340 */ 341 342 if (pa->pa_intrpin == 0) { 343 DPRINTF(PDB_INTR, ("%s: no intrpen\n", __func__)); 344 return (-1); 345 } 346 347 /* 348 * This deserves some documentation. Should anyone 349 * have anything official looking, please speak up. 350 */ 351 dev = pa->pa_device - 1; 352 353 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 354 *ihp |= (dev << 2) & INTMAP_PCISLOT; 355 *ihp |= sc->sc_ign; 356 357 DPRINTF(PDB_INTR, ("%s: weird hack -> ih %lx\n", __func__, (u_long)*ihp)); 358 return (0); 359 } 360 361 bus_space_tag_t 362 pyro_alloc_mem_tag(struct pyro_pbm *pp) 363 { 364 return (pyro_alloc_bus_tag(pp, "mem", PCI_MEMORY_BUS_SPACE)); 365 } 366 367 bus_space_tag_t 368 pyro_alloc_io_tag(struct pyro_pbm *pp) 369 { 370 return (pyro_alloc_bus_tag(pp, "io", PCI_IO_BUS_SPACE)); 371 } 372 373 bus_space_tag_t 374 pyro_alloc_config_tag(struct pyro_pbm *pp) 375 { 376 return (pyro_alloc_bus_tag(pp, "cfg", PCI_CONFIG_BUS_SPACE)); 377 } 378 379 bus_space_tag_t 380 pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int type) 381 { 382 struct pyro_softc *sc = pbm->pp_sc; 383 struct sparc_bus_space_tag *bt; 384 385 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 386 if (bt == NULL) 387 panic("pyro: could not allocate bus tag"); 388 389 #if 0 390 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 391 device_xname(sc->sc_dev), name, ss, asi); 392 #endif 393 394 bt->cookie = pbm; 395 bt->parent = sc->sc_bustag; 396 bt->type = type; 397 bt->sparc_bus_map = pyro_bus_map; 398 bt->sparc_bus_mmap = pyro_bus_mmap; 399 bt->sparc_intr_establish = pyro_intr_establish; 400 return (bt); 401 } 402 403 bus_dma_tag_t 404 pyro_alloc_dma_tag(struct pyro_pbm *pbm) 405 { 406 struct pyro_softc *sc = pbm->pp_sc; 407 bus_dma_tag_t dt, pdt = sc->sc_dmat; 408 409 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 410 if (dt == NULL) 411 panic("pyro: could not alloc dma tag"); 412 413 dt->_cookie = pbm; 414 dt->_parent = pdt; 415 #define PCOPY(x) dt->x = pdt->x 416 dt->_dmamap_create = pyro_dmamap_create; 417 PCOPY(_dmamap_destroy); 418 dt->_dmamap_load = iommu_dvmamap_load; 419 PCOPY(_dmamap_load_mbuf); 420 PCOPY(_dmamap_load_uio); 421 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 422 dt->_dmamap_unload = iommu_dvmamap_unload; 423 dt->_dmamap_sync = iommu_dvmamap_sync; 424 dt->_dmamem_alloc = iommu_dvmamem_alloc; 425 dt->_dmamem_free = iommu_dvmamem_free; 426 dt->_dmamem_map = iommu_dvmamem_map; 427 dt->_dmamem_unmap = iommu_dvmamem_unmap; 428 PCOPY(_dmamem_mmap); 429 #undef PCOPY 430 return (dt); 431 } 432 433 pci_chipset_tag_t 434 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc) 435 { 436 pci_chipset_tag_t npc; 437 438 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 439 if (npc == NULL) 440 panic("pyro: could not allocate pci_chipset_tag_t"); 441 memcpy(npc, pc, sizeof *pc); 442 npc->cookie = pbm; 443 npc->rootnode = node; 444 npc->spc_conf_read = pyro_conf_read; 445 npc->spc_conf_write = pyro_conf_write; 446 npc->spc_intr_map = pyro_intr_map; 447 npc->spc_intr_establish = pyro_pci_intr_establish; 448 npc->spc_find_ino = NULL; 449 return (npc); 450 } 451 452 int 453 pyro_dmamap_create(bus_dma_tag_t t, bus_size_t size, 454 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 455 bus_dmamap_t *dmamp) 456 { 457 struct pyro_pbm *pbm = t->_cookie; 458 int error; 459 460 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 461 boundary, flags, dmamp); 462 if (error == 0) 463 (*dmamp)->_dm_cookie = &pbm->pp_sb; 464 return error; 465 } 466 467 int 468 pyro_bus_map(bus_space_tag_t t, bus_addr_t offset, 469 bus_size_t size, int flags, vaddr_t unused, bus_space_handle_t *hp) 470 { 471 struct pyro_pbm *pbm = t->cookie; 472 struct pyro_softc *sc = pbm->pp_sc; 473 int i, ss; 474 475 DPRINTF(PDB_BUSMAP, ("pyro_bus_map: type %d off %qx sz %qx flags %d", 476 t->type, 477 (unsigned long long)offset, 478 (unsigned long long)size, 479 flags)); 480 481 ss = sparc_pci_childspace(t->type); 482 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 483 484 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 485 printf("\n_pyro_bus_map: invalid parent"); 486 return (EINVAL); 487 } 488 489 for (i = 0; i < pbm->pp_nrange; i++) { 490 bus_addr_t paddr; 491 struct pyro_range *pr = &pbm->pp_range[i]; 492 493 if (((pr->cspace >> 24) & 0x03) != ss) 494 continue; 495 496 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 497 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 498 flags, 0, hp)); 499 } 500 501 return (EINVAL); 502 } 503 504 paddr_t 505 pyro_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 506 off_t off, int prot, int flags) 507 { 508 bus_addr_t offset = paddr; 509 struct pyro_pbm *pbm = t->cookie; 510 struct pyro_softc *sc = pbm->pp_sc; 511 int i, ss; 512 513 ss = sparc_pci_childspace(t->type); 514 515 DPRINTF(PDB_BUSMAP, ("pyro_bus_mmap: prot %d flags %d pa %qx\n", 516 prot, flags, (unsigned long long)paddr)); 517 518 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 519 printf("\n_pyro_bus_mmap: invalid parent"); 520 return (-1); 521 } 522 523 for (i = 0; i < pbm->pp_nrange; i++) { 524 struct pyro_range *pr = &pbm->pp_range[i]; 525 526 if (((pr->cspace >> 24) & 0x03) != ss) 527 continue; 528 529 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 530 return (bus_space_mmap(sc->sc_bustag, paddr, off, 531 prot, flags)); 532 } 533 534 return (-1); 535 } 536 537 void * 538 pyro_intr_establish(bus_space_tag_t t, int ihandle, int level, 539 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 540 { 541 struct pyro_pbm *pbm = t->cookie; 542 struct pyro_softc *sc = pbm->pp_sc; 543 struct intrhand *ih = NULL; 544 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 545 u_int64_t *imapbase, *iclrbase; 546 int ino; 547 548 ino = INTINO(ihandle); 549 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d ino %#x", __func__, (u_long)ihandle, level, ino)); 550 551 if (level == IPL_NONE) 552 level = INTLEV(ihandle); 553 if (level == IPL_NONE) { 554 printf(": no IPL, setting IPL 2.\n"); 555 level = 2; 556 } 557 558 imapbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1000); 559 iclrbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1400); 560 intrmapptr = &imapbase[ino]; 561 intrclrptr = &iclrbase[ino]; 562 DPRINTF(PDB_INTR, (" mapptr %p clrptr %p\n", intrmapptr, intrclrptr)); 563 564 ino |= INTVEC(ihandle); 565 566 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 567 if (ih == NULL) 568 return (NULL); 569 570 /* Register the map and clear intr registers */ 571 ih->ih_map = intrmapptr; 572 ih->ih_clr = intrclrptr; 573 574 ih->ih_ivec = ihandle; 575 ih->ih_fun = handler; 576 ih->ih_arg = arg; 577 ih->ih_pil = level; 578 ih->ih_number = ino; 579 ih->ih_pending = 0; 580 581 intr_establish(ih->ih_pil, level != IPL_VM, ih); 582 583 if (intrmapptr != NULL) { 584 u_int64_t imap; 585 586 imap = *intrmapptr; 587 DPRINTF(PDB_INTR, ("%s: read intrmap = %016qx", __func__, 588 (unsigned long long)imap)); 589 imap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK; 590 imap |= FIRE_INTRMAP_INT_CNTRL_NUM0; 591 DPRINTF(PDB_INTR, ("; set intr group intrmap = %016qx", 592 (unsigned long long)imap)); 593 if (sc->sc_oberon) { 594 imap &= ~OBERON_INTRMAP_T_DESTID_MASK; 595 imap |= CPU_JUPITERID << 596 OBERON_INTRMAP_T_DESTID_SHIFT; 597 } else { 598 imap &= ~FIRE_INTRMAP_T_JPID_MASK; 599 imap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT; 600 } 601 DPRINTF(PDB_INTR, ("; set cpuid num intrmap = %016qx", 602 (unsigned long long)imap)); 603 imap |= INTMAP_V; 604 *intrmapptr = imap; 605 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx", 606 (unsigned long long)imap)); 607 imap = *intrmapptr; 608 ih->ih_number |= imap & INTMAP_INR; 609 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx, " 610 "set ih_number to %x\n", 611 (unsigned long long)imap, ih->ih_number)); 612 } 613 if (intrclrptr) { 614 /* set state to IDLE */ 615 *intrclrptr = 0; 616 } 617 618 return (ih); 619 } 620 621 static void * 622 pyro_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 623 int (*func)(void *), void *arg) 624 { 625 void *cookie; 626 struct pyro_pbm *pbm = (struct pyro_pbm *)pc->cookie; 627 628 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d\n", __func__, (u_long)ih, level)); 629 cookie = bus_intr_establish(pbm->pp_memt, ih, level, func, arg); 630 631 DPRINTF(PDB_INTR, ("%s: returning handle %p\n", __func__, cookie)); 632 return (cookie); 633 } 634
Indexes created Wed Sep 24 15:09:51 GMT 2025