pyro.c revision 1.17
1 /* $NetBSD: pyro.c,v 1.17 2016/05/10 19:23:59 palle Exp $ */ 2 /* from: $OpenBSD: pyro.c,v 1.20 2010/12/05 15:15:14 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2007 Mark Kettenis 8 * Copyright (c) 2011 Matthew R. Green 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pyro.c,v 1.17 2016/05/10 19:23:59 palle Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 #include <sys/malloc.h> 40 #include <sys/systm.h> 41 42 #define _SPARC_BUS_DMA_PRIVATE 43 #include <sys/bus.h> 44 #include <machine/autoconf.h> 45 46 #ifdef DDB 47 #include <machine/db_machdep.h> 48 #endif 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/dev/iommuvar.h> 55 #include <sparc64/dev/pyrovar.h> 56 57 #ifdef DEBUG 58 #define PDB_PROM 0x01 59 #define PDB_BUSMAP 0x02 60 #define PDB_INTR 0x04 61 #define PDB_CONF 0x08 62 int pyro_debug = 0x0; 63 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0) 64 #else 65 #define DPRINTF(l, s) 66 #endif 67 68 #define FIRE_RESET_GEN 0x7010 69 70 #define FIRE_RESET_GEN_XIR 0x0000000000000002L 71 72 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 73 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 74 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 75 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 76 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 77 #define FIRE_INTRMAP_T_JPID_SHIFT 26 78 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 79 80 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 81 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 82 83 extern struct sparc_pci_chipset _sparc_pci_chipset; 84 85 int pyro_match(device_t, cfdata_t, void *); 86 void pyro_attach(device_t, device_t, void *); 87 int pyro_print(void *, const char *); 88 89 CFATTACH_DECL_NEW(pyro, sizeof(struct pyro_softc), 90 pyro_match, pyro_attach, NULL, NULL); 91 92 void pyro_init(struct pyro_softc *, int); 93 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *); 94 95 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int, 96 pci_chipset_tag_t); 97 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *); 98 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *); 99 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *); 100 bus_space_tag_t pyro_alloc_bus_tag(struct pyro_pbm *, const char *, int); 101 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *); 102 103 #if 0 104 int pyro_conf_size(pci_chipset_tag_t, pcitag_t); 105 #endif 106 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int); 107 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 108 109 static void * pyro_pci_intr_establish(pci_chipset_tag_t pc, 110 pci_intr_handle_t ih, int level, 111 int (*func)(void *), void *arg); 112 113 int pyro_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 114 int pyro_bus_map(bus_space_tag_t, bus_addr_t, 115 bus_size_t, int, vaddr_t, bus_space_handle_t *); 116 paddr_t pyro_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, 117 int, int); 118 void *pyro_intr_establish(bus_space_tag_t, int, int, 119 int (*)(void *), void *, void (*)(void)); 120 121 int pyro_dmamap_create(bus_dma_tag_t, bus_size_t, int, 122 bus_size_t, bus_size_t, int, bus_dmamap_t *); 123 124 int 125 pyro_match(device_t parent, cfdata_t match, void *aux) 126 { 127 struct mainbus_attach_args *ma = aux; 128 char *str; 129 130 if (strcmp(ma->ma_name, "pci") != 0) 131 return (0); 132 133 str = prom_getpropstring(ma->ma_node, "compatible"); 134 if (strcmp(str, "pciex108e,80f0") == 0 || 135 strcmp(str, "pciex108e,80f8") == 0) 136 return (1); 137 138 return (0); 139 } 140 141 void 142 pyro_attach(device_t parent, device_t self, void *aux) 143 { 144 struct pyro_softc *sc = device_private(self); 145 struct mainbus_attach_args *ma = aux; 146 char *str; 147 int busa; 148 149 sc->sc_dev = self; 150 sc->sc_node = ma->ma_node; 151 sc->sc_dmat = ma->ma_dmatag; 152 sc->sc_bustag = ma->ma_bustag; 153 sc->sc_csr = ma->ma_reg[0].ur_paddr; 154 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 155 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 156 157 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 158 busa = 1; 159 else 160 busa = 0; 161 162 if (bus_space_map(sc->sc_bustag, sc->sc_csr, 163 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, &sc->sc_csrh)) { 164 printf(": failed to map csr registers\n"); 165 return; 166 } 167 168 if (bus_space_map(sc->sc_bustag, sc->sc_xbc, 169 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 170 printf(": failed to map xbc registers\n"); 171 return; 172 } 173 174 str = prom_getpropstring(ma->ma_node, "compatible"); 175 if (strcmp(str, "pciex108e,80f8") == 0) 176 sc->sc_oberon = 1; 177 178 pyro_init(sc, busa); 179 } 180 181 void 182 pyro_init(struct pyro_softc *sc, int busa) 183 { 184 struct pyro_pbm *pbm; 185 struct pcibus_attach_args pba; 186 int *busranges = NULL, nranges; 187 188 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 189 if (pbm == NULL) 190 panic("pyro: can't alloc pyro pbm"); 191 192 pbm->pp_sc = sc; 193 pbm->pp_bus_a = busa; 194 195 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct pyro_range), 196 &pbm->pp_nrange, (void **)&pbm->pp_range)) 197 panic("pyro: can't get ranges"); 198 199 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 200 (void **)&busranges)) 201 panic("pyro: can't get bus-range"); 202 203 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n", 204 sc->sc_oberon ? "Oberon" : "Fire", 205 prom_getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign, 206 busa ? 'A' : 'B', busranges[0], busranges[1]); 207 208 printf("%s: ", device_xname(sc->sc_dev)); 209 pyro_init_iommu(sc, pbm); 210 211 pbm->pp_memt = pyro_alloc_mem_tag(pbm); 212 pbm->pp_iot = pyro_alloc_io_tag(pbm); 213 pbm->pp_cfgt = pyro_alloc_config_tag(pbm); 214 pbm->pp_dmat = pyro_alloc_dma_tag(pbm); 215 pbm->pp_flags = (pbm->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 216 (pbm->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 217 218 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh)) 219 panic("pyro: can't map config space"); 220 221 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 222 pbm->pp_pc->spc_busmax = busranges[1]; 223 pbm->pp_pc->spc_busnode = malloc(sizeof(*pbm->pp_pc->spc_busnode), 224 M_DEVBUF, M_NOWAIT | M_ZERO); 225 if (pbm->pp_pc->spc_busnode == NULL) 226 panic("pyro: malloc busnode"); 227 228 #if 0 229 pbm->pp_pc->bustag = pbm->pp_cfgt; 230 pbm->pp_pc->bushandle = pbm->pp_cfgh; 231 #endif 232 233 bzero(&pba, sizeof(pba)); 234 pba.pba_bus = busranges[0]; 235 pba.pba_pc = pbm->pp_pc; 236 pba.pba_flags = pbm->pp_flags; 237 pba.pba_dmat = pbm->pp_dmat; 238 pba.pba_dmat64 = NULL; /* XXX */ 239 pba.pba_memt = pbm->pp_memt; 240 pba.pba_iot = pbm->pp_iot; 241 242 free(busranges, M_DEVBUF); 243 244 config_found(sc->sc_dev, &pba, pyro_print); 245 } 246 247 void 248 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm) 249 { 250 struct iommu_state *is = &pbm->pp_is; 251 int tsbsize = 7; 252 u_int32_t iobase = -1; 253 char *name; 254 255 pbm->pp_sb.sb_is = is; 256 is->is_bustag = sc->sc_bustag; 257 258 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 259 0x40000, 0x100, &is->is_iommu)) { 260 panic("pyro: unable to create iommu handle"); 261 } 262 263 /* We have no STC. */ 264 is->is_sb[0] = NULL; 265 266 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 267 if (name == NULL) 268 panic("couldn't malloc iommu name"); 269 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 270 271 /* Tell iommu how to set the TSB size. */ 272 is->is_flags = IOMMU_TSBSIZE_IN_PTSB; 273 274 /* On Oberon, we need to flush the cache. */ 275 if (sc->sc_oberon) 276 is->is_flags |= IOMMU_FLUSH_CACHE; 277 278 iommu_init(name, is, tsbsize, iobase); 279 } 280 281 int 282 pyro_print(void *aux, const char *p) 283 { 284 if (p == NULL) 285 return (UNCONF); 286 return (QUIET); 287 } 288 289 pcireg_t 290 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 291 { 292 struct pyro_pbm *pp = pc->cookie; 293 struct cpu_info *ci = curcpu(); 294 pcireg_t val = (pcireg_t)~0; 295 int s; 296 297 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 298 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 299 s = splhigh(); 300 ci->ci_pci_probe = true; 301 membar_Sync(); 302 val = bus_space_read_4(pp->pp_cfgt, pp->pp_cfgh, 303 (PCITAG_OFFSET(tag) << 4) + reg); 304 membar_Sync(); 305 if (ci->ci_pci_fault) 306 val = (pcireg_t)~0; 307 ci->ci_pci_probe = ci->ci_pci_fault = false; 308 splx(s); 309 } 310 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 311 return (val); 312 } 313 314 void 315 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 316 { 317 struct pyro_pbm *pp = pc->cookie; 318 319 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 320 (long)tag, reg, (int)data)); 321 322 /* If we don't know it, just punt it. */ 323 if (PCITAG_NODE(tag) == -1) { 324 DPRINTF(PDB_CONF, (" .. bad addr\n")); 325 return; 326 } 327 328 if ((unsigned int)reg >= PCI_CONF_SIZE) 329 return; 330 331 bus_space_write_4(pp->pp_cfgt, pp->pp_cfgh, 332 (PCITAG_OFFSET(tag) << 4) + reg, data); 333 DPRINTF(PDB_CONF, (" .. done\n")); 334 } 335 336 /* 337 * Bus-specific interrupt mapping 338 */ 339 int 340 pyro_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 341 { 342 struct pyro_pbm *pp = pa->pa_pc->cookie; 343 struct pyro_softc *sc = pp->pp_sc; 344 u_int dev; 345 346 if (*ihp != (pci_intr_handle_t)-1) { 347 *ihp |= sc->sc_ign; 348 DPRINTF(PDB_INTR, ("%s: not -1 -> ih %lx\n", __func__, (u_long)*ihp)); 349 return (0); 350 } 351 352 /* 353 * We didn't find a PROM mapping for this interrupt. Try to 354 * construct one ourselves based on the swizzled interrupt pin 355 * and the interrupt mapping for PCI slots documented in the 356 * UltraSPARC-IIi User's Manual. 357 */ 358 359 if (pa->pa_intrpin == 0) { 360 DPRINTF(PDB_INTR, ("%s: no intrpen\n", __func__)); 361 return (-1); 362 } 363 364 /* 365 * This deserves some documentation. Should anyone 366 * have anything official looking, please speak up. 367 */ 368 dev = pa->pa_device - 1; 369 370 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 371 *ihp |= (dev << 2) & INTMAP_PCISLOT; 372 *ihp |= sc->sc_ign; 373 374 DPRINTF(PDB_INTR, ("%s: weird hack -> ih %lx\n", __func__, (u_long)*ihp)); 375 return (0); 376 } 377 378 bus_space_tag_t 379 pyro_alloc_mem_tag(struct pyro_pbm *pp) 380 { 381 return (pyro_alloc_bus_tag(pp, "mem", PCI_MEMORY_BUS_SPACE)); 382 } 383 384 bus_space_tag_t 385 pyro_alloc_io_tag(struct pyro_pbm *pp) 386 { 387 return (pyro_alloc_bus_tag(pp, "io", PCI_IO_BUS_SPACE)); 388 } 389 390 bus_space_tag_t 391 pyro_alloc_config_tag(struct pyro_pbm *pp) 392 { 393 return (pyro_alloc_bus_tag(pp, "cfg", PCI_CONFIG_BUS_SPACE)); 394 } 395 396 bus_space_tag_t 397 pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int type) 398 { 399 struct pyro_softc *sc = pbm->pp_sc; 400 struct sparc_bus_space_tag *bt; 401 402 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 403 if (bt == NULL) 404 panic("pyro: could not allocate bus tag"); 405 406 #if 0 407 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 408 device_xname(sc->sc_dev), name, ss, asi); 409 #endif 410 411 bt->cookie = pbm; 412 bt->parent = sc->sc_bustag; 413 bt->type = type; 414 bt->sparc_bus_map = pyro_bus_map; 415 bt->sparc_bus_mmap = pyro_bus_mmap; 416 bt->sparc_intr_establish = pyro_intr_establish; 417 return (bt); 418 } 419 420 bus_dma_tag_t 421 pyro_alloc_dma_tag(struct pyro_pbm *pbm) 422 { 423 struct pyro_softc *sc = pbm->pp_sc; 424 bus_dma_tag_t dt, pdt = sc->sc_dmat; 425 426 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 427 if (dt == NULL) 428 panic("pyro: could not alloc dma tag"); 429 430 dt->_cookie = pbm; 431 dt->_parent = pdt; 432 #define PCOPY(x) dt->x = pdt->x 433 dt->_dmamap_create = pyro_dmamap_create; 434 PCOPY(_dmamap_destroy); 435 dt->_dmamap_load = iommu_dvmamap_load; 436 PCOPY(_dmamap_load_mbuf); 437 PCOPY(_dmamap_load_uio); 438 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 439 dt->_dmamap_unload = iommu_dvmamap_unload; 440 dt->_dmamap_sync = iommu_dvmamap_sync; 441 dt->_dmamem_alloc = iommu_dvmamem_alloc; 442 dt->_dmamem_free = iommu_dvmamem_free; 443 dt->_dmamem_map = iommu_dvmamem_map; 444 dt->_dmamem_unmap = iommu_dvmamem_unmap; 445 PCOPY(_dmamem_mmap); 446 #undef PCOPY 447 return (dt); 448 } 449 450 pci_chipset_tag_t 451 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc) 452 { 453 pci_chipset_tag_t npc; 454 455 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 456 if (npc == NULL) 457 panic("pyro: could not allocate pci_chipset_tag_t"); 458 memcpy(npc, pc, sizeof *pc); 459 npc->cookie = pbm; 460 npc->rootnode = node; 461 npc->spc_conf_read = pyro_conf_read; 462 npc->spc_conf_write = pyro_conf_write; 463 npc->spc_intr_map = pyro_intr_map; 464 npc->spc_intr_establish = pyro_pci_intr_establish; 465 npc->spc_find_ino = NULL; 466 return (npc); 467 } 468 469 int 470 pyro_dmamap_create(bus_dma_tag_t t, bus_size_t size, 471 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 472 bus_dmamap_t *dmamp) 473 { 474 struct pyro_pbm *pbm = t->_cookie; 475 int error; 476 477 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 478 boundary, flags, dmamp); 479 if (error == 0) 480 (*dmamp)->_dm_cookie = &pbm->pp_sb; 481 return error; 482 } 483 484 int 485 pyro_bus_map(bus_space_tag_t t, bus_addr_t offset, 486 bus_size_t size, int flags, vaddr_t unused, bus_space_handle_t *hp) 487 { 488 struct pyro_pbm *pbm = t->cookie; 489 struct pyro_softc *sc = pbm->pp_sc; 490 int i, ss; 491 492 DPRINTF(PDB_BUSMAP, ("pyro_bus_map: type %d off %qx sz %qx flags %d", 493 t->type, 494 (unsigned long long)offset, 495 (unsigned long long)size, 496 flags)); 497 498 ss = sparc_pci_childspace(t->type); 499 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 500 501 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 502 printf("\n_pyro_bus_map: invalid parent"); 503 return (EINVAL); 504 } 505 506 for (i = 0; i < pbm->pp_nrange; i++) { 507 bus_addr_t paddr; 508 struct pyro_range *pr = &pbm->pp_range[i]; 509 510 if (((pr->cspace >> 24) & 0x03) != ss) 511 continue; 512 513 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 514 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 515 flags, 0, hp)); 516 } 517 518 return (EINVAL); 519 } 520 521 paddr_t 522 pyro_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 523 off_t off, int prot, int flags) 524 { 525 bus_addr_t offset = paddr; 526 struct pyro_pbm *pbm = t->cookie; 527 struct pyro_softc *sc = pbm->pp_sc; 528 int i, ss; 529 530 ss = sparc_pci_childspace(t->type); 531 532 DPRINTF(PDB_BUSMAP, ("pyro_bus_mmap: prot %d flags %d pa %qx\n", 533 prot, flags, (unsigned long long)paddr)); 534 535 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 536 printf("\n_pyro_bus_mmap: invalid parent"); 537 return (-1); 538 } 539 540 for (i = 0; i < pbm->pp_nrange; i++) { 541 struct pyro_range *pr = &pbm->pp_range[i]; 542 543 if (((pr->cspace >> 24) & 0x03) != ss) 544 continue; 545 546 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 547 return (bus_space_mmap(sc->sc_bustag, paddr, off, 548 prot, flags)); 549 } 550 551 return (-1); 552 } 553 554 void * 555 pyro_intr_establish(bus_space_tag_t t, int ihandle, int level, 556 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 557 { 558 struct pyro_pbm *pbm = t->cookie; 559 struct pyro_softc *sc = pbm->pp_sc; 560 struct intrhand *ih = NULL; 561 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 562 u_int64_t *imapbase, *iclrbase; 563 int ino; 564 565 ino = INTINO(ihandle); 566 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d ino %#x", __func__, (u_long)ihandle, level, ino)); 567 568 if (level == IPL_NONE) 569 level = INTLEV(ihandle); 570 if (level == IPL_NONE) { 571 printf(": no IPL, setting IPL 2.\n"); 572 level = 2; 573 } 574 575 imapbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1000); 576 iclrbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1400); 577 intrmapptr = &imapbase[ino]; 578 intrclrptr = &iclrbase[ino]; 579 DPRINTF(PDB_INTR, (" mapptr %p clrptr %p\n", intrmapptr, intrclrptr)); 580 581 ino |= INTVEC(ihandle); 582 583 ih = intrhand_alloc(); 584 585 /* Register the map and clear intr registers */ 586 ih->ih_map = intrmapptr; 587 ih->ih_clr = intrclrptr; 588 589 ih->ih_ivec = ihandle; 590 ih->ih_fun = handler; 591 ih->ih_arg = arg; 592 ih->ih_pil = level; 593 ih->ih_number = ino; 594 ih->ih_pending = 0; 595 596 intr_establish(ih->ih_pil, level != IPL_VM, ih); 597 598 if (intrmapptr != NULL) { 599 u_int64_t imap; 600 601 imap = *intrmapptr; 602 DPRINTF(PDB_INTR, ("%s: read intrmap = %016qx", __func__, 603 (unsigned long long)imap)); 604 imap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK; 605 imap |= FIRE_INTRMAP_INT_CNTRL_NUM0; 606 DPRINTF(PDB_INTR, ("; set intr group intrmap = %016qx", 607 (unsigned long long)imap)); 608 if (sc->sc_oberon) { 609 imap &= ~OBERON_INTRMAP_T_DESTID_MASK; 610 imap |= CPU_JUPITERID << 611 OBERON_INTRMAP_T_DESTID_SHIFT; 612 } else { 613 imap &= ~FIRE_INTRMAP_T_JPID_MASK; 614 imap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT; 615 } 616 DPRINTF(PDB_INTR, ("; set cpuid num intrmap = %016qx", 617 (unsigned long long)imap)); 618 imap |= INTMAP_V; 619 *intrmapptr = imap; 620 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx", 621 (unsigned long long)imap)); 622 imap = *intrmapptr; 623 ih->ih_number |= imap & INTMAP_INR; 624 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx, " 625 "set ih_number to %x\n", 626 (unsigned long long)imap, ih->ih_number)); 627 } 628 if (intrclrptr) { 629 /* set state to IDLE */ 630 *intrclrptr = 0; 631 } 632 633 return (ih); 634 } 635 636 static void * 637 pyro_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 638 int (*func)(void *), void *arg) 639 { 640 void *cookie; 641 struct pyro_pbm *pbm = (struct pyro_pbm *)pc->cookie; 642 643 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d\n", __func__, (u_long)ih, level)); 644 cookie = bus_intr_establish(pbm->pp_memt, ih, level, func, arg); 645 646 DPRINTF(PDB_INTR, ("%s: returning handle %p\n", __func__, cookie)); 647 return (cookie); 648 } 649
Indexes created Tue Sep 23 07:09:52 GMT 2025