pyro.c revision 1.4
1 /* $NetBSD: pyro.c,v 1.4 2011/04/04 20:37:54 dyoung Exp $ */ 2 /* from: $OpenBSD: pyro.c,v 1.20 2010/12/05 15:15:14 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2007 Mark Kettenis 8 * Copyright (c) 2011 Matthew R. Green 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/errno.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 39 #define _SPARC_BUS_DMA_PRIVATE 40 #include <machine/bus.h> 41 #include <machine/autoconf.h> 42 43 #ifdef DDB 44 #include <machine/db_machdep.h> 45 #endif 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include <sparc64/dev/iommureg.h> 51 #include <sparc64/dev/iommuvar.h> 52 #include <sparc64/dev/pyrovar.h> 53 54 #ifdef DEBUG 55 #define PDB_PROM 0x01 56 #define PDB_BUSMAP 0x02 57 #define PDB_INTR 0x04 58 #define PDB_CONF 0x08 59 int pyro_debug = 0x4; 60 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0) 61 #else 62 #define DPRINTF(l, s) 63 #endif 64 65 #define FIRE_RESET_GEN 0x7010 66 67 #define FIRE_RESET_GEN_XIR 0x0000000000000002L 68 69 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 70 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 71 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 72 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 73 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 74 #define FIRE_INTRMAP_T_JPID_SHIFT 26 75 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 76 77 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 78 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 79 80 extern struct sparc_pci_chipset _sparc_pci_chipset; 81 82 int pyro_match(struct device *, struct cfdata *, void *); 83 void pyro_attach(struct device *, struct device *, void *); 84 int pyro_print(void *, const char *); 85 86 CFATTACH_DECL(pyro, sizeof(struct pyro_softc), 87 pyro_match, pyro_attach, NULL, NULL); 88 89 void pyro_init(struct pyro_softc *, int); 90 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *); 91 92 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int, 93 pci_chipset_tag_t); 94 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *); 95 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *); 96 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *); 97 bus_space_tag_t pyro_alloc_bus_tag(struct pyro_pbm *, const char *, int); 98 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *); 99 100 #if 0 101 int pyro_conf_size(pci_chipset_tag_t, pcitag_t); 102 #endif 103 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int); 104 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 105 106 static void * pyro_pci_intr_establish(pci_chipset_tag_t pc, 107 pci_intr_handle_t ih, int level, 108 int (*func)(void *), void *arg); 109 110 int pyro_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 111 int pyro_bus_map(bus_space_tag_t, bus_addr_t, 112 bus_size_t, int, vaddr_t, bus_space_handle_t *); 113 paddr_t pyro_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, 114 int, int); 115 void *pyro_intr_establish(bus_space_tag_t, int, int, 116 int (*)(void *), void *, void (*)(void)); 117 118 int pyro_dmamap_create(bus_dma_tag_t, bus_size_t, int, 119 bus_size_t, bus_size_t, int, bus_dmamap_t *); 120 121 int 122 pyro_match(struct device *parent, struct cfdata *match, void *aux) 123 { 124 struct mainbus_attach_args *ma = aux; 125 char *str; 126 127 if (strcmp(ma->ma_name, "pci") != 0) 128 return (0); 129 130 str = prom_getpropstring(ma->ma_node, "compatible"); 131 if (strcmp(str, "pciex108e,80f0") == 0 || 132 strcmp(str, "pciex108e,80f8") == 0) 133 return (1); 134 135 return (0); 136 } 137 138 void 139 pyro_attach(struct device *parent, struct device *self, void *aux) 140 { 141 struct pyro_softc *sc = (struct pyro_softc *)self; 142 struct mainbus_attach_args *ma = aux; 143 char *str; 144 int busa; 145 146 sc->sc_node = ma->ma_node; 147 sc->sc_dmat = ma->ma_dmatag; 148 sc->sc_bustag = ma->ma_bustag; 149 sc->sc_csr = ma->ma_reg[0].ur_paddr; 150 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 151 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 152 153 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 154 busa = 1; 155 else 156 busa = 0; 157 158 if (bus_space_map(sc->sc_bustag, sc->sc_csr, 159 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, &sc->sc_csrh)) { 160 printf(": failed to map csr registers\n"); 161 return; 162 } 163 164 if (bus_space_map(sc->sc_bustag, sc->sc_xbc, 165 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 166 printf(": failed to map xbc registers\n"); 167 return; 168 } 169 170 str = prom_getpropstring(ma->ma_node, "compatible"); 171 if (strcmp(str, "pciex108e,80f8") == 0) 172 sc->sc_oberon = 1; 173 174 pyro_init(sc, busa); 175 } 176 177 void 178 pyro_init(struct pyro_softc *sc, int busa) 179 { 180 struct pyro_pbm *pbm; 181 struct pcibus_attach_args pba; 182 int *busranges = NULL, nranges; 183 184 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 185 if (pbm == NULL) 186 panic("pyro: can't alloc pyro pbm"); 187 188 pbm->pp_sc = sc; 189 pbm->pp_bus_a = busa; 190 191 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct pyro_range), 192 &pbm->pp_nrange, (void **)&pbm->pp_range)) 193 panic("pyro: can't get ranges"); 194 195 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 196 (void **)&busranges)) 197 panic("pyro: can't get bus-range"); 198 199 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n", 200 sc->sc_oberon ? "Oberon" : "Fire", 201 prom_getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign, 202 busa ? 'A' : 'B', busranges[0], busranges[1]); 203 204 printf("%s: ", sc->sc_dv.dv_xname); 205 pyro_init_iommu(sc, pbm); 206 207 pbm->pp_memt = pyro_alloc_mem_tag(pbm); 208 pbm->pp_iot = pyro_alloc_io_tag(pbm); 209 pbm->pp_cfgt = pyro_alloc_config_tag(pbm); 210 pbm->pp_dmat = pyro_alloc_dma_tag(pbm); 211 pbm->pp_flags = (pbm->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 212 (pbm->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 213 214 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh)) 215 panic("pyro: can't map config space"); 216 217 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 218 pbm->pp_pc->spc_busmax = busranges[1]; 219 pbm->pp_pc->spc_busnode = malloc(sizeof(*pbm->pp_pc->spc_busnode), 220 M_DEVBUF, M_NOWAIT | M_ZERO); 221 if (pbm->pp_pc->spc_busnode == NULL) 222 panic("schizo: malloc busnode"); 223 224 #if 0 225 pbm->pp_pc->bustag = pbm->pp_cfgt; 226 pbm->pp_pc->bushandle = pbm->pp_cfgh; 227 #endif 228 229 bzero(&pba, sizeof(pba)); 230 pba.pba_bus = busranges[0]; 231 pba.pba_pc = pbm->pp_pc; 232 pba.pba_flags = pbm->pp_flags; 233 pba.pba_dmat = pbm->pp_dmat; 234 pba.pba_dmat64 = NULL; /* XXX */ 235 pba.pba_memt = pbm->pp_memt; 236 pba.pba_iot = pbm->pp_iot; 237 238 free(busranges, M_DEVBUF); 239 240 config_found(&sc->sc_dv, &pba, pyro_print); 241 } 242 243 void 244 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm) 245 { 246 struct iommu_state *is = &pbm->pp_is; 247 int tsbsize = 7; 248 u_int32_t iobase = -1; 249 char *name; 250 251 pbm->pp_sb.sb_is = is; 252 is->is_bustag = sc->sc_bustag; 253 254 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 255 0x40000, 0x100, &is->is_iommu)) { 256 panic("pyro: unable to create iommu handle"); 257 } 258 259 /* We have no STC. */ 260 is->is_sb[0] = NULL; 261 262 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 263 if (name == NULL) 264 panic("couldn't malloc iommu name"); 265 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 266 267 /* Tell iommu how to set the TSB size. */ 268 is->is_flags = IOMMU_TSBSIZE_IN_PTSB; 269 270 /* On Oberon, we need to flush the cache. */ 271 if (sc->sc_oberon) 272 is->is_flags |= IOMMU_FLUSH_CACHE; 273 274 iommu_init(name, is, tsbsize, iobase); 275 } 276 277 int 278 pyro_print(void *aux, const char *p) 279 { 280 if (p == NULL) 281 return (UNCONF); 282 return (QUIET); 283 } 284 285 pcireg_t 286 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 287 { 288 struct pyro_pbm *pp = pc->cookie; 289 pcireg_t val = (pcireg_t)~0; 290 291 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 292 if (PCITAG_NODE(tag) != -1) 293 val = bus_space_read_4(pp->pp_cfgt, pp->pp_cfgh, 294 (PCITAG_OFFSET(tag) << 4) + reg); 295 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 296 return (val); 297 } 298 299 void 300 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 301 { 302 struct pyro_pbm *pp = pc->cookie; 303 304 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 305 (long)tag, reg, (int)data)); 306 307 /* If we don't know it, just punt it. */ 308 if (PCITAG_NODE(tag) == -1) { 309 DPRINTF(PDB_CONF, (" .. bad addr\n")); 310 return; 311 } 312 313 bus_space_write_4(pp->pp_cfgt, pp->pp_cfgh, 314 (PCITAG_OFFSET(tag) << 4) + reg, data); 315 DPRINTF(PDB_CONF, (" .. done\n")); 316 } 317 318 /* 319 * Bus-specific interrupt mapping 320 */ 321 int 322 pyro_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 323 { 324 struct pyro_pbm *pp = pa->pa_pc->cookie; 325 struct pyro_softc *sc = pp->pp_sc; 326 u_int dev; 327 328 if (*ihp != (pci_intr_handle_t)-1) { 329 *ihp |= sc->sc_ign; 330 DPRINTF(PDB_INTR, ("%s: not -1 -> ih %lx\n", __func__, (u_long)*ihp)); 331 return (0); 332 } 333 334 /* 335 * We didn't find a PROM mapping for this interrupt. Try to 336 * construct one ourselves based on the swizzled interrupt pin 337 * and the interrupt mapping for PCI slots documented in the 338 * UltraSPARC-IIi User's Manual. 339 */ 340 341 if (pa->pa_intrpin == 0) { 342 DPRINTF(PDB_INTR, ("%s: no intrpen\n", __func__)); 343 return (-1); 344 } 345 346 /* 347 * This deserves some documentation. Should anyone 348 * have anything official looking, please speak up. 349 */ 350 dev = pa->pa_device - 1; 351 352 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 353 *ihp |= (dev << 2) & INTMAP_PCISLOT; 354 *ihp |= sc->sc_ign; 355 356 DPRINTF(PDB_INTR, ("%s: weird hack -> ih %lx\n", __func__, (u_long)*ihp)); 357 return (0); 358 } 359 360 bus_space_tag_t 361 pyro_alloc_mem_tag(struct pyro_pbm *pp) 362 { 363 return (pyro_alloc_bus_tag(pp, "mem", PCI_MEMORY_BUS_SPACE)); 364 } 365 366 bus_space_tag_t 367 pyro_alloc_io_tag(struct pyro_pbm *pp) 368 { 369 return (pyro_alloc_bus_tag(pp, "io", PCI_IO_BUS_SPACE)); 370 } 371 372 bus_space_tag_t 373 pyro_alloc_config_tag(struct pyro_pbm *pp) 374 { 375 return (pyro_alloc_bus_tag(pp, "cfg", PCI_CONFIG_BUS_SPACE)); 376 } 377 378 bus_space_tag_t 379 pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int type) 380 { 381 struct pyro_softc *sc = pbm->pp_sc; 382 struct sparc_bus_space_tag *bt; 383 384 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 385 if (bt == NULL) 386 panic("pyro: could not allocate bus tag"); 387 388 #if 0 389 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 390 sc->sc_dv.dv_xname, name, ss, asi); 391 #endif 392 393 bt->cookie = pbm; 394 bt->parent = sc->sc_bustag; 395 bt->type = type; 396 bt->sparc_bus_map = pyro_bus_map; 397 bt->sparc_bus_mmap = pyro_bus_mmap; 398 bt->sparc_intr_establish = pyro_intr_establish; 399 return (bt); 400 } 401 402 bus_dma_tag_t 403 pyro_alloc_dma_tag(struct pyro_pbm *pbm) 404 { 405 struct pyro_softc *sc = pbm->pp_sc; 406 bus_dma_tag_t dt, pdt = sc->sc_dmat; 407 408 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 409 if (dt == NULL) 410 panic("pyro: could not alloc dma tag"); 411 412 dt->_cookie = pbm; 413 dt->_parent = pdt; 414 #define PCOPY(x) dt->x = pdt->x 415 dt->_dmamap_create = pyro_dmamap_create; 416 PCOPY(_dmamap_destroy); 417 dt->_dmamap_load = iommu_dvmamap_load; 418 PCOPY(_dmamap_load_mbuf); 419 PCOPY(_dmamap_load_uio); 420 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 421 dt->_dmamap_unload = iommu_dvmamap_unload; 422 dt->_dmamap_sync = iommu_dvmamap_sync; 423 dt->_dmamem_alloc = iommu_dvmamem_alloc; 424 dt->_dmamem_free = iommu_dvmamem_free; 425 dt->_dmamem_map = iommu_dvmamem_map; 426 dt->_dmamem_unmap = iommu_dvmamem_unmap; 427 PCOPY(_dmamem_mmap); 428 #undef PCOPY 429 return (dt); 430 } 431 432 pci_chipset_tag_t 433 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc) 434 { 435 pci_chipset_tag_t npc; 436 437 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 438 if (npc == NULL) 439 panic("pyro: could not allocate pci_chipset_tag_t"); 440 memcpy(npc, pc, sizeof *pc); 441 npc->cookie = pbm; 442 npc->rootnode = node; 443 npc->spc_conf_read = pyro_conf_read; 444 npc->spc_conf_write = pyro_conf_write; 445 npc->spc_intr_map = pyro_intr_map; 446 npc->spc_intr_establish = pyro_pci_intr_establish; 447 npc->spc_find_ino = NULL; 448 return (npc); 449 } 450 451 int 452 pyro_dmamap_create(bus_dma_tag_t t, bus_size_t size, 453 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 454 bus_dmamap_t *dmamp) 455 { 456 struct pyro_pbm *pbm = t->_cookie; 457 int error; 458 459 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 460 boundary, flags, dmamp); 461 if (error == 0) 462 (*dmamp)->_dm_cookie = &pbm->pp_sb; 463 return error; 464 } 465 466 int 467 pyro_bus_map(bus_space_tag_t t, bus_addr_t offset, 468 bus_size_t size, int flags, vaddr_t unused, bus_space_handle_t *hp) 469 { 470 struct pyro_pbm *pbm = t->cookie; 471 struct pyro_softc *sc = pbm->pp_sc; 472 int i, ss; 473 474 DPRINTF(PDB_BUSMAP, ("pyro_bus_map: type %d off %qx sz %qx flags %d", 475 t->type, 476 (unsigned long long)offset, 477 (unsigned long long)size, 478 flags)); 479 480 ss = sparc_pci_childspace(t->type); 481 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 482 483 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 484 printf("\n_pyro_bus_map: invalid parent"); 485 return (EINVAL); 486 } 487 488 for (i = 0; i < pbm->pp_nrange; i++) { 489 bus_addr_t paddr; 490 struct pyro_range *pr = &pbm->pp_range[i]; 491 492 if (((pr->cspace >> 24) & 0x03) != ss) 493 continue; 494 495 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 496 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 497 flags, 0, hp)); 498 } 499 500 return (EINVAL); 501 } 502 503 paddr_t 504 pyro_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 505 off_t off, int prot, int flags) 506 { 507 bus_addr_t offset = paddr; 508 struct pyro_pbm *pbm = t->cookie; 509 struct pyro_softc *sc = pbm->pp_sc; 510 int i, ss; 511 512 ss = sparc_pci_childspace(t->type); 513 514 DPRINTF(PDB_BUSMAP, ("pyro_bus_mmap: prot %d flags %d pa %qx\n", 515 prot, flags, (unsigned long long)paddr)); 516 517 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 518 printf("\n_pyro_bus_mmap: invalid parent"); 519 return (-1); 520 } 521 522 for (i = 0; i < pbm->pp_nrange; i++) { 523 struct pyro_range *pr = &pbm->pp_range[i]; 524 525 if (((pr->cspace >> 24) & 0x03) != ss) 526 continue; 527 528 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 529 return (bus_space_mmap(sc->sc_bustag, paddr, off, 530 prot, flags)); 531 } 532 533 return (-1); 534 } 535 536 void * 537 pyro_intr_establish(bus_space_tag_t t, int ihandle, int level, 538 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 539 { 540 struct pyro_pbm *pbm = t->cookie; 541 struct pyro_softc *sc = pbm->pp_sc; 542 struct intrhand *ih = NULL; 543 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 544 u_int64_t *imapbase, *iclrbase; 545 int ino; 546 547 ino = INTINO(ihandle); 548 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d ino %d", __func__, (u_long)ih, level, ino)); 549 550 if (level == IPL_NONE) 551 level = INTLEV(ihandle); 552 if (level == IPL_NONE) { 553 printf(": no IPL, setting IPL 2.\n"); 554 level = 2; 555 } 556 557 imapbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1000); 558 iclrbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1400); 559 intrmapptr = &imapbase[ino]; 560 intrclrptr = &iclrbase[ino]; 561 DPRINTF(PDB_INTR, (" imapbase %p iclrbase %p mapptr %p clrptr %p\n", imapbase, iclrbase, intrmapptr, intrclrptr)); 562 ino |= INTVEC(ihandle); 563 564 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 565 if (ih == NULL) 566 return (NULL); 567 568 /* Register the map and clear intr registers */ 569 ih->ih_map = intrmapptr; 570 ih->ih_clr = intrclrptr; 571 572 ih->ih_fun = handler; 573 ih->ih_arg = arg; 574 ih->ih_pil = level; 575 ih->ih_number = ino; 576 577 intr_establish(ih->ih_pil, level != IPL_VM, ih); 578 579 if (intrmapptr != NULL) { 580 u_int64_t imap; 581 582 imap = *intrmapptr; 583 DPRINTF(PDB_INTR, ("%s: read intrmap = %016qx", __func__, 584 (unsigned long long)imap)); 585 imap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK; 586 imap |= FIRE_INTRMAP_INT_CNTRL_NUM0; 587 DPRINTF(PDB_INTR, ("; set intr group intrmap = %016qx", 588 (unsigned long long)imap)); 589 if (sc->sc_oberon) { 590 imap &= ~OBERON_INTRMAP_T_DESTID_MASK; 591 imap |= CPU_JUPITERID << 592 OBERON_INTRMAP_T_DESTID_SHIFT; 593 } else { 594 imap &= ~FIRE_INTRMAP_T_JPID_MASK; 595 imap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT; 596 } 597 DPRINTF(PDB_INTR, ("; set cpuid num intrmap = %016qx", 598 (unsigned long long)imap)); 599 imap |= INTMAP_V; 600 *intrmapptr = imap; 601 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx", 602 (unsigned long long)imap)); 603 imap = *intrmapptr; 604 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx\n", 605 (unsigned long long)imap)); 606 ih->ih_number |= imap & INTMAP_INR; 607 } 608 if (intrclrptr) { 609 /* set state to IDLE */ 610 *intrclrptr = 0; 611 } 612 613 return (ih); 614 } 615 616 static void * 617 pyro_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 618 int (*func)(void *), void *arg) 619 { 620 void *cookie; 621 struct pyro_pbm *pbm = (struct pyro_pbm *)pc->cookie; 622 623 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d\n", __func__, (u_long)ih, level)); 624 cookie = bus_intr_establish(pbm->pp_memt, ih, level, func, arg); 625 626 DPRINTF(PDB_INTR, ("%s: returning handle %p\n", __func__, cookie)); 627 return (cookie); 628 } 629
Indexes created Wed Sep 24 05:09:52 GMT 2025