sbus.c revision 1.2
1 /* $NetBSD: sbus.c,v 1.2 1998/07/07 03:05:02 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Sbus stuff. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/malloc.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <vm/vm.h> 92 93 #include <machine/bus.h> 94 #include <sparc64/sparc64/vaddrs.h> 95 #include <sparc64/dev/sbusreg.h> 96 #include <sparc64/dev/sbusvar.h> 97 #include <sparc64/sparc64/asm.h> 98 99 #include <machine/autoconf.h> 100 #include <machine/ctlreg.h> 101 #include <machine/cpu.h> 102 103 /* XXXXX -- Needed to allow dvma_mapin to work -- need to switch to bus_dma_* */ 104 struct sbus_softc *sbus0; 105 106 #ifdef DEBUG 107 #define SDB_DVMA 0x1 108 #define SDB_INTR 0x2 109 int sbusdebug = 0; 110 #endif 111 112 void sbusreset __P((int)); 113 int sbus_flush __P((struct sbus_softc *)); 114 115 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 116 static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *)); 117 static int sbus_get_intr __P((struct sbus_softc *, int, int *)); 118 static int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 119 int, bus_space_handle_t *)); 120 static int _sbus_bus_map __P(( 121 bus_space_tag_t, 122 bus_type_t, 123 bus_addr_t, /*offset*/ 124 bus_size_t, /*size*/ 125 int, /*flags*/ 126 vm_offset_t, /*preferred virtual address */ 127 bus_space_handle_t *)); 128 static void *sbus_intr_establish __P(( 129 bus_space_tag_t, 130 int, /*level*/ 131 int, /*flags*/ 132 int (*) __P((void *)), /*handler*/ 133 void *)); /*handler arg*/ 134 135 136 /* autoconfiguration driver */ 137 int sbus_match __P((struct device *, struct cfdata *, void *)); 138 void sbus_attach __P((struct device *, struct device *, void *)); 139 140 141 struct cfattach sbus_ca = { 142 sizeof(struct sbus_softc), sbus_match, sbus_attach 143 }; 144 145 extern struct cfdriver sbus_cd; 146 147 /* 148 * DVMA routines 149 */ 150 void sbus_enter __P((struct sbus_softc *, vm_offset_t, int64_t, int)); 151 void sbus_remove __P((struct sbus_softc *, vm_offset_t, int)); 152 int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 153 bus_size_t, struct proc *, int)); 154 void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 155 void sbus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 156 bus_size_t, int)); 157 int sbus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 158 bus_size_t alignment, bus_size_t boundary, 159 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags)); 160 void sbus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 161 int nsegs)); 162 int sbus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 163 int nsegs, size_t size, caddr_t *kvap, int flags)); 164 void sbus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 165 size_t size)); 166 167 168 /* 169 * Child devices receive the Sbus interrupt level in their attach 170 * arguments. We translate these to CPU IPLs using the following 171 * tables. Note: obio bus interrupt levels are identical to the 172 * processor IPL. 173 * 174 * The second set of tables is used when the Sbus interrupt level 175 * cannot be had from the PROM as an `interrupt' property. We then 176 * fall back on the `intr' property which contains the CPU IPL. 177 */ 178 179 /* Translate Sbus interrupt level to processor IPL */ 180 static int intr_sbus2ipl_4c[] = { 181 0, 1, 2, 3, 5, 7, 8, 9 182 }; 183 static int intr_sbus2ipl_4m[] = { 184 0, 2, 3, 5, 7, 9, 11, 13 185 }; 186 187 /* 188 * This value is or'ed into the attach args' interrupt level cookie 189 * if the interrupt level comes from an `intr' property, i.e. it is 190 * not an Sbus interrupt level. 191 */ 192 #define SBUS_INTR_COMPAT 0x80000000 193 194 195 /* 196 * Print the location of some sbus-attached device (called just 197 * before attaching that device). If `sbus' is not NULL, the 198 * device was found but not configured; print the sbus as well. 199 * Return UNCONF (config_find ignores this if the device was configured). 200 */ 201 int 202 sbus_print(args, busname) 203 void *args; 204 const char *busname; 205 { 206 struct sbus_attach_args *sa = args; 207 208 if (busname) 209 printf("%s at %s", sa->sa_name, busname); 210 printf(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset); 211 if (sa->sa_pri) { 212 int level = sa->sa_pri; 213 214 printf(" vector %x ipl %d", (int)INTVEC(level), (int)INTLEV(level)); 215 } 216 return (UNCONF); 217 } 218 219 int 220 sbus_match(parent, cf, aux) 221 struct device *parent; 222 struct cfdata *cf; 223 void *aux; 224 { 225 struct mainbus_attach_args *ma = aux; 226 227 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 228 } 229 230 /* 231 * Attach an Sbus. 232 */ 233 void 234 sbus_attach(parent, self, aux) 235 struct device *parent; 236 struct device *self; 237 void *aux; 238 { 239 struct sbus_softc *sc = sbus0 = (struct sbus_softc *)self; 240 struct mainbus_attach_args *ma = aux; 241 int node = ma->ma_node; 242 243 int node0, error; 244 bus_space_tag_t sbt; 245 struct sbus_attach_args sa; 246 char *busname = "sbus"; 247 struct bootpath *bp = ma->ma_bp; 248 249 250 sc->sc_bustag = ma->ma_bustag; 251 sc->sc_dmatag = ma->ma_dmatag; 252 sc->sc_sysio = (struct sysioreg*) ma->ma_address[0]; /* Use prom mapping for sysio. */ 253 sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */ 254 255 /* Setup interrupt translation tables */ 256 sc->sc_intr2ipl = CPU_ISSUN4C 257 ? intr_sbus2ipl_4c 258 : intr_sbus2ipl_4m; 259 260 /* 261 * Record clock frequency for synchronous SCSI. 262 * IS THIS THE CORRECT DEFAULT?? 263 */ 264 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 265 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 266 267 sbt = sbus_alloc_bustag(sc); 268 sc->sc_dmatag = sbus_alloc_dmatag(sc); 269 270 /* 271 * Get the SBus burst transfer size if burst transfers are supported 272 */ 273 sc->sc_burst = getpropint(node, "burst-sizes", 0); 274 275 /* Propagate bootpath */ 276 if (bp != NULL && strcmp(bp->name, busname) == 0) 277 bp++; 278 else 279 bp = NULL; 280 281 /* 282 * Collect address translations from the OBP. 283 */ 284 error = getpropA(node, "ranges", sizeof(struct sbus_range), 285 &sc->sc_nrange, (void **)&sc->sc_range); 286 switch (error) { 287 case 0: 288 break; 289 #if 0 290 case ENOENT: 291 /* Fall back to our own `range' construction */ 292 sc->sc_range = sbus_translations; 293 sc->sc_nrange = 294 sizeof(sbus_translations)/sizeof(sbus_translations[0]); 295 break; 296 #endif 297 default: 298 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 299 } 300 301 302 /* 303 * Setup the iommu. 304 * 305 * The sun4u iommu is part of the SBUS controller so we will 306 * deal with it here. We could try to fake a device node so 307 * we can eventually share it with the PCI bus run by psyco, 308 * but I don't want to get into that sort of cruft. 309 */ 310 311 /* 312 * All IOMMUs will share the same TSB which is allocated in pmap_bootstrap. 313 * 314 * This makes device management easier. 315 */ 316 { 317 extern int64_t *iotsb; 318 extern vm_offset_t iotsbp; 319 extern int iotsbsize; 320 321 sc->sc_tsbsize = iotsbsize; 322 sc->sc_tsb = iotsb; 323 sc->sc_ptsb = iotsbp; 324 } 325 #if 0 326 /* Need to do 64-bit stores */ 327 sc->sc_sysio->sys_iommu.iommu_cr = (IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN); 328 sc->sc_sysio->sys_iommu.iommu_tsb = sc->sc_ptsb; 329 #else 330 stxa(&sc->sc_sysio->sys_iommu.iommu_cr,ASI_NUCLEUS,(IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN)); 331 stxa(&sc->sc_sysio->sys_iommu.iommu_tsb,ASI_NUCLEUS,sc->sc_ptsb); 332 #endif 333 #ifdef DEBUG 334 if (sbusdebug & SDB_DVMA) 335 { 336 /* Probe the iommu */ 337 int64_t cr, tsb; 338 339 printf("iommu regs at: cr=%x tsb=%x flush=%x\n", &sc->sc_sysio->sys_iommu.iommu_cr, 340 &sc->sc_sysio->sys_iommu.iommu_tsb, &sc->sc_sysio->sys_iommu.iommu_flush); 341 cr = sc->sc_sysio->sys_iommu.iommu_cr; 342 tsb = sc->sc_sysio->sys_iommu.iommu_tsb; 343 printf("iommu cr=%x:%x tsb=%x:%x\n", (long)(cr>>32), (long)cr, (long)(tsb>>32), (long)tsb); 344 printf("sysio base %p phys %p TSB base %p phys %p", 345 (long)sc->sc_sysio, (long)pmap_extract(pmap_kernel(), (vm_offset_t)sc->sc_sysio), 346 (long)sc->sc_tsb, (long)sc->sc_ptsb); 347 delay(1000000); /* 1 s */ 348 } 349 #endif 350 351 /* 352 * Initialize streaming buffer. 353 */ 354 sc->sc_flushpa = pmap_extract(pmap_kernel(), &sc->sc_flush); 355 #if 0 356 sc->sc_sysio->sys_strbuf.strbuf_ctl = STRBUF_EN; /* Enable diagnostics mode? */ 357 #else 358 stxa(&sc->sc_sysio->sys_strbuf.strbuf_ctl,ASI_NUCLEUS,STRBUF_EN); 359 #endif 360 361 /* 362 * Loop through ROM children, fixing any relative addresses 363 * and then configuring each device. 364 * `specials' is an array of device names that are treated 365 * specially: 366 */ 367 node0 = firstchild(node); 368 for (node = node0; node; node = nextsibling(node)) { 369 char *name = getpropstring(node, "name"); 370 371 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 372 node, bp, &sa) != 0) { 373 printf("sbus_attach: %s: incomplete\n", name); 374 continue; 375 } 376 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 377 } 378 } 379 380 int 381 sbus_setup_attach_args(sc, bustag, dmatag, node, bp, sa) 382 struct sbus_softc *sc; 383 bus_space_tag_t bustag; 384 bus_dma_tag_t dmatag; 385 int node; 386 struct bootpath *bp; 387 struct sbus_attach_args *sa; 388 { 389 struct sbus_reg romreg; 390 int base; 391 int error; 392 393 bzero(sa, sizeof(struct sbus_attach_args)); 394 sa->sa_name = getpropstring(node, "name"); 395 sa->sa_bustag = bustag; 396 sa->sa_dmatag = dmatag; 397 sa->sa_node = node; 398 sa->sa_bp = bp; 399 400 if ((error = getprop_reg1(node, &romreg)) != 0) 401 return (error); 402 403 /* We pass only the first "reg" property */ 404 base = (int)romreg.rr_paddr; 405 if (SBUS_ABS(base)) { 406 sa->sa_slot = SBUS_ABS_TO_SLOT(base); 407 sa->sa_offset = SBUS_ABS_TO_OFFSET(base); 408 } else { 409 sa->sa_slot = romreg.rr_iospace; 410 sa->sa_offset = base; 411 } 412 sa->sa_size = romreg.rr_len; 413 414 if ((error = sbus_get_intr(sc, node, &sa->sa_pri)) != 0) 415 return (error); 416 417 if ((error = getprop_address1(node, &sa->sa_promvaddr)) != 0) 418 return (error); 419 420 return (0); 421 } 422 423 int 424 _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp) 425 bus_space_tag_t t; 426 bus_type_t btype; 427 bus_addr_t offset; 428 bus_size_t size; 429 int flags; 430 vm_offset_t vaddr; 431 bus_space_handle_t *hp; 432 { 433 struct sbus_softc *sc = t->cookie; 434 int64_t slot = btype; 435 int i; 436 437 for (i = 0; i < sc->sc_nrange; i++) { 438 bus_addr_t paddr; 439 440 if (sc->sc_range[i].cspace != slot) 441 continue; 442 443 /* We've found the connection to the parent bus */ 444 paddr = sc->sc_range[i].poffset + offset; 445 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 446 #ifdef DEBUG 447 if (sbusdebug & SDB_DVMA) 448 printf("\n_sbus_bus_map: mapping paddr slot %x offset %x:%x poffset %x paddr %x:%x\n", 449 (int)slot, (int)(offset>>32), (int)offset, (int)sc->sc_range[i].poffset, (int)(paddr>>32), (int)paddr); 450 #endif 451 return (bus_space_map2(sc->sc_bustag, 0, paddr, 452 size, flags, vaddr, hp)); 453 } 454 455 return (EINVAL); 456 } 457 458 int 459 sbus_bus_mmap(t, btype, paddr, flags, hp) 460 bus_space_tag_t t; 461 bus_type_t btype; 462 bus_addr_t paddr; 463 int flags; 464 bus_space_handle_t *hp; 465 { 466 bus_addr_t offset = paddr; 467 int slot = (paddr>>32); 468 struct sbus_softc *sc = t->cookie; 469 int i; 470 471 for (i = 0; i < sc->sc_nrange; i++) { 472 bus_addr_t paddr; 473 474 if (sc->sc_range[i].cspace != slot) 475 continue; 476 477 paddr = sc->sc_range[i].poffset + offset; 478 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 479 return (bus_space_mmap(sc->sc_bustag, 0, paddr, 480 flags, hp)); 481 } 482 483 return (-1); 484 } 485 486 487 /* 488 * Each attached device calls sbus_establish after it initializes 489 * its sbusdev portion. 490 */ 491 void 492 sbus_establish(sd, dev) 493 register struct sbusdev *sd; 494 register struct device *dev; 495 { 496 register struct sbus_softc *sc; 497 register struct device *curdev; 498 499 /* 500 * We have to look for the sbus by name, since it is not necessarily 501 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 502 * We don't just use the device structure of the above-attached 503 * sbus, since we might (in the future) support multiple sbus's. 504 */ 505 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 506 if (!curdev || !curdev->dv_xname) 507 panic("sbus_establish: can't find sbus parent for %s", 508 sd->sd_dev->dv_xname 509 ? sd->sd_dev->dv_xname 510 : "<unknown>" ); 511 512 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 513 break; 514 } 515 sc = (struct sbus_softc *) curdev; 516 517 sd->sd_dev = dev; 518 sd->sd_bchain = sc->sc_sbdev; 519 sc->sc_sbdev = sd; 520 } 521 522 /* 523 * Reset the given sbus. (???) 524 */ 525 void 526 sbusreset(sbus) 527 int sbus; 528 { 529 register struct sbusdev *sd; 530 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 531 struct device *dev; 532 533 printf("reset %s:", sc->sc_dev.dv_xname); 534 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 535 if (sd->sd_reset) { 536 dev = sd->sd_dev; 537 (*sd->sd_reset)(dev); 538 printf(" %s", dev->dv_xname); 539 } 540 } 541 #if 0 542 /* Reload iommu regs */ 543 sc->sc_sysio->sys_iommu.iommu_cr = (IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN); 544 sc->sc_sysio->sys_iommu.iommu_tsb = sc->sc_ptsb; 545 sc->sc_sysio->sys_strbuf.strbuf_ctl = STRBUF_EN; /* Enable diagnostics mode? */ 546 #else 547 /* Reload iommu regs */ 548 stxa(&sc->sc_sysio->sys_iommu.iommu_cr,ASI_NUCLEUS,(IOMMUCR_TSB1K|IOMMUCR_8KPG|IOMMUCR_EN)); 549 stxa(&sc->sc_sysio->sys_iommu.iommu_tsb,ASI_NUCLEUS,sc->sc_ptsb); 550 stxa(&sc->sc_sysio->sys_strbuf.strbuf_ctl,ASI_NUCLEUS,STRBUF_EN); 551 #endif 552 } 553 554 /* 555 * Here are the iommu control routines. 556 */ 557 void 558 sbus_enter(sc, va, pa, flags) 559 struct sbus_softc *sc; 560 vm_offset_t va; 561 int64_t pa; 562 int flags; 563 { 564 int64_t tte; 565 566 #ifdef DIAGNOSTIC 567 if (va < sc->sc_dvmabase) 568 panic("sbus_enter: va 0x%x not in DVMA space",va); 569 #endif 570 571 tte = MAKEIOTTE(pa, flags&BUS_DMA_WRITE, flags&BUS_DMA_CACHE, 572 !(flags&BUS_DMA_COHERENT)); 573 574 /* Is the streamcache flush really needed? */ 575 #if 0 576 sc->sc_sysio->sys_strbuf.strbuf_pgflush = va; 577 #else 578 stxa(&(sc->sc_sysio->sys_strbuf.strbuf_pgflush), ASI_NUCLEUS, va); 579 #endif 580 sbus_flush(sc); 581 sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)] = tte; 582 #if 0 583 sc->sc_sysio->sys_iommu.iommu_flush = va; 584 #else 585 stxa(&sc->sc_sysio->sys_iommu.iommu_flush,ASI_NUCLEUS,va); 586 #endif 587 #ifdef DEBUG 588 if (sbusdebug & SDB_DVMA) 589 printf("sbus_enter: va %x pa %x:%x TSB[%x]@%p=%x:%x\n", 590 va, (int)(pa>>32), (int)pa, IOTSBSLOT(va,sc->sc_tsbsize), 591 &sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)], 592 (int)(tte>>32), (int)tte); 593 #endif 594 } 595 596 /* 597 * sbus_clear: clears mappings created by sbus_enter 598 * 599 * Only demap from IOMMU if flag is set. 600 */ 601 void 602 sbus_remove(sc, va, len) 603 struct sbus_softc *sc; 604 vm_offset_t va; 605 int len; 606 { 607 608 #ifdef DIAGNOSTIC 609 if (va < sc->sc_dvmabase) 610 panic("sbus_remove: va 0x%x not in DVMA space", (int)va); 611 if ((int)(va + len) < (int)va) 612 panic("sbus_remove: va 0x%x + len 0x%x wraps", 613 (int) va, (int) len); 614 #endif 615 616 va = trunc_page(va); 617 while (len > 0) { 618 619 /* 620 * Streaming buffer flushes: 621 * 622 * 1 Tell strbuf to flush by storing va to strbuf_pgflush 623 * If we're not on a cache line boundary (64-bits): 624 * 2 Store 0 in flag 625 * 3 Store pointer to flag in flushsync 626 * 4 wait till flushsync becomes 0x1 627 * 628 * If it takes more than .5 sec, something went wrong. 629 */ 630 #if 0 631 sc->sc_sysio->sys_strbuf.strbuf_pgflush = va; 632 #else 633 stxa(&(sc->sc_sysio->sys_strbuf.strbuf_pgflush), ASI_NUCLEUS, va); 634 #endif 635 if (len <= NBPG) { 636 sbus_flush(sc); 637 } 638 #ifdef DEBUG 639 if (sbusdebug & SDB_DVMA) 640 printf("sbus_remove: flushed va %p TSB[%x]@%p=%x:%x\n", 641 (int)va, (int)IOTSBSLOT(va,sc->sc_tsbsize), 642 (int)&sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)], 643 (int)((sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)])>>32), 644 (int)(sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)])); 645 #endif 646 sc->sc_tsb[IOTSBSLOT(va,sc->sc_tsbsize)] = 0; 647 #if 0 648 sc->sc_sysio->sys_iommu.iommu_flush = va; 649 #else 650 stxa(&sc->sc_sysio->sys_iommu.iommu_flush, ASI_NUCLEUS, va); 651 #endif 652 len -= NBPG; 653 va += NBPG; 654 } 655 } 656 657 int 658 sbus_flush(sc) 659 struct sbus_softc *sc; 660 { 661 extern u_int64_t cpu_clockrate; 662 u_int64_t flushtimeout; 663 664 sc->sc_flush = 0; 665 /* 666 * KLUGE ALERT KLUGE ALERT 667 * 668 * In order not to bother with pmap_extract() to do the vtop 669 * translation, flushdone is a static variable that resides in 670 * the kernel's 4MB locked TTE. This means that this routine 671 * is NOT re-entrant. Since we're single-threaded and poll 672 * on this value, this is currently not a problem. 673 */ 674 #ifdef NOTDEF_DEBUG 675 if (sbusdebug & SDB_DVMA) 676 printf("sbus_remove: flush = %x at va = %x pa = %x:%x\n", 677 (int)sc->sc_flush, (int)&sc->sc_flush, 678 (int)(sc->sc_flushpa>>32), (int)sc->sc_flushpa); 679 #endif 680 #if 0 681 sc->sc_sysio->sys_strbuf.strbuf_flushsync = sc->sc_flushpa; 682 #else 683 stxa(&sc->sc_sysio->sys_strbuf.strbuf_flushsync, ASI_NUCLEUS, sc->sc_flushpa); 684 #endif 685 membar_sync(); 686 flushtimeout = tick() + cpu_clockrate/2; /* .5 sec after *now* */ 687 while( !sc->sc_flush && flushtimeout > tick()) membar_sync(); 688 #ifdef DIAGNOSTIC 689 if( !sc->sc_flush ) 690 printf("sbus_remove: flush timeout %x at %x:%x\n", (int)sc->sc_flush, 691 (int)(sc->sc_flushpa>>32), (int)sc->sc_flushpa); /* panic? */ 692 #endif 693 return (sc->sc_flush); 694 } 695 /* 696 * Get interrupt attributes for an Sbus device. 697 */ 698 int 699 sbus_get_intr(sc, node, ip) 700 struct sbus_softc *sc; 701 int node; 702 int *ip; 703 { 704 struct sbus_intr *rip; 705 int *ipl; 706 int n; 707 char buf[32]; 708 709 /* 710 * The `interrupts' property contains the Sbus interrupt level. 711 */ 712 ipl = NULL; 713 if (getpropA(node, "interrupts", sizeof(int), &n, (void **)&ipl) == 0) { 714 /* Now things get ugly. We need to take this value which is 715 * the interrupt vector number and encode the IPL into it 716 * somehow. Luckily, the interrupt vector has lots of free 717 * space and we can easily stuff the IPL in there for a while. 718 */ 719 getpropstringA(node, "device_type", buf); 720 for (n=0; intrmap[n].in_class; n++) { 721 if (strcmp(intrmap[n].in_class, buf) == 0) { 722 ipl[0] |= INTLEVENCODE(intrmap[n].in_lev); 723 break; 724 } 725 } 726 *ip = ipl[0]; 727 free(ipl, M_DEVBUF); 728 return (0); 729 } 730 731 /* We really don't support the following */ 732 /* printf("\nWARNING: sbus_get_intr() \"interrupts\" not found -- using \"intr\"\n"); */ 733 /* And some devices don't even have interrupts */ 734 /* 735 * Fall back on `intr' property. 736 */ 737 rip = NULL; 738 switch (getpropA(node, "intr", sizeof(*rip), &n, (void **)&rip)) { 739 case 0: 740 getpropstringA(node, "device_type", buf); 741 for (n=0; intrmap[n].in_class; n++) { 742 if (strcmp(intrmap[n].in_class, buf) == 0) { 743 rip[0].int_pri |= INTLEVENCODE(intrmap[n].in_lev); 744 break; 745 } 746 } 747 *ip = rip[0].int_pri; 748 free(rip, M_DEVBUF); 749 return (0); 750 case ENOENT: 751 *ip = 0; 752 return (0); 753 } 754 755 return (-1); 756 } 757 758 759 /* 760 * Install an interrupt handler for an Sbus device. 761 */ 762 void * 763 sbus_intr_establish(t, level, flags, handler, arg) 764 bus_space_tag_t t; 765 int level; 766 int flags; 767 int (*handler) __P((void *)); 768 void *arg; 769 { 770 struct sbus_softc *sc = t->cookie; 771 struct intrhand *ih; 772 int ipl; 773 774 ih = (struct intrhand *) 775 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 776 if (ih == NULL) 777 return (NULL); 778 779 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 780 ipl = level; 781 else if ((level & SBUS_INTR_COMPAT) != 0) 782 ipl = level & ~SBUS_INTR_COMPAT; 783 else { 784 /* Decode and remove IPL */ 785 ipl = INTLEV(level); 786 level = INTVEC(level); 787 #ifdef DEBUG 788 if (sbusdebug & SDB_INTR) { 789 printf("\nsbus: intr[%d]%x: %x\n", ipl, level, 790 intrlev[level]); 791 printf("Hunting for IRQ...\n"); 792 } 793 #endif 794 if ((level & INTMAP_OBIO) == 0) { 795 /* We're in an SBUS slot */ 796 /* Register the map and clear intr registers */ 797 #ifdef DEBUG 798 if (sbusdebug & SDB_INTR) { 799 int64_t *intrptr = &(&sc->sc_sysio->sbus_slot0_int)[INTSLOT(level)]; 800 int64_t intrmap = *intrptr; 801 802 printf("Found SBUS %x IRQ as %x:%x in slot %d\n", 803 level, (int)(intrmap>>32), (int)intrmap, 804 INTSLOT(level)); 805 } 806 #endif 807 ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[INTSLOT(level)]; 808 ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[INTVEC(level)]; 809 /* Enable the interrupt */ 810 level |= INTMAP_V; 811 stxa(ih->ih_map, ASI_NUCLEUS, level); 812 } else { 813 int64_t *intrptr = &sc->sc_sysio->scsi_int_map; 814 int64_t intrmap = 0; 815 int i; 816 817 /* Insert IGN */ 818 level |= sc->sc_ign; 819 for (i=0; 820 &intrptr[i] <= (int64_t *)&sc->sc_sysio->reserved_int_map && 821 INTVEC(intrmap=intrptr[i]) != INTVEC(level); 822 i++); 823 if (INTVEC(intrmap) == INTVEC(level)) { 824 #ifdef DEBUG 825 if (sbusdebug & SDB_INTR) 826 printf("Found OBIO %x IRQ as %x:%x in slot %d\n", 827 level, (int)(intrmap>>32), (int)intrmap, 828 i); 829 #endif 830 /* Register the map and clear intr registers */ 831 ih->ih_map = &intrptr[i]; 832 intrptr = (int64_t *)&sc->sc_sysio->scsi_clr_int; 833 ih->ih_clr = &intrptr[i]; 834 /* Enable the interrupt */ 835 intrmap |= INTMAP_V; 836 stxa(ih->ih_map, ASI_NUCLEUS, intrmap); 837 } else panic("IRQ not found!"); 838 } 839 } 840 #ifdef DEBUG 841 if (sbusdebug & SDB_INTR) { int i; for (i=0; i<140000000; i++); } 842 #endif 843 844 ih->ih_fun = handler; 845 ih->ih_arg = arg; 846 ih->ih_number = level; 847 ih->ih_pil = (1<<ipl); 848 if ((flags & BUS_INTR_ESTABLISH_FASTTRAP) != 0) 849 intr_fasttrap(ipl, (void (*)__P((void)))handler); 850 else 851 intr_establish(ipl, ih); 852 return (ih); 853 } 854 855 static bus_space_tag_t 856 sbus_alloc_bustag(sc) 857 struct sbus_softc *sc; 858 { 859 bus_space_tag_t sbt; 860 861 sbt = (bus_space_tag_t) 862 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 863 if (sbt == NULL) 864 return (NULL); 865 866 bzero(sbt, sizeof *sbt); 867 sbt->cookie = sc; 868 sbt->parent = sc->sc_bustag; 869 sbt->type = SBUS_BUS_SPACE; 870 sbt->sparc_bus_map = _sbus_bus_map; 871 sbt->sparc_bus_mmap = sbus_bus_mmap; 872 sbt->sparc_intr_establish = sbus_intr_establish; 873 return (sbt); 874 } 875 876 877 static bus_dma_tag_t 878 sbus_alloc_dmatag(sc) 879 struct sbus_softc *sc; 880 { 881 bus_dma_tag_t sdt, psdt = sc->sc_dmatag; 882 883 sdt = (bus_dma_tag_t) 884 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 885 if (sdt == NULL) 886 /* Panic? */ 887 return (psdt); 888 889 sdt->_cookie = sc; 890 sdt->_parent = psdt; 891 #define PCOPY(x) sdt->x = psdt->x 892 PCOPY(_dmamap_create); 893 PCOPY(_dmamap_destroy); 894 sdt->_dmamap_load = sbus_dmamap_load; 895 PCOPY(_dmamap_load_mbuf); 896 PCOPY(_dmamap_load_uio); 897 PCOPY(_dmamap_load_raw); 898 sdt->_dmamap_unload = sbus_dmamap_unload; 899 sdt->_dmamap_sync = sbus_dmamap_sync; 900 sdt->_dmamem_alloc = sbus_dmamem_alloc; 901 sdt->_dmamem_free = sbus_dmamem_free; 902 sdt->_dmamem_map = sbus_dmamem_map; 903 sdt->_dmamem_unmap = sbus_dmamem_unmap; 904 PCOPY(_dmamem_mmap); 905 #undef PCOPY 906 sc->sc_dmatag = sdt; 907 return (sdt); 908 } 909 910 int 911 sbus_dmamap_load(t, map, buf, buflen, p, flags) 912 bus_dma_tag_t t; 913 bus_dmamap_t map; 914 void *buf; 915 bus_size_t buflen; 916 struct proc *p; 917 int flags; 918 { 919 int err; 920 bus_size_t sgsize; 921 vm_offset_t curaddr; 922 vm_offset_t dvmaddr, vaddr = (vm_offset_t)buf; 923 pmap_t pmap; 924 struct sbus_softc *sc = (struct sbus_softc *)t->_cookie; 925 926 if (map->dm_nsegs) { 927 /* Already in use?? */ 928 #ifdef DIAGNOSTIC 929 printf("sbus_dmamap_load: map still in use\n"); 930 #endif 931 bus_dmamap_unload(t, map); 932 } 933 if ((err = bus_dmamap_load(t->_parent, map, buf, buflen, p, flags))) 934 return (err); 935 936 if (p != NULL) 937 pmap = p->p_vmspace->vm_map.pmap; 938 else 939 pmap = pmap_kernel(); 940 941 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 942 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 943 for (; buflen > 0; ) { 944 /* 945 * Get the physical address for this page. 946 */ 947 if ((curaddr = (bus_addr_t)pmap_extract(pmap, (vm_offset_t)vaddr)) == NULL) { 948 bus_dmamap_unload(t, map); 949 return (-1); 950 } 951 952 /* 953 * Compute the segment size, and adjust counts. 954 */ 955 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 956 if (buflen < sgsize) 957 sgsize = buflen; 958 959 #ifdef DEBUG 960 if (sbusdebug & SDB_DVMA) 961 printf("sbus_dmamap_load: map %p loading va %x at pa %x\n", 962 map, (int)dvmaddr, (int)(curaddr & ~(NBPG-1))); 963 #endif 964 sbus_enter(sc, trunc_page(dvmaddr), trunc_page(curaddr), flags); 965 966 dvmaddr += PAGE_SIZE; 967 vaddr += sgsize; 968 buflen -= sgsize; 969 } 970 return (0); 971 } 972 973 void 974 sbus_dmamap_unload(t, map) 975 bus_dma_tag_t t; 976 bus_dmamap_t map; 977 { 978 vm_offset_t addr; 979 int len; 980 struct sbus_softc *sc = (struct sbus_softc *)t->_cookie; 981 982 if (map->dm_nsegs != 1) 983 panic("_sbus_dmamap_unload: nsegs = %d", map->dm_nsegs); 984 985 addr = trunc_page(map->dm_segs[0].ds_addr); 986 len = map->dm_segs[0].ds_len; 987 988 #ifdef DEBUG 989 if (sbusdebug & SDB_DVMA) 990 printf("sbus_dmamap_unload: map %p removing va %x size %x\n", 991 map, (int)addr, (int)len); 992 #endif 993 sbus_remove(sc, addr, len); 994 bus_dmamap_unload(t->_parent, map); 995 } 996 997 998 void 999 sbus_dmamap_sync(t, map, offset, len, ops) 1000 bus_dma_tag_t t; 1001 bus_dmamap_t map; 1002 bus_addr_t offset; 1003 bus_size_t len; 1004 int ops; 1005 { 1006 struct sbus_softc *sc = (struct sbus_softc *)t->_cookie; 1007 vm_offset_t va = map->dm_segs[0].ds_addr + offset; 1008 1009 1010 /* 1011 * We only support one DMA segment; supporting more makes this code 1012 * too unweildy. 1013 */ 1014 1015 if (ops&BUS_DMASYNC_PREREAD) 1016 /* Nothing to do */; 1017 if (ops&BUS_DMASYNC_POSTREAD) { 1018 /* 1019 * We should sync the IOMMU streaming caches here first. 1020 */ 1021 while (len > 0) { 1022 1023 /* 1024 * Streaming buffer flushes: 1025 * 1026 * 1 Tell strbuf to flush by storing va to strbuf_pgflush 1027 * If we're not on a cache line boundary (64-bits): 1028 * 2 Store 0 in flag 1029 * 3 Store pointer to flag in flushsync 1030 * 4 wait till flushsync becomes 0x1 1031 * 1032 * If it takes more than .5 sec, something went wrong. 1033 */ 1034 #if 0 1035 sc->sc_sysio->sys_strbuf.strbuf_pgflush = va; 1036 #else 1037 stxa(&(sc->sc_sysio->sys_strbuf.strbuf_pgflush), ASI_NUCLEUS, va); 1038 #endif 1039 if (len <= NBPG) { 1040 sbus_flush(sc); 1041 } 1042 len -= NBPG; 1043 va += NBPG; 1044 } 1045 } 1046 if (ops&BUS_DMASYNC_PREWRITE) 1047 /* Nothing to do */; 1048 if (ops&BUS_DMASYNC_POSTWRITE) 1049 /* Nothing to do */; 1050 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1051 } 1052 1053 int 1054 sbus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 1055 bus_dma_tag_t t; 1056 bus_size_t size, alignment, boundary; 1057 bus_dma_segment_t *segs; 1058 int nsegs; 1059 int *rsegs; 1060 int flags; 1061 { 1062 vm_offset_t curaddr; 1063 bus_addr_t dvmaddr; 1064 vm_page_t m; 1065 struct pglist *mlist; 1066 int error; 1067 int n; 1068 struct sbus_softc *sc = (struct sbus_softc *)t->_cookie; 1069 1070 if ((error = bus_dmamem_alloc(t->_parent, size, alignment, 1071 boundary, segs, nsegs, rsegs, flags))) 1072 return (error); 1073 1074 for (n=0; n<*rsegs; n++) { 1075 dvmaddr = segs[n].ds_addr; 1076 size = segs[n].ds_len; 1077 mlist = segs[n]._ds_mlist; 1078 1079 /* Map memory into DVMA space */ 1080 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 1081 curaddr = VM_PAGE_TO_PHYS(m); 1082 sbus_enter(sc, dvmaddr, curaddr, flags); 1083 dvmaddr += PAGE_SIZE; 1084 } 1085 } 1086 return (0); 1087 } 1088 1089 void 1090 sbus_dmamem_free(t, segs, nsegs) 1091 bus_dma_tag_t t; 1092 bus_dma_segment_t *segs; 1093 int nsegs; 1094 { 1095 vm_offset_t addr; 1096 int len; 1097 int n; 1098 struct sbus_softc *sc = (struct sbus_softc *)t->_cookie; 1099 1100 1101 for (n=0; n<nsegs; n++) { 1102 addr = segs[n].ds_addr; 1103 len = segs[n].ds_len; 1104 sbus_remove(sc, addr, len); 1105 } 1106 bus_dmamem_free(t->_parent, segs, nsegs); 1107 } 1108 1109 /* 1110 * Call bus_dmamem_map() to map it into the kernel, then map it into the IOTSB. 1111 * Check the flags to see whether we're streaming or coherent. 1112 */ 1113 int 1114 sbus_dmamem_map(t, segs, nsegs, size, kvap, flags) 1115 bus_dma_tag_t t; 1116 bus_dma_segment_t *segs; 1117 int nsegs; 1118 size_t size; 1119 caddr_t *kvap; 1120 int flags; 1121 { 1122 vm_page_t m; 1123 vm_offset_t va; 1124 bus_addr_t addr; 1125 struct pglist *mlist; 1126 struct sbus_softc *sc = (struct sbus_softc *)t->_cookie; 1127 int r, cbit; 1128 int rval; 1129 1130 /* 1131 * First have the parent driver allocate some address space in DVMA space. 1132 */ 1133 if (rval = bus_dmamem_map(t->_parent, segs, nsegs, size, kvap, flags)) 1134 return (rval); 1135 1136 /* 1137 * digest flags: 1138 */ 1139 cbit = 0; 1140 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 1141 cbit |= PMAP_NVC; 1142 if (flags & BUS_DMA_CACHE) /* sideffects */ 1143 cbit |= PMAP_NC; 1144 /* 1145 * Now take this and map it both into the CPU and into the IOMMU. 1146 */ 1147 va = (vm_offset_t)*kvap; 1148 mlist = segs[0]._ds_mlist; 1149 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 1150 1151 if (size == 0) 1152 panic("_bus_dmamem_map: size botch"); 1153 1154 addr = VM_PAGE_TO_PHYS(m); 1155 pmap_enter(pmap_kernel(), va, addr | cbit, 1156 VM_PROT_READ | VM_PROT_WRITE, TRUE); 1157 sbus_enter(sc, va, addr, flags); 1158 va += PAGE_SIZE; 1159 size -= PAGE_SIZE; 1160 } 1161 1162 return (0); 1163 } 1164 1165 /* 1166 * Common function for unmapping DMA-safe memory. May be called by 1167 * bus-specific DMA memory unmapping functions. 1168 */ 1169 void 1170 sbus_dmamem_unmap(t, kva, size) 1171 bus_dma_tag_t t; 1172 caddr_t kva; 1173 size_t size; 1174 { 1175 struct sbus_softc *sc = (struct sbus_softc *)t->_cookie; 1176 1177 #ifdef DIAGNOSTIC 1178 if ((u_long)kva & PGOFSET) 1179 panic("_bus_dmamem_unmap"); 1180 #endif 1181 1182 size = round_page(size); 1183 sbus_remove(sc, kva, size); 1184 bus_dmamem_unmap(t->_parent, kva, size); 1185 } 1186
Indexes created Thu Oct 02 14:10:14 GMT 2025