sbus.c revision 1.28
1 /* $NetBSD: sbus.c,v 1.28 2000/04/22 17:06:05 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Copyright (c) 1999 Eduardo Horvath 85 * 86 * Redistribution and use in source and binary forms, with or without 87 * modification, are permitted provided that the following conditions 88 * are met: 89 * 1. Redistributions of source code must retain the above copyright 90 * notice, this list of conditions and the following disclaimer. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 */ 105 106 107 /* 108 * Sbus stuff. 109 */ 110 #include "opt_ddb.h" 111 112 #include <sys/param.h> 113 #include <sys/extent.h> 114 #include <sys/malloc.h> 115 #include <sys/systm.h> 116 #include <sys/device.h> 117 #include <vm/vm.h> 118 119 #include <machine/bus.h> 120 #include <sparc64/sparc64/vaddrs.h> 121 #include <sparc64/sparc64/cache.h> 122 #include <sparc64/dev/iommureg.h> 123 #include <sparc64/dev/iommuvar.h> 124 #include <sparc64/dev/sbusreg.h> 125 #include <dev/sbus/sbusvar.h> 126 127 #include <machine/autoconf.h> 128 #include <machine/ctlreg.h> 129 #include <machine/cpu.h> 130 #include <machine/sparc64.h> 131 132 #ifdef DEBUG 133 #define SDB_DVMA 0x1 134 #define SDB_INTR 0x2 135 int sbus_debug = 0; 136 #define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 137 #else 138 #define DPRINTF(l, s) 139 #endif 140 141 void sbusreset __P((int)); 142 143 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 144 static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *)); 145 static int sbus_get_intr __P((struct sbus_softc *, int, 146 struct sbus_intr **, int *, int)); 147 static int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 148 int, bus_space_handle_t *)); 149 static int _sbus_bus_map __P(( 150 bus_space_tag_t, 151 bus_type_t, 152 bus_addr_t, /*offset*/ 153 bus_size_t, /*size*/ 154 int, /*flags*/ 155 vaddr_t, /*preferred virtual address */ 156 bus_space_handle_t *)); 157 static void *sbus_intr_establish __P(( 158 bus_space_tag_t, 159 int, /*level*/ 160 int, /*flags*/ 161 int (*) __P((void *)), /*handler*/ 162 void *)); /*handler arg*/ 163 164 165 /* autoconfiguration driver */ 166 int sbus_match __P((struct device *, struct cfdata *, void *)); 167 void sbus_attach __P((struct device *, struct device *, void *)); 168 169 170 struct cfattach sbus_ca = { 171 sizeof(struct sbus_softc), sbus_match, sbus_attach 172 }; 173 174 extern struct cfdriver sbus_cd; 175 176 /* 177 * DVMA routines 178 */ 179 int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 180 bus_size_t, struct proc *, int)); 181 void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 182 void sbus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 183 bus_size_t, int)); 184 int sbus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 185 bus_size_t alignment, bus_size_t boundary, 186 bus_dma_segment_t *segs, int nsegs, int *rsegs, 187 int flags)); 188 void sbus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 189 int nsegs)); 190 int sbus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 191 int nsegs, size_t size, caddr_t *kvap, int flags)); 192 void sbus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 193 size_t size)); 194 195 /* 196 * Child devices receive the Sbus interrupt level in their attach 197 * arguments. We translate these to CPU IPLs using the following 198 * tables. Note: obio bus interrupt levels are identical to the 199 * processor IPL. 200 * 201 * The second set of tables is used when the Sbus interrupt level 202 * cannot be had from the PROM as an `interrupt' property. We then 203 * fall back on the `intr' property which contains the CPU IPL. 204 */ 205 206 /* Translate Sbus interrupt level to processor IPL */ 207 static int intr_sbus2ipl_4c[] = { 208 0, 1, 2, 3, 5, 7, 8, 9 209 }; 210 static int intr_sbus2ipl_4m[] = { 211 0, 2, 3, 5, 7, 9, 11, 13 212 }; 213 214 /* 215 * This value is or'ed into the attach args' interrupt level cookie 216 * if the interrupt level comes from an `intr' property, i.e. it is 217 * not an Sbus interrupt level. 218 */ 219 #define SBUS_INTR_COMPAT 0x80000000 220 221 222 /* 223 * Print the location of some sbus-attached device (called just 224 * before attaching that device). If `sbus' is not NULL, the 225 * device was found but not configured; print the sbus as well. 226 * Return UNCONF (config_find ignores this if the device was configured). 227 */ 228 int 229 sbus_print(args, busname) 230 void *args; 231 const char *busname; 232 { 233 struct sbus_attach_args *sa = args; 234 int i; 235 236 if (busname) 237 printf("%s at %s", sa->sa_name, busname); 238 printf(" slot %ld offset 0x%lx", (long)sa->sa_slot, 239 (u_long)sa->sa_offset); 240 for (i = 0; i < sa->sa_nintr; i++) { 241 struct sbus_intr *sbi = &sa->sa_intr[i]; 242 243 printf(" vector %lx ipl %ld", 244 (u_long)sbi->sbi_vec, 245 (long)INTLEV(sbi->sbi_pri)); 246 } 247 return (UNCONF); 248 } 249 250 int 251 sbus_match(parent, cf, aux) 252 struct device *parent; 253 struct cfdata *cf; 254 void *aux; 255 { 256 struct mainbus_attach_args *ma = aux; 257 258 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 259 } 260 261 /* 262 * Attach an Sbus. 263 */ 264 void 265 sbus_attach(parent, self, aux) 266 struct device *parent; 267 struct device *self; 268 void *aux; 269 { 270 struct sbus_softc *sc = (struct sbus_softc *)self; 271 struct mainbus_attach_args *ma = aux; 272 char *name; 273 int node = ma->ma_node; 274 275 int node0, error; 276 bus_space_tag_t sbt; 277 struct sbus_attach_args sa; 278 279 sc->sc_bustag = ma->ma_bustag; 280 sc->sc_dmatag = ma->ma_dmatag; 281 sc->sc_sysio = (struct sysioreg*)(u_long)ma->ma_address[0]; /* Use prom mapping for sysio. */ 282 sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */ 283 284 /* Setup interrupt translation tables */ 285 sc->sc_intr2ipl = CPU_ISSUN4C 286 ? intr_sbus2ipl_4c 287 : intr_sbus2ipl_4m; 288 289 /* 290 * Record clock frequency for synchronous SCSI. 291 * IS THIS THE CORRECT DEFAULT?? 292 */ 293 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 294 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 295 296 sbt = sbus_alloc_bustag(sc); 297 sc->sc_dmatag = sbus_alloc_dmatag(sc); 298 299 /* 300 * Get the SBus burst transfer size if burst transfers are supported 301 */ 302 sc->sc_burst = getpropint(node, "burst-sizes", 0); 303 304 /* 305 * Collect address translations from the OBP. 306 */ 307 error = getprop(node, "ranges", sizeof(struct sbus_range), 308 &sc->sc_nrange, (void **)&sc->sc_range); 309 if (error) 310 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 311 312 /* initailise the IOMMU */ 313 314 /* punch in our copies */ 315 sc->sc_is.is_bustag = sc->sc_bustag; 316 sc->sc_is.is_iommu = &sc->sc_sysio->sys_iommu; 317 sc->sc_is.is_sb = &sc->sc_sysio->sys_strbuf; 318 319 /* give us a nice name.. */ 320 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 321 if (name == 0) 322 panic("couldn't malloc iommu name"); 323 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 324 325 iommu_init(name, &sc->sc_is, 0); 326 327 /* 328 * Loop through ROM children, fixing any relative addresses 329 * and then configuring each device. 330 * `specials' is an array of device names that are treated 331 * specially: 332 */ 333 node0 = firstchild(node); 334 for (node = node0; node; node = nextsibling(node)) { 335 char *name = getpropstring(node, "name"); 336 337 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 338 node, &sa) != 0) { 339 printf("sbus_attach: %s: incomplete\n", name); 340 continue; 341 } 342 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 343 sbus_destroy_attach_args(&sa); 344 } 345 } 346 347 int 348 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 349 struct sbus_softc *sc; 350 bus_space_tag_t bustag; 351 bus_dma_tag_t dmatag; 352 int node; 353 struct sbus_attach_args *sa; 354 { 355 /*struct sbus_reg sbusreg;*/ 356 /*int base;*/ 357 int error; 358 int n; 359 360 bzero(sa, sizeof(struct sbus_attach_args)); 361 error = getprop(node, "name", 1, &n, (void **)&sa->sa_name); 362 if (error != 0) 363 return (error); 364 sa->sa_name[n] = '\0'; 365 366 sa->sa_bustag = bustag; 367 sa->sa_dmatag = dmatag; 368 sa->sa_node = node; 369 370 error = getprop(node, "reg", sizeof(struct sbus_reg), 371 &sa->sa_nreg, (void **)&sa->sa_reg); 372 if (error != 0) { 373 char buf[32]; 374 if (error != ENOENT || 375 !node_has_property(node, "device_type") || 376 strcmp(getpropstringA(node, "device_type", buf), 377 "hierarchical") != 0) 378 return (error); 379 } 380 for (n = 0; n < sa->sa_nreg; n++) { 381 /* Convert to relative addressing, if necessary */ 382 u_int32_t base = sa->sa_reg[n].sbr_offset; 383 if (SBUS_ABS(base)) { 384 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 385 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 386 } 387 } 388 389 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr, 390 sa->sa_slot)) != 0) 391 return (error); 392 393 error = getprop(node, "address", sizeof(u_int32_t), 394 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 395 if (error != 0 && error != ENOENT) 396 return (error); 397 398 return (0); 399 } 400 401 void 402 sbus_destroy_attach_args(sa) 403 struct sbus_attach_args *sa; 404 { 405 if (sa->sa_name != NULL) 406 free(sa->sa_name, M_DEVBUF); 407 408 if (sa->sa_nreg != 0) 409 free(sa->sa_reg, M_DEVBUF); 410 411 if (sa->sa_intr) 412 free(sa->sa_intr, M_DEVBUF); 413 414 if (sa->sa_promvaddrs) 415 free((void *)sa->sa_promvaddrs, M_DEVBUF); 416 417 bzero(sa, sizeof(struct sbus_attach_args)); /*DEBUG*/ 418 } 419 420 421 int 422 _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp) 423 bus_space_tag_t t; 424 bus_type_t btype; 425 bus_addr_t offset; 426 bus_size_t size; 427 int flags; 428 vaddr_t vaddr; 429 bus_space_handle_t *hp; 430 { 431 struct sbus_softc *sc = t->cookie; 432 int64_t slot = btype; 433 int i; 434 435 for (i = 0; i < sc->sc_nrange; i++) { 436 bus_addr_t paddr; 437 438 if (sc->sc_range[i].cspace != slot) 439 continue; 440 441 /* We've found the connection to the parent bus */ 442 paddr = sc->sc_range[i].poffset + offset; 443 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 444 DPRINTF(SDB_DVMA, 445 ("\n_sbus_bus_map: mapping paddr slot %lx offset %lx poffset %lx paddr %lx\n", 446 (long)slot, (long)offset, (long)sc->sc_range[i].poffset, 447 (long)paddr)); 448 return (bus_space_map2(sc->sc_bustag, 0, paddr, 449 size, flags, vaddr, hp)); 450 } 451 452 return (EINVAL); 453 } 454 455 int 456 sbus_bus_mmap(t, btype, paddr, flags, hp) 457 bus_space_tag_t t; 458 bus_type_t btype; 459 bus_addr_t paddr; 460 int flags; 461 bus_space_handle_t *hp; 462 { 463 bus_addr_t offset = paddr; 464 int slot = (paddr>>32); 465 struct sbus_softc *sc = t->cookie; 466 int i; 467 468 for (i = 0; i < sc->sc_nrange; i++) { 469 bus_addr_t paddr; 470 471 if (sc->sc_range[i].cspace != slot) 472 continue; 473 474 paddr = sc->sc_range[i].poffset + offset; 475 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 476 return (bus_space_mmap(sc->sc_bustag, 0, paddr, 477 flags, hp)); 478 } 479 480 return (-1); 481 } 482 483 484 /* 485 * Each attached device calls sbus_establish after it initializes 486 * its sbusdev portion. 487 */ 488 void 489 sbus_establish(sd, dev) 490 register struct sbusdev *sd; 491 register struct device *dev; 492 { 493 register struct sbus_softc *sc; 494 register struct device *curdev; 495 496 /* 497 * We have to look for the sbus by name, since it is not necessarily 498 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 499 * We don't just use the device structure of the above-attached 500 * sbus, since we might (in the future) support multiple sbus's. 501 */ 502 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 503 if (!curdev || !curdev->dv_xname) 504 panic("sbus_establish: can't find sbus parent for %s", 505 sd->sd_dev->dv_xname 506 ? sd->sd_dev->dv_xname 507 : "<unknown>" ); 508 509 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 510 break; 511 } 512 sc = (struct sbus_softc *) curdev; 513 514 sd->sd_dev = dev; 515 sd->sd_bchain = sc->sc_sbdev; 516 sc->sc_sbdev = sd; 517 } 518 519 /* 520 * Reset the given sbus. (???) 521 */ 522 void 523 sbusreset(sbus) 524 int sbus; 525 { 526 register struct sbusdev *sd; 527 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 528 struct device *dev; 529 530 printf("reset %s:", sc->sc_dev.dv_xname); 531 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 532 if (sd->sd_reset) { 533 dev = sd->sd_dev; 534 (*sd->sd_reset)(dev); 535 printf(" %s", dev->dv_xname); 536 } 537 } 538 /* Reload iommu regs */ 539 iommu_reset(&sc->sc_is); 540 } 541 542 /* 543 * Get interrupt attributes for an Sbus device. 544 */ 545 int 546 sbus_get_intr(sc, node, ipp, np, slot) 547 struct sbus_softc *sc; 548 int node; 549 struct sbus_intr **ipp; 550 int *np; 551 int slot; 552 { 553 int *ipl; 554 int n, i; 555 char buf[32]; 556 557 /* 558 * The `interrupts' property contains the Sbus interrupt level. 559 */ 560 ipl = NULL; 561 if (getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 562 struct sbus_intr *ip; 563 int pri; 564 565 /* Default to interrupt level 2 -- otherwise unused */ 566 pri = INTLEVENCODE(2); 567 568 /* Change format to an `struct sbus_intr' array */ 569 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 570 if (ip == NULL) 571 return (ENOMEM); 572 573 /* 574 * Now things get ugly. We need to take this value which is 575 * the interrupt vector number and encode the IPL into it 576 * somehow. Luckily, the interrupt vector has lots of free 577 * space and we can easily stuff the IPL in there for a while. 578 */ 579 getpropstringA(node, "device_type", buf); 580 if (!buf[0]) 581 getpropstringA(node, "name", buf); 582 583 for (i = 0; intrmap[i].in_class; i++) 584 if (strcmp(intrmap[i].in_class, buf) == 0) { 585 pri = INTLEVENCODE(intrmap[i].in_lev); 586 break; 587 } 588 589 /* 590 * Sbus card devices need the slot number encoded into 591 * the vector as this is generally not done. 592 */ 593 if ((ipl[0] & INTMAP_OBIO) == 0) 594 pri |= slot << 3; 595 596 for (n = 0; n < *np; n++) { 597 /* 598 * We encode vector and priority into sbi_pri so we 599 * can pass them as a unit. This will go away if 600 * sbus_establish ever takes an sbus_intr instead 601 * of an integer level. 602 * Stuff the real vector in sbi_vec. 603 */ 604 605 ip[n].sbi_pri = pri|ipl[n]; 606 ip[n].sbi_vec = ipl[n]; 607 } 608 free(ipl, M_DEVBUF); 609 *ipp = ip; 610 } 611 612 return (0); 613 } 614 615 616 /* 617 * Install an interrupt handler for an Sbus device. 618 */ 619 void * 620 sbus_intr_establish(t, level, flags, handler, arg) 621 bus_space_tag_t t; 622 int level; 623 int flags; 624 int (*handler) __P((void *)); 625 void *arg; 626 { 627 struct sbus_softc *sc = t->cookie; 628 struct intrhand *ih; 629 int ipl; 630 long vec = level; 631 632 ih = (struct intrhand *) 633 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 634 if (ih == NULL) 635 return (NULL); 636 637 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 638 ipl = vec; 639 else if ((vec & SBUS_INTR_COMPAT) != 0) 640 ipl = vec & ~SBUS_INTR_COMPAT; 641 else { 642 /* Decode and remove IPL */ 643 ipl = INTLEV(vec); 644 vec = INTVEC(vec); 645 DPRINTF(SDB_INTR, 646 ("\nsbus: intr[%ld]%lx: %lx\nHunting for IRQ...\n", 647 (long)ipl, (long)vec, intrlev[vec])); 648 if ((vec & INTMAP_OBIO) == 0) { 649 /* We're in an SBUS slot */ 650 /* Register the map and clear intr registers */ 651 652 int slot = INTSLOT(level); 653 654 ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[slot]; 655 ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[vec]; 656 #ifdef DEBUG 657 if (sbus_debug & SDB_INTR) { 658 int64_t intrmap = *ih->ih_map; 659 660 printf("Found SBUS %lx IRQ as %llx in slot %d\n", 661 (long)vec, (long long)intrmap, slot); 662 printf("\tmap addr %p clr addr %p\n", ih->ih_map, ih->ih_clr); 663 } 664 #endif 665 /* Enable the interrupt */ 666 vec |= INTMAP_V; 667 /* Insert IGN */ 668 vec |= sc->sc_ign; 669 bus_space_write_8(sc->sc_bustag, ih->ih_map, 0, vec); 670 } else { 671 int64_t *intrptr = &sc->sc_sysio->scsi_int_map; 672 int64_t intrmap = 0; 673 int i; 674 675 /* Insert IGN */ 676 vec |= sc->sc_ign; 677 for (i = 0; &intrptr[i] <= 678 (int64_t *)&sc->sc_sysio->reserved_int_map && 679 INTVEC(intrmap = intrptr[i]) != INTVEC(vec); i++) 680 ; 681 if (INTVEC(intrmap) == INTVEC(vec)) { 682 DPRINTF(SDB_INTR, 683 ("Found OBIO %lx IRQ as %lx in slot %d\n", 684 vec, (long)intrmap, i)); 685 /* Register the map and clear intr registers */ 686 ih->ih_map = &intrptr[i]; 687 intrptr = (int64_t *)&sc->sc_sysio->scsi_clr_int; 688 ih->ih_clr = &intrptr[i]; 689 /* Enable the interrupt */ 690 intrmap |= INTMAP_V; 691 bus_space_write_8(sc->sc_bustag, ih->ih_map, 0, (u_long)intrmap); 692 } else 693 panic("IRQ not found!"); 694 } 695 } 696 #ifdef DEBUG 697 if (sbus_debug & SDB_INTR) { long i; for (i = 0; i < 400000000; i++); } 698 #endif 699 700 ih->ih_fun = handler; 701 ih->ih_arg = arg; 702 ih->ih_number = vec; 703 ih->ih_pil = (1<<ipl); 704 intr_establish(ipl, ih); 705 return (ih); 706 } 707 708 static bus_space_tag_t 709 sbus_alloc_bustag(sc) 710 struct sbus_softc *sc; 711 { 712 bus_space_tag_t sbt; 713 714 sbt = (bus_space_tag_t) 715 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 716 if (sbt == NULL) 717 return (NULL); 718 719 bzero(sbt, sizeof *sbt); 720 sbt->cookie = sc; 721 sbt->parent = sc->sc_bustag; 722 sbt->type = SBUS_BUS_SPACE; 723 sbt->sparc_bus_map = _sbus_bus_map; 724 sbt->sparc_bus_mmap = sbus_bus_mmap; 725 sbt->sparc_intr_establish = sbus_intr_establish; 726 return (sbt); 727 } 728 729 730 static bus_dma_tag_t 731 sbus_alloc_dmatag(sc) 732 struct sbus_softc *sc; 733 { 734 bus_dma_tag_t sdt, psdt = sc->sc_dmatag; 735 736 sdt = (bus_dma_tag_t) 737 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 738 if (sdt == NULL) 739 /* Panic? */ 740 return (psdt); 741 742 sdt->_cookie = sc; 743 sdt->_parent = psdt; 744 #define PCOPY(x) sdt->x = psdt->x 745 PCOPY(_dmamap_create); 746 PCOPY(_dmamap_destroy); 747 sdt->_dmamap_load = sbus_dmamap_load; 748 PCOPY(_dmamap_load_mbuf); 749 PCOPY(_dmamap_load_uio); 750 PCOPY(_dmamap_load_raw); 751 sdt->_dmamap_unload = sbus_dmamap_unload; 752 sdt->_dmamap_sync = sbus_dmamap_sync; 753 sdt->_dmamem_alloc = sbus_dmamem_alloc; 754 sdt->_dmamem_free = sbus_dmamem_free; 755 sdt->_dmamem_map = sbus_dmamem_map; 756 sdt->_dmamem_unmap = sbus_dmamem_unmap; 757 PCOPY(_dmamem_mmap); 758 #undef PCOPY 759 sc->sc_dmatag = sdt; 760 return (sdt); 761 } 762 763 int 764 sbus_dmamap_load(tag, map, buf, buflen, p, flags) 765 bus_dma_tag_t tag; 766 bus_dmamap_t map; 767 void *buf; 768 bus_size_t buflen; 769 struct proc *p; 770 int flags; 771 { 772 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 773 774 return (iommu_dvmamap_load(tag, &sc->sc_is, map, buf, buflen, p, flags)); 775 } 776 777 void 778 sbus_dmamap_unload(tag, map) 779 bus_dma_tag_t tag; 780 bus_dmamap_t map; 781 { 782 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 783 784 iommu_dvmamap_unload(tag, &sc->sc_is, map); 785 } 786 787 void 788 sbus_dmamap_sync(tag, map, offset, len, ops) 789 bus_dma_tag_t tag; 790 bus_dmamap_t map; 791 bus_addr_t offset; 792 bus_size_t len; 793 int ops; 794 { 795 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 796 797 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 798 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 799 } 800 801 int 802 sbus_dmamem_alloc(tag, size, alignment, boundary, segs, nsegs, rsegs, flags) 803 bus_dma_tag_t tag; 804 bus_size_t size; 805 bus_size_t alignment; 806 bus_size_t boundary; 807 bus_dma_segment_t *segs; 808 int nsegs; 809 int *rsegs; 810 int flags; 811 { 812 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 813 814 return (iommu_dvmamem_alloc(tag, &sc->sc_is, size, alignment, boundary, 815 segs, nsegs, rsegs, flags)); 816 } 817 818 void 819 sbus_dmamem_free(tag, segs, nsegs) 820 bus_dma_tag_t tag; 821 bus_dma_segment_t *segs; 822 int nsegs; 823 { 824 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 825 826 iommu_dvmamem_free(tag, &sc->sc_is, segs, nsegs); 827 } 828 829 int 830 sbus_dmamem_map(tag, segs, nsegs, size, kvap, flags) 831 bus_dma_tag_t tag; 832 bus_dma_segment_t *segs; 833 int nsegs; 834 size_t size; 835 caddr_t *kvap; 836 int flags; 837 { 838 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 839 840 return (iommu_dvmamem_map(tag, &sc->sc_is, segs, nsegs, size, kvap, flags)); 841 } 842 843 void 844 sbus_dmamem_unmap(tag, kva, size) 845 bus_dma_tag_t tag; 846 caddr_t kva; 847 size_t size; 848 { 849 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 850 851 iommu_dvmamem_unmap(tag, &sc->sc_is, kva, size); 852 } 853
Indexes created Thu Oct 02 14:10:14 GMT 2025