sbus.c revision 1.33
1 /* $NetBSD: sbus.c,v 1.33 2000/06/29 07:37:55 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Copyright (c) 1999 Eduardo Horvath 85 * 86 * Redistribution and use in source and binary forms, with or without 87 * modification, are permitted provided that the following conditions 88 * are met: 89 * 1. Redistributions of source code must retain the above copyright 90 * notice, this list of conditions and the following disclaimer. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 */ 105 106 107 /* 108 * Sbus stuff. 109 */ 110 #include "opt_ddb.h" 111 112 #include <sys/param.h> 113 #include <sys/extent.h> 114 #include <sys/malloc.h> 115 #include <sys/systm.h> 116 #include <sys/device.h> 117 118 #include <machine/bus.h> 119 #include <sparc64/sparc64/cache.h> 120 #include <sparc64/dev/iommureg.h> 121 #include <sparc64/dev/iommuvar.h> 122 #include <sparc64/dev/sbusreg.h> 123 #include <dev/sbus/sbusvar.h> 124 125 #include <machine/autoconf.h> 126 #include <machine/cpu.h> 127 #include <machine/sparc64.h> 128 129 #ifdef DEBUG 130 #define SDB_DVMA 0x1 131 #define SDB_INTR 0x2 132 int sbus_debug = 0; 133 #define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 134 #else 135 #define DPRINTF(l, s) 136 #endif 137 138 void sbusreset __P((int)); 139 140 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 141 static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *)); 142 static int sbus_get_intr __P((struct sbus_softc *, int, 143 struct sbus_intr **, int *, int)); 144 static int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 145 int, bus_space_handle_t *)); 146 static int _sbus_bus_map __P(( 147 bus_space_tag_t, 148 bus_type_t, 149 bus_addr_t, /*offset*/ 150 bus_size_t, /*size*/ 151 int, /*flags*/ 152 vaddr_t, /*preferred virtual address */ 153 bus_space_handle_t *)); 154 static void *sbus_intr_establish __P(( 155 bus_space_tag_t, 156 int, /*level*/ 157 int, /*flags*/ 158 int (*) __P((void *)), /*handler*/ 159 void *)); /*handler arg*/ 160 161 162 /* autoconfiguration driver */ 163 int sbus_match __P((struct device *, struct cfdata *, void *)); 164 void sbus_attach __P((struct device *, struct device *, void *)); 165 166 167 struct cfattach sbus_ca = { 168 sizeof(struct sbus_softc), sbus_match, sbus_attach 169 }; 170 171 extern struct cfdriver sbus_cd; 172 173 /* 174 * DVMA routines 175 */ 176 int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 177 bus_size_t, struct proc *, int)); 178 void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 179 int sbus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 180 bus_dma_segment_t *, int, bus_size_t, int)); 181 void sbus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 182 bus_size_t, int)); 183 int sbus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 184 bus_size_t alignment, bus_size_t boundary, 185 bus_dma_segment_t *segs, int nsegs, int *rsegs, 186 int flags)); 187 void sbus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 188 int nsegs)); 189 int sbus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 190 int nsegs, size_t size, caddr_t *kvap, int flags)); 191 void sbus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 192 size_t size)); 193 194 /* 195 * Child devices receive the Sbus interrupt level in their attach 196 * arguments. We translate these to CPU IPLs using the following 197 * tables. Note: obio bus interrupt levels are identical to the 198 * processor IPL. 199 * 200 * The second set of tables is used when the Sbus interrupt level 201 * cannot be had from the PROM as an `interrupt' property. We then 202 * fall back on the `intr' property which contains the CPU IPL. 203 */ 204 205 /* Translate Sbus interrupt level to processor IPL */ 206 static int intr_sbus2ipl_4c[] = { 207 0, 1, 2, 3, 5, 7, 8, 9 208 }; 209 static int intr_sbus2ipl_4m[] = { 210 0, 2, 3, 5, 7, 9, 11, 13 211 }; 212 213 /* 214 * This value is or'ed into the attach args' interrupt level cookie 215 * if the interrupt level comes from an `intr' property, i.e. it is 216 * not an Sbus interrupt level. 217 */ 218 #define SBUS_INTR_COMPAT 0x80000000 219 220 221 /* 222 * Print the location of some sbus-attached device (called just 223 * before attaching that device). If `sbus' is not NULL, the 224 * device was found but not configured; print the sbus as well. 225 * Return UNCONF (config_find ignores this if the device was configured). 226 */ 227 int 228 sbus_print(args, busname) 229 void *args; 230 const char *busname; 231 { 232 struct sbus_attach_args *sa = args; 233 int i; 234 235 if (busname) 236 printf("%s at %s", sa->sa_name, busname); 237 printf(" slot %ld offset 0x%lx", (long)sa->sa_slot, 238 (u_long)sa->sa_offset); 239 for (i = 0; i < sa->sa_nintr; i++) { 240 struct sbus_intr *sbi = &sa->sa_intr[i]; 241 242 printf(" vector %lx ipl %ld", 243 (u_long)sbi->sbi_vec, 244 (long)INTLEV(sbi->sbi_pri)); 245 } 246 return (UNCONF); 247 } 248 249 int 250 sbus_match(parent, cf, aux) 251 struct device *parent; 252 struct cfdata *cf; 253 void *aux; 254 { 255 struct mainbus_attach_args *ma = aux; 256 257 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 258 } 259 260 /* 261 * Attach an Sbus. 262 */ 263 void 264 sbus_attach(parent, self, aux) 265 struct device *parent; 266 struct device *self; 267 void *aux; 268 { 269 struct sbus_softc *sc = (struct sbus_softc *)self; 270 struct mainbus_attach_args *ma = aux; 271 char *name; 272 int node = ma->ma_node; 273 274 int node0, error; 275 bus_space_tag_t sbt; 276 struct sbus_attach_args sa; 277 278 sc->sc_bustag = ma->ma_bustag; 279 sc->sc_dmatag = ma->ma_dmatag; 280 sc->sc_sysio = (struct sysioreg*)(u_long)ma->ma_address[0]; /* Use prom mapping for sysio. */ 281 sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */ 282 283 /* Setup interrupt translation tables */ 284 sc->sc_intr2ipl = CPU_ISSUN4C 285 ? intr_sbus2ipl_4c 286 : intr_sbus2ipl_4m; 287 288 /* 289 * Record clock frequency for synchronous SCSI. 290 * IS THIS THE CORRECT DEFAULT?? 291 */ 292 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 293 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 294 295 sbt = sbus_alloc_bustag(sc); 296 sc->sc_dmatag = sbus_alloc_dmatag(sc); 297 298 /* 299 * Get the SBus burst transfer size if burst transfers are supported 300 */ 301 sc->sc_burst = getpropint(node, "burst-sizes", 0); 302 303 /* 304 * Collect address translations from the OBP. 305 */ 306 error = getprop(node, "ranges", sizeof(struct sbus_range), 307 &sc->sc_nrange, (void **)&sc->sc_range); 308 if (error) 309 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 310 311 /* initailise the IOMMU */ 312 313 /* punch in our copies */ 314 sc->sc_is.is_bustag = sc->sc_bustag; 315 sc->sc_is.is_iommu = &sc->sc_sysio->sys_iommu; 316 sc->sc_is.is_sb = &sc->sc_sysio->sys_strbuf; 317 318 /* give us a nice name.. */ 319 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 320 if (name == 0) 321 panic("couldn't malloc iommu name"); 322 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 323 324 iommu_init(name, &sc->sc_is, 0); 325 326 /* 327 * Loop through ROM children, fixing any relative addresses 328 * and then configuring each device. 329 * `specials' is an array of device names that are treated 330 * specially: 331 */ 332 node0 = firstchild(node); 333 for (node = node0; node; node = nextsibling(node)) { 334 char *name = getpropstring(node, "name"); 335 336 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 337 node, &sa) != 0) { 338 printf("sbus_attach: %s: incomplete\n", name); 339 continue; 340 } 341 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 342 sbus_destroy_attach_args(&sa); 343 } 344 } 345 346 int 347 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 348 struct sbus_softc *sc; 349 bus_space_tag_t bustag; 350 bus_dma_tag_t dmatag; 351 int node; 352 struct sbus_attach_args *sa; 353 { 354 /*struct sbus_reg sbusreg;*/ 355 /*int base;*/ 356 int error; 357 int n; 358 359 bzero(sa, sizeof(struct sbus_attach_args)); 360 error = getprop(node, "name", 1, &n, (void **)&sa->sa_name); 361 if (error != 0) 362 return (error); 363 sa->sa_name[n] = '\0'; 364 365 sa->sa_bustag = bustag; 366 sa->sa_dmatag = dmatag; 367 sa->sa_node = node; 368 369 error = getprop(node, "reg", sizeof(struct sbus_reg), 370 &sa->sa_nreg, (void **)&sa->sa_reg); 371 if (error != 0) { 372 char buf[32]; 373 if (error != ENOENT || 374 !node_has_property(node, "device_type") || 375 strcmp(getpropstringA(node, "device_type", buf), 376 "hierarchical") != 0) 377 return (error); 378 } 379 for (n = 0; n < sa->sa_nreg; n++) { 380 /* Convert to relative addressing, if necessary */ 381 u_int32_t base = sa->sa_reg[n].sbr_offset; 382 if (SBUS_ABS(base)) { 383 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 384 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 385 } 386 } 387 388 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr, 389 sa->sa_slot)) != 0) 390 return (error); 391 392 error = getprop(node, "address", sizeof(u_int32_t), 393 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 394 if (error != 0 && error != ENOENT) 395 return (error); 396 397 return (0); 398 } 399 400 void 401 sbus_destroy_attach_args(sa) 402 struct sbus_attach_args *sa; 403 { 404 if (sa->sa_name != NULL) 405 free(sa->sa_name, M_DEVBUF); 406 407 if (sa->sa_nreg != 0) 408 free(sa->sa_reg, M_DEVBUF); 409 410 if (sa->sa_intr) 411 free(sa->sa_intr, M_DEVBUF); 412 413 if (sa->sa_promvaddrs) 414 free((void *)sa->sa_promvaddrs, M_DEVBUF); 415 416 bzero(sa, sizeof(struct sbus_attach_args)); /*DEBUG*/ 417 } 418 419 420 int 421 _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp) 422 bus_space_tag_t t; 423 bus_type_t btype; 424 bus_addr_t offset; 425 bus_size_t size; 426 int flags; 427 vaddr_t vaddr; 428 bus_space_handle_t *hp; 429 { 430 struct sbus_softc *sc = t->cookie; 431 int64_t slot = btype; 432 int i; 433 434 for (i = 0; i < sc->sc_nrange; i++) { 435 bus_addr_t paddr; 436 437 if (sc->sc_range[i].cspace != slot) 438 continue; 439 440 /* We've found the connection to the parent bus */ 441 paddr = sc->sc_range[i].poffset + offset; 442 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 443 DPRINTF(SDB_DVMA, 444 ("\n_sbus_bus_map: mapping paddr slot %lx offset %lx poffset %lx paddr %lx\n", 445 (long)slot, (long)offset, (long)sc->sc_range[i].poffset, 446 (long)paddr)); 447 return (bus_space_map2(sc->sc_bustag, 0, paddr, 448 size, flags, vaddr, hp)); 449 } 450 451 return (EINVAL); 452 } 453 454 int 455 sbus_bus_mmap(t, btype, paddr, flags, hp) 456 bus_space_tag_t t; 457 bus_type_t btype; 458 bus_addr_t paddr; 459 int flags; 460 bus_space_handle_t *hp; 461 { 462 bus_addr_t offset = paddr; 463 int slot = (paddr>>32); 464 struct sbus_softc *sc = t->cookie; 465 int i; 466 467 for (i = 0; i < sc->sc_nrange; i++) { 468 bus_addr_t paddr; 469 470 if (sc->sc_range[i].cspace != slot) 471 continue; 472 473 paddr = sc->sc_range[i].poffset + offset; 474 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 475 return (bus_space_mmap(sc->sc_bustag, 0, paddr, 476 flags, hp)); 477 } 478 479 return (-1); 480 } 481 482 483 /* 484 * Each attached device calls sbus_establish after it initializes 485 * its sbusdev portion. 486 */ 487 void 488 sbus_establish(sd, dev) 489 register struct sbusdev *sd; 490 register struct device *dev; 491 { 492 register struct sbus_softc *sc; 493 register struct device *curdev; 494 495 /* 496 * We have to look for the sbus by name, since it is not necessarily 497 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 498 * We don't just use the device structure of the above-attached 499 * sbus, since we might (in the future) support multiple sbus's. 500 */ 501 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 502 if (!curdev || !curdev->dv_xname) 503 panic("sbus_establish: can't find sbus parent for %s", 504 sd->sd_dev->dv_xname 505 ? sd->sd_dev->dv_xname 506 : "<unknown>" ); 507 508 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 509 break; 510 } 511 sc = (struct sbus_softc *) curdev; 512 513 sd->sd_dev = dev; 514 sd->sd_bchain = sc->sc_sbdev; 515 sc->sc_sbdev = sd; 516 } 517 518 /* 519 * Reset the given sbus. 520 */ 521 void 522 sbusreset(sbus) 523 int sbus; 524 { 525 register struct sbusdev *sd; 526 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 527 struct device *dev; 528 529 printf("reset %s:", sc->sc_dev.dv_xname); 530 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 531 if (sd->sd_reset) { 532 dev = sd->sd_dev; 533 (*sd->sd_reset)(dev); 534 printf(" %s", dev->dv_xname); 535 } 536 } 537 /* Reload iommu regs */ 538 iommu_reset(&sc->sc_is); 539 } 540 541 /* 542 * Get interrupt attributes for an Sbus device. 543 */ 544 int 545 sbus_get_intr(sc, node, ipp, np, slot) 546 struct sbus_softc *sc; 547 int node; 548 struct sbus_intr **ipp; 549 int *np; 550 int slot; 551 { 552 int *ipl; 553 int n, i; 554 char buf[32]; 555 556 /* 557 * The `interrupts' property contains the Sbus interrupt level. 558 */ 559 ipl = NULL; 560 if (getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 561 struct sbus_intr *ip; 562 int pri; 563 564 /* Default to interrupt level 2 -- otherwise unused */ 565 pri = INTLEVENCODE(2); 566 567 /* Change format to an `struct sbus_intr' array */ 568 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 569 if (ip == NULL) 570 return (ENOMEM); 571 572 /* 573 * Now things get ugly. We need to take this value which is 574 * the interrupt vector number and encode the IPL into it 575 * somehow. Luckily, the interrupt vector has lots of free 576 * space and we can easily stuff the IPL in there for a while. 577 */ 578 getpropstringA(node, "device_type", buf); 579 if (!buf[0]) 580 getpropstringA(node, "name", buf); 581 582 for (i = 0; intrmap[i].in_class; i++) 583 if (strcmp(intrmap[i].in_class, buf) == 0) { 584 pri = INTLEVENCODE(intrmap[i].in_lev); 585 break; 586 } 587 588 /* 589 * Sbus card devices need the slot number encoded into 590 * the vector as this is generally not done. 591 */ 592 if ((ipl[0] & INTMAP_OBIO) == 0) 593 pri |= slot << 3; 594 595 for (n = 0; n < *np; n++) { 596 /* 597 * We encode vector and priority into sbi_pri so we 598 * can pass them as a unit. This will go away if 599 * sbus_establish ever takes an sbus_intr instead 600 * of an integer level. 601 * Stuff the real vector in sbi_vec. 602 */ 603 604 ip[n].sbi_pri = pri|ipl[n]; 605 ip[n].sbi_vec = ipl[n]; 606 } 607 free(ipl, M_DEVBUF); 608 *ipp = ip; 609 } 610 611 return (0); 612 } 613 614 615 /* 616 * Install an interrupt handler for an Sbus device. 617 */ 618 void * 619 sbus_intr_establish(t, level, flags, handler, arg) 620 bus_space_tag_t t; 621 int level; 622 int flags; 623 int (*handler) __P((void *)); 624 void *arg; 625 { 626 struct sbus_softc *sc = t->cookie; 627 struct intrhand *ih; 628 int ipl; 629 long vec = level; 630 631 ih = (struct intrhand *) 632 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 633 if (ih == NULL) 634 return (NULL); 635 636 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 637 ipl = vec; 638 else if ((vec & SBUS_INTR_COMPAT) != 0) 639 ipl = vec & ~SBUS_INTR_COMPAT; 640 else { 641 /* Decode and remove IPL */ 642 ipl = INTLEV(vec); 643 vec = INTVEC(vec); 644 DPRINTF(SDB_INTR, 645 ("\nsbus: intr[%ld]%lx: %lx\nHunting for IRQ...\n", 646 (long)ipl, (long)vec, intrlev[vec])); 647 if ((vec & INTMAP_OBIO) == 0) { 648 /* We're in an SBUS slot */ 649 /* Register the map and clear intr registers */ 650 651 int slot = INTSLOT(level); 652 653 ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[slot]; 654 ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[vec]; 655 #ifdef DEBUG 656 if (sbus_debug & SDB_INTR) { 657 int64_t intrmap = *ih->ih_map; 658 659 printf("Found SBUS %lx IRQ as %llx in slot %d\n", 660 (long)vec, (long long)intrmap, slot); 661 printf("\tmap addr %p clr addr %p\n", ih->ih_map, ih->ih_clr); 662 } 663 #endif 664 /* Enable the interrupt */ 665 vec |= INTMAP_V; 666 /* Insert IGN */ 667 vec |= sc->sc_ign; 668 bus_space_write_8(sc->sc_bustag, ih->ih_map, 0, vec); 669 } else { 670 int64_t *intrptr = &sc->sc_sysio->scsi_int_map; 671 int64_t intrmap = 0; 672 int i; 673 674 /* Insert IGN */ 675 vec |= sc->sc_ign; 676 for (i = 0; &intrptr[i] <= 677 (int64_t *)&sc->sc_sysio->reserved_int_map && 678 INTVEC(intrmap = intrptr[i]) != INTVEC(vec); i++) 679 ; 680 if (INTVEC(intrmap) == INTVEC(vec)) { 681 DPRINTF(SDB_INTR, 682 ("Found OBIO %lx IRQ as %lx in slot %d\n", 683 vec, (long)intrmap, i)); 684 /* Register the map and clear intr registers */ 685 ih->ih_map = &intrptr[i]; 686 intrptr = (int64_t *)&sc->sc_sysio->scsi_clr_int; 687 ih->ih_clr = &intrptr[i]; 688 /* Enable the interrupt */ 689 intrmap |= INTMAP_V; 690 bus_space_write_8(sc->sc_bustag, ih->ih_map, 0, (u_long)intrmap); 691 } else 692 panic("IRQ not found!"); 693 } 694 } 695 #ifdef DEBUG 696 if (sbus_debug & SDB_INTR) { long i; for (i = 0; i < 400000000; i++); } 697 #endif 698 699 ih->ih_fun = handler; 700 ih->ih_arg = arg; 701 ih->ih_number = vec; 702 ih->ih_pil = (1<<ipl); 703 intr_establish(ipl, ih); 704 return (ih); 705 } 706 707 static bus_space_tag_t 708 sbus_alloc_bustag(sc) 709 struct sbus_softc *sc; 710 { 711 bus_space_tag_t sbt; 712 713 sbt = (bus_space_tag_t) 714 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 715 if (sbt == NULL) 716 return (NULL); 717 718 bzero(sbt, sizeof *sbt); 719 sbt->cookie = sc; 720 sbt->parent = sc->sc_bustag; 721 sbt->type = SBUS_BUS_SPACE; 722 sbt->sparc_bus_map = _sbus_bus_map; 723 sbt->sparc_bus_mmap = sbus_bus_mmap; 724 sbt->sparc_intr_establish = sbus_intr_establish; 725 return (sbt); 726 } 727 728 729 static bus_dma_tag_t 730 sbus_alloc_dmatag(sc) 731 struct sbus_softc *sc; 732 { 733 bus_dma_tag_t sdt, psdt = sc->sc_dmatag; 734 735 sdt = (bus_dma_tag_t) 736 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 737 if (sdt == NULL) 738 /* Panic? */ 739 return (psdt); 740 741 sdt->_cookie = sc; 742 sdt->_parent = psdt; 743 #define PCOPY(x) sdt->x = psdt->x 744 PCOPY(_dmamap_create); 745 PCOPY(_dmamap_destroy); 746 sdt->_dmamap_load = sbus_dmamap_load; 747 PCOPY(_dmamap_load_mbuf); 748 PCOPY(_dmamap_load_uio); 749 sdt->_dmamap_load_raw = sbus_dmamap_load_raw; 750 sdt->_dmamap_unload = sbus_dmamap_unload; 751 sdt->_dmamap_sync = sbus_dmamap_sync; 752 sdt->_dmamem_alloc = sbus_dmamem_alloc; 753 sdt->_dmamem_free = sbus_dmamem_free; 754 sdt->_dmamem_map = sbus_dmamem_map; 755 sdt->_dmamem_unmap = sbus_dmamem_unmap; 756 PCOPY(_dmamem_mmap); 757 #undef PCOPY 758 sc->sc_dmatag = sdt; 759 return (sdt); 760 } 761 762 int 763 sbus_dmamap_load(tag, map, buf, buflen, p, flags) 764 bus_dma_tag_t tag; 765 bus_dmamap_t map; 766 void *buf; 767 bus_size_t buflen; 768 struct proc *p; 769 int flags; 770 { 771 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 772 773 return (iommu_dvmamap_load(tag, &sc->sc_is, map, buf, buflen, p, flags)); 774 } 775 776 int 777 sbus_dmamap_load_raw(tag, map, segs, nsegs, size, flags) 778 bus_dma_tag_t tag; 779 bus_dmamap_t map; 780 bus_dma_segment_t *segs; 781 int nsegs; 782 bus_size_t size; 783 int flags; 784 { 785 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 786 787 return (iommu_dvmamap_load_raw(tag, &sc->sc_is, map, segs, nsegs, size, flags)); 788 } 789 790 void 791 sbus_dmamap_unload(tag, map) 792 bus_dma_tag_t tag; 793 bus_dmamap_t map; 794 { 795 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 796 797 iommu_dvmamap_unload(tag, &sc->sc_is, map); 798 } 799 800 void 801 sbus_dmamap_sync(tag, map, offset, len, ops) 802 bus_dma_tag_t tag; 803 bus_dmamap_t map; 804 bus_addr_t offset; 805 bus_size_t len; 806 int ops; 807 { 808 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 809 810 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 811 /* Flush the CPU then the IOMMU */ 812 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 813 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 814 } 815 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 816 /* Flush the IOMMU then the CPU */ 817 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 818 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 819 } 820 } 821 822 int 823 sbus_dmamem_alloc(tag, size, alignment, boundary, segs, nsegs, rsegs, flags) 824 bus_dma_tag_t tag; 825 bus_size_t size; 826 bus_size_t alignment; 827 bus_size_t boundary; 828 bus_dma_segment_t *segs; 829 int nsegs; 830 int *rsegs; 831 int flags; 832 { 833 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 834 835 return (iommu_dvmamem_alloc(tag, &sc->sc_is, size, alignment, boundary, 836 segs, nsegs, rsegs, flags)); 837 } 838 839 void 840 sbus_dmamem_free(tag, segs, nsegs) 841 bus_dma_tag_t tag; 842 bus_dma_segment_t *segs; 843 int nsegs; 844 { 845 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 846 847 iommu_dvmamem_free(tag, &sc->sc_is, segs, nsegs); 848 } 849 850 int 851 sbus_dmamem_map(tag, segs, nsegs, size, kvap, flags) 852 bus_dma_tag_t tag; 853 bus_dma_segment_t *segs; 854 int nsegs; 855 size_t size; 856 caddr_t *kvap; 857 int flags; 858 { 859 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 860 861 return (iommu_dvmamem_map(tag, &sc->sc_is, segs, nsegs, size, kvap, flags)); 862 } 863 864 void 865 sbus_dmamem_unmap(tag, kva, size) 866 bus_dma_tag_t tag; 867 caddr_t kva; 868 size_t size; 869 { 870 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 871 872 iommu_dvmamem_unmap(tag, &sc->sc_is, kva, size); 873 } 874
Indexes created Thu Oct 02 14:10:14 GMT 2025