sbus.c revision 1.38
1 /* $NetBSD: sbus.c,v 1.38 2000/12/04 20:19:49 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Copyright (c) 1999 Eduardo Horvath 85 * 86 * Redistribution and use in source and binary forms, with or without 87 * modification, are permitted provided that the following conditions 88 * are met: 89 * 1. Redistributions of source code must retain the above copyright 90 * notice, this list of conditions and the following disclaimer. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 */ 105 106 107 /* 108 * Sbus stuff. 109 */ 110 #include "opt_ddb.h" 111 112 #include <sys/param.h> 113 #include <sys/extent.h> 114 #include <sys/malloc.h> 115 #include <sys/systm.h> 116 #include <sys/device.h> 117 118 #include <machine/bus.h> 119 #include <sparc64/sparc64/cache.h> 120 #include <sparc64/dev/iommureg.h> 121 #include <sparc64/dev/iommuvar.h> 122 #include <sparc64/dev/sbusreg.h> 123 #include <dev/sbus/sbusvar.h> 124 125 #include <machine/autoconf.h> 126 #include <machine/cpu.h> 127 #include <machine/sparc64.h> 128 129 #ifdef DEBUG 130 #define SDB_DVMA 0x1 131 #define SDB_INTR 0x2 132 int sbus_debug = 0; 133 #define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 134 #else 135 #define DPRINTF(l, s) 136 #endif 137 138 void sbusreset __P((int)); 139 140 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 141 static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *)); 142 static int sbus_get_intr __P((struct sbus_softc *, int, 143 struct sbus_intr **, int *, int)); 144 static int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 145 int, bus_space_handle_t *)); 146 static int _sbus_bus_map __P(( 147 bus_space_tag_t, 148 bus_type_t, 149 bus_addr_t, /*offset*/ 150 bus_size_t, /*size*/ 151 int, /*flags*/ 152 vaddr_t, /*preferred virtual address */ 153 bus_space_handle_t *)); 154 static void *sbus_intr_establish __P(( 155 bus_space_tag_t, 156 int, /*Sbus interrupt level*/ 157 int, /*`device class' priority*/ 158 int, /*flags*/ 159 int (*) __P((void *)), /*handler*/ 160 void *)); /*handler arg*/ 161 162 163 /* autoconfiguration driver */ 164 int sbus_match __P((struct device *, struct cfdata *, void *)); 165 void sbus_attach __P((struct device *, struct device *, void *)); 166 167 168 struct cfattach sbus_ca = { 169 sizeof(struct sbus_softc), sbus_match, sbus_attach 170 }; 171 172 extern struct cfdriver sbus_cd; 173 174 /* 175 * DVMA routines 176 */ 177 int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 178 bus_size_t, struct proc *, int)); 179 void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 180 int sbus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 181 bus_dma_segment_t *, int, bus_size_t, int)); 182 void sbus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 183 bus_size_t, int)); 184 int sbus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 185 bus_size_t alignment, bus_size_t boundary, 186 bus_dma_segment_t *segs, int nsegs, int *rsegs, 187 int flags)); 188 void sbus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 189 int nsegs)); 190 int sbus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 191 int nsegs, size_t size, caddr_t *kvap, int flags)); 192 void sbus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 193 size_t size)); 194 195 /* 196 * Child devices receive the Sbus interrupt level in their attach 197 * arguments. We translate these to CPU IPLs using the following 198 * tables. Note: obio bus interrupt levels are identical to the 199 * processor IPL. 200 * 201 * The second set of tables is used when the Sbus interrupt level 202 * cannot be had from the PROM as an `interrupt' property. We then 203 * fall back on the `intr' property which contains the CPU IPL. 204 */ 205 206 /* Translate Sbus interrupt level to processor IPL */ 207 static int intr_sbus2ipl_4c[] = { 208 0, 1, 2, 3, 5, 7, 8, 9 209 }; 210 static int intr_sbus2ipl_4m[] = { 211 0, 2, 3, 5, 7, 9, 11, 13 212 }; 213 214 /* 215 * This value is or'ed into the attach args' interrupt level cookie 216 * if the interrupt level comes from an `intr' property, i.e. it is 217 * not an Sbus interrupt level. 218 */ 219 #define SBUS_INTR_COMPAT 0x80000000 220 221 222 /* 223 * Print the location of some sbus-attached device (called just 224 * before attaching that device). If `sbus' is not NULL, the 225 * device was found but not configured; print the sbus as well. 226 * Return UNCONF (config_find ignores this if the device was configured). 227 */ 228 int 229 sbus_print(args, busname) 230 void *args; 231 const char *busname; 232 { 233 struct sbus_attach_args *sa = args; 234 int i; 235 236 if (busname) 237 printf("%s at %s", sa->sa_name, busname); 238 printf(" slot %ld offset 0x%lx", (long)sa->sa_slot, 239 (u_long)sa->sa_offset); 240 for (i = 0; i < sa->sa_nintr; i++) { 241 struct sbus_intr *sbi = &sa->sa_intr[i]; 242 243 printf(" vector %lx ipl %ld", 244 (u_long)sbi->sbi_vec, 245 (long)INTLEV(sbi->sbi_pri)); 246 } 247 return (UNCONF); 248 } 249 250 int 251 sbus_match(parent, cf, aux) 252 struct device *parent; 253 struct cfdata *cf; 254 void *aux; 255 { 256 struct mainbus_attach_args *ma = aux; 257 258 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 259 } 260 261 /* 262 * Attach an Sbus. 263 */ 264 void 265 sbus_attach(parent, self, aux) 266 struct device *parent; 267 struct device *self; 268 void *aux; 269 { 270 struct sbus_softc *sc = (struct sbus_softc *)self; 271 struct mainbus_attach_args *ma = aux; 272 char *name; 273 int node = ma->ma_node; 274 275 int node0, error; 276 bus_space_tag_t sbt; 277 struct sbus_attach_args sa; 278 279 sc->sc_bustag = ma->ma_bustag; 280 sc->sc_dmatag = ma->ma_dmatag; 281 sc->sc_sysio = (struct sysioreg*)(u_long)ma->ma_address[0]; /* Use prom mapping for sysio. */ 282 sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */ 283 284 /* Setup interrupt translation tables */ 285 sc->sc_intr2ipl = CPU_ISSUN4C 286 ? intr_sbus2ipl_4c 287 : intr_sbus2ipl_4m; 288 289 /* 290 * Record clock frequency for synchronous SCSI. 291 * IS THIS THE CORRECT DEFAULT?? 292 */ 293 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 294 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 295 296 sbt = sbus_alloc_bustag(sc); 297 sc->sc_dmatag = sbus_alloc_dmatag(sc); 298 299 /* 300 * Get the SBus burst transfer size if burst transfers are supported 301 */ 302 sc->sc_burst = getpropint(node, "burst-sizes", 0); 303 304 /* 305 * Collect address translations from the OBP. 306 */ 307 error = getprop(node, "ranges", sizeof(struct sbus_range), 308 &sc->sc_nrange, (void **)&sc->sc_range); 309 if (error) 310 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 311 312 /* initailise the IOMMU */ 313 314 /* punch in our copies */ 315 sc->sc_is.is_bustag = sc->sc_bustag; 316 sc->sc_is.is_iommu = &sc->sc_sysio->sys_iommu; 317 sc->sc_is.is_sb = &sc->sc_sysio->sys_strbuf; 318 319 /* give us a nice name.. */ 320 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 321 if (name == 0) 322 panic("couldn't malloc iommu name"); 323 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 324 325 iommu_init(name, &sc->sc_is, 0); 326 327 /* 328 * Loop through ROM children, fixing any relative addresses 329 * and then configuring each device. 330 * `specials' is an array of device names that are treated 331 * specially: 332 */ 333 node0 = firstchild(node); 334 for (node = node0; node; node = nextsibling(node)) { 335 char *name = getpropstring(node, "name"); 336 337 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 338 node, &sa) != 0) { 339 printf("sbus_attach: %s: incomplete\n", name); 340 continue; 341 } 342 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 343 sbus_destroy_attach_args(&sa); 344 } 345 } 346 347 int 348 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 349 struct sbus_softc *sc; 350 bus_space_tag_t bustag; 351 bus_dma_tag_t dmatag; 352 int node; 353 struct sbus_attach_args *sa; 354 { 355 /*struct sbus_reg sbusreg;*/ 356 /*int base;*/ 357 int error; 358 int n; 359 360 bzero(sa, sizeof(struct sbus_attach_args)); 361 error = getprop(node, "name", 1, &n, (void **)&sa->sa_name); 362 if (error != 0) 363 return (error); 364 sa->sa_name[n] = '\0'; 365 366 sa->sa_bustag = bustag; 367 sa->sa_dmatag = dmatag; 368 sa->sa_node = node; 369 sa->sa_frequency = sc->sc_clockfreq; 370 371 error = getprop(node, "reg", sizeof(struct sbus_reg), 372 &sa->sa_nreg, (void **)&sa->sa_reg); 373 if (error != 0) { 374 char buf[32]; 375 if (error != ENOENT || 376 !node_has_property(node, "device_type") || 377 strcmp(getpropstringA(node, "device_type", buf), 378 "hierarchical") != 0) 379 return (error); 380 } 381 for (n = 0; n < sa->sa_nreg; n++) { 382 /* Convert to relative addressing, if necessary */ 383 u_int32_t base = sa->sa_reg[n].sbr_offset; 384 if (SBUS_ABS(base)) { 385 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 386 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 387 } 388 } 389 390 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr, 391 sa->sa_slot)) != 0) 392 return (error); 393 394 error = getprop(node, "address", sizeof(u_int32_t), 395 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 396 if (error != 0 && error != ENOENT) 397 return (error); 398 399 return (0); 400 } 401 402 void 403 sbus_destroy_attach_args(sa) 404 struct sbus_attach_args *sa; 405 { 406 if (sa->sa_name != NULL) 407 free(sa->sa_name, M_DEVBUF); 408 409 if (sa->sa_nreg != 0) 410 free(sa->sa_reg, M_DEVBUF); 411 412 if (sa->sa_intr) 413 free(sa->sa_intr, M_DEVBUF); 414 415 if (sa->sa_promvaddrs) 416 free((void *)sa->sa_promvaddrs, M_DEVBUF); 417 418 bzero(sa, sizeof(struct sbus_attach_args)); /*DEBUG*/ 419 } 420 421 422 int 423 _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp) 424 bus_space_tag_t t; 425 bus_type_t btype; 426 bus_addr_t offset; 427 bus_size_t size; 428 int flags; 429 vaddr_t vaddr; 430 bus_space_handle_t *hp; 431 { 432 struct sbus_softc *sc = t->cookie; 433 int64_t slot = btype; 434 int i; 435 436 for (i = 0; i < sc->sc_nrange; i++) { 437 bus_addr_t paddr; 438 439 if (sc->sc_range[i].cspace != slot) 440 continue; 441 442 /* We've found the connection to the parent bus */ 443 paddr = sc->sc_range[i].poffset + offset; 444 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 445 DPRINTF(SDB_DVMA, 446 ("\n_sbus_bus_map: mapping paddr slot %lx offset %lx poffset %lx paddr %lx\n", 447 (long)slot, (long)offset, (long)sc->sc_range[i].poffset, 448 (long)paddr)); 449 return (bus_space_map2(sc->sc_bustag, 0, paddr, 450 size, flags, vaddr, hp)); 451 } 452 453 return (EINVAL); 454 } 455 456 int 457 sbus_bus_mmap(t, btype, paddr, flags, hp) 458 bus_space_tag_t t; 459 bus_type_t btype; 460 bus_addr_t paddr; 461 int flags; 462 bus_space_handle_t *hp; 463 { 464 bus_addr_t offset = paddr; 465 int slot = btype; 466 struct sbus_softc *sc = t->cookie; 467 int i; 468 469 for (i = 0; i < sc->sc_nrange; i++) { 470 bus_addr_t paddr; 471 472 if (sc->sc_range[i].cspace != slot) 473 continue; 474 475 paddr = sc->sc_range[i].poffset + offset; 476 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 477 return (bus_space_mmap(sc->sc_bustag, 0, paddr, 478 flags, hp)); 479 } 480 481 return (-1); 482 } 483 484 485 /* 486 * Each attached device calls sbus_establish after it initializes 487 * its sbusdev portion. 488 */ 489 void 490 sbus_establish(sd, dev) 491 register struct sbusdev *sd; 492 register struct device *dev; 493 { 494 register struct sbus_softc *sc; 495 register struct device *curdev; 496 497 /* 498 * We have to look for the sbus by name, since it is not necessarily 499 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 500 * We don't just use the device structure of the above-attached 501 * sbus, since we might (in the future) support multiple sbus's. 502 */ 503 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 504 if (!curdev || !curdev->dv_xname) 505 panic("sbus_establish: can't find sbus parent for %s", 506 sd->sd_dev->dv_xname 507 ? sd->sd_dev->dv_xname 508 : "<unknown>" ); 509 510 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 511 break; 512 } 513 sc = (struct sbus_softc *) curdev; 514 515 sd->sd_dev = dev; 516 sd->sd_bchain = sc->sc_sbdev; 517 sc->sc_sbdev = sd; 518 } 519 520 /* 521 * Reset the given sbus. 522 */ 523 void 524 sbusreset(sbus) 525 int sbus; 526 { 527 register struct sbusdev *sd; 528 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 529 struct device *dev; 530 531 printf("reset %s:", sc->sc_dev.dv_xname); 532 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 533 if (sd->sd_reset) { 534 dev = sd->sd_dev; 535 (*sd->sd_reset)(dev); 536 printf(" %s", dev->dv_xname); 537 } 538 } 539 /* Reload iommu regs */ 540 iommu_reset(&sc->sc_is); 541 } 542 543 /* 544 * Get interrupt attributes for an Sbus device. 545 */ 546 int 547 sbus_get_intr(sc, node, ipp, np, slot) 548 struct sbus_softc *sc; 549 int node; 550 struct sbus_intr **ipp; 551 int *np; 552 int slot; 553 { 554 int *ipl; 555 int n, i; 556 char buf[32]; 557 558 /* 559 * The `interrupts' property contains the Sbus interrupt level. 560 */ 561 ipl = NULL; 562 if (getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 563 struct sbus_intr *ip; 564 int pri; 565 566 /* Default to interrupt level 2 -- otherwise unused */ 567 pri = INTLEVENCODE(2); 568 569 /* Change format to an `struct sbus_intr' array */ 570 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 571 if (ip == NULL) 572 return (ENOMEM); 573 574 /* 575 * Now things get ugly. We need to take this value which is 576 * the interrupt vector number and encode the IPL into it 577 * somehow. Luckily, the interrupt vector has lots of free 578 * space and we can easily stuff the IPL in there for a while. 579 */ 580 getpropstringA(node, "device_type", buf); 581 if (!buf[0]) 582 getpropstringA(node, "name", buf); 583 584 for (i = 0; intrmap[i].in_class; i++) 585 if (strcmp(intrmap[i].in_class, buf) == 0) { 586 pri = INTLEVENCODE(intrmap[i].in_lev); 587 break; 588 } 589 590 /* 591 * Sbus card devices need the slot number encoded into 592 * the vector as this is generally not done. 593 */ 594 if ((ipl[0] & INTMAP_OBIO) == 0) 595 pri |= slot << 3; 596 597 for (n = 0; n < *np; n++) { 598 /* 599 * We encode vector and priority into sbi_pri so we 600 * can pass them as a unit. This will go away if 601 * sbus_establish ever takes an sbus_intr instead 602 * of an integer level. 603 * Stuff the real vector in sbi_vec. 604 */ 605 606 ip[n].sbi_pri = pri|ipl[n]; 607 ip[n].sbi_vec = ipl[n]; 608 } 609 free(ipl, M_DEVBUF); 610 *ipp = ip; 611 } 612 613 return (0); 614 } 615 616 617 /* 618 * Install an interrupt handler for an Sbus device. 619 */ 620 void * 621 sbus_intr_establish(t, pri, level, flags, handler, arg) 622 bus_space_tag_t t; 623 int pri; 624 int level; 625 int flags; 626 int (*handler) __P((void *)); 627 void *arg; 628 { 629 struct sbus_softc *sc = t->cookie; 630 struct intrhand *ih; 631 int ipl; 632 long vec = pri; 633 634 ih = (struct intrhand *) 635 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 636 if (ih == NULL) 637 return (NULL); 638 639 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 640 ipl = vec; 641 else if ((vec & SBUS_INTR_COMPAT) != 0) 642 ipl = vec & ~SBUS_INTR_COMPAT; 643 else { 644 /* Decode and remove IPL */ 645 ipl = INTLEV(vec); 646 vec = INTVEC(vec); 647 DPRINTF(SDB_INTR, 648 ("\nsbus: intr[%ld]%lx: %lx\nHunting for IRQ...\n", 649 (long)ipl, (long)vec, intrlev[vec])); 650 if ((vec & INTMAP_OBIO) == 0) { 651 /* We're in an SBUS slot */ 652 /* Register the map and clear intr registers */ 653 654 int slot = INTSLOT(pri); 655 656 ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[slot]; 657 ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[vec]; 658 #ifdef DEBUG 659 if (sbus_debug & SDB_INTR) { 660 int64_t intrmap = *ih->ih_map; 661 662 printf("SBUS %lx IRQ as %llx in slot %d\n", 663 (long)vec, (long long)intrmap, slot); 664 printf("\tmap addr %p clr addr %p\n", 665 ih->ih_map, ih->ih_clr); 666 } 667 #endif 668 /* Enable the interrupt */ 669 vec |= INTMAP_V; 670 /* Insert IGN */ 671 vec |= sc->sc_ign; 672 bus_space_write_8(sc->sc_bustag, 673 (bus_space_handle_t)(u_long)ih->ih_map, 0, vec); 674 } else { 675 int64_t *intrptr = &sc->sc_sysio->scsi_int_map; 676 int64_t intrmap = 0; 677 int i; 678 679 /* Insert IGN */ 680 vec |= sc->sc_ign; 681 for (i = 0; &intrptr[i] <= 682 (int64_t *)&sc->sc_sysio->reserved_int_map && 683 INTVEC(intrmap = intrptr[i]) != INTVEC(vec); i++) 684 ; 685 if (INTVEC(intrmap) == INTVEC(vec)) { 686 DPRINTF(SDB_INTR, 687 ("OBIO %lx IRQ as %lx in slot %d\n", 688 vec, (long)intrmap, i)); 689 /* Register the map and clear intr registers */ 690 ih->ih_map = &intrptr[i]; 691 intrptr = (int64_t *)&sc->sc_sysio->scsi_clr_int; 692 ih->ih_clr = &intrptr[i]; 693 /* Enable the interrupt */ 694 intrmap |= INTMAP_V; 695 bus_space_write_8(sc->sc_bustag, 696 (bus_space_handle_t)(u_long)ih->ih_map, 0, 697 (u_long)intrmap); 698 } else 699 panic("IRQ not found!"); 700 } 701 } 702 #ifdef DEBUG 703 if (sbus_debug & SDB_INTR) { long i; for (i = 0; i < 400000000; i++); } 704 #endif 705 706 ih->ih_fun = handler; 707 ih->ih_arg = arg; 708 ih->ih_number = vec; 709 ih->ih_pil = (1<<ipl); 710 intr_establish(ipl, ih); 711 return (ih); 712 } 713 714 static bus_space_tag_t 715 sbus_alloc_bustag(sc) 716 struct sbus_softc *sc; 717 { 718 bus_space_tag_t sbt; 719 720 sbt = (bus_space_tag_t) 721 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 722 if (sbt == NULL) 723 return (NULL); 724 725 bzero(sbt, sizeof *sbt); 726 sbt->cookie = sc; 727 sbt->parent = sc->sc_bustag; 728 sbt->type = SBUS_BUS_SPACE; 729 sbt->sparc_bus_map = _sbus_bus_map; 730 sbt->sparc_bus_mmap = sbus_bus_mmap; 731 sbt->sparc_intr_establish = sbus_intr_establish; 732 return (sbt); 733 } 734 735 736 static bus_dma_tag_t 737 sbus_alloc_dmatag(sc) 738 struct sbus_softc *sc; 739 { 740 bus_dma_tag_t sdt, psdt = sc->sc_dmatag; 741 742 sdt = (bus_dma_tag_t) 743 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 744 if (sdt == NULL) 745 /* Panic? */ 746 return (psdt); 747 748 sdt->_cookie = sc; 749 sdt->_parent = psdt; 750 #define PCOPY(x) sdt->x = psdt->x 751 PCOPY(_dmamap_create); 752 PCOPY(_dmamap_destroy); 753 sdt->_dmamap_load = sbus_dmamap_load; 754 PCOPY(_dmamap_load_mbuf); 755 PCOPY(_dmamap_load_uio); 756 sdt->_dmamap_load_raw = sbus_dmamap_load_raw; 757 sdt->_dmamap_unload = sbus_dmamap_unload; 758 sdt->_dmamap_sync = sbus_dmamap_sync; 759 sdt->_dmamem_alloc = sbus_dmamem_alloc; 760 sdt->_dmamem_free = sbus_dmamem_free; 761 sdt->_dmamem_map = sbus_dmamem_map; 762 sdt->_dmamem_unmap = sbus_dmamem_unmap; 763 PCOPY(_dmamem_mmap); 764 #undef PCOPY 765 sc->sc_dmatag = sdt; 766 return (sdt); 767 } 768 769 int 770 sbus_dmamap_load(tag, map, buf, buflen, p, flags) 771 bus_dma_tag_t tag; 772 bus_dmamap_t map; 773 void *buf; 774 bus_size_t buflen; 775 struct proc *p; 776 int flags; 777 { 778 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 779 780 return (iommu_dvmamap_load(tag, &sc->sc_is, map, buf, buflen, p, flags)); 781 } 782 783 int 784 sbus_dmamap_load_raw(tag, map, segs, nsegs, size, flags) 785 bus_dma_tag_t tag; 786 bus_dmamap_t map; 787 bus_dma_segment_t *segs; 788 int nsegs; 789 bus_size_t size; 790 int flags; 791 { 792 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 793 794 return (iommu_dvmamap_load_raw(tag, &sc->sc_is, map, segs, nsegs, flags, size)); 795 } 796 797 void 798 sbus_dmamap_unload(tag, map) 799 bus_dma_tag_t tag; 800 bus_dmamap_t map; 801 { 802 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 803 804 iommu_dvmamap_unload(tag, &sc->sc_is, map); 805 } 806 807 void 808 sbus_dmamap_sync(tag, map, offset, len, ops) 809 bus_dma_tag_t tag; 810 bus_dmamap_t map; 811 bus_addr_t offset; 812 bus_size_t len; 813 int ops; 814 { 815 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 816 817 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 818 /* Flush the CPU then the IOMMU */ 819 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 820 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 821 } 822 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 823 /* Flush the IOMMU then the CPU */ 824 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 825 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 826 } 827 } 828 829 int 830 sbus_dmamem_alloc(tag, size, alignment, boundary, segs, nsegs, rsegs, flags) 831 bus_dma_tag_t tag; 832 bus_size_t size; 833 bus_size_t alignment; 834 bus_size_t boundary; 835 bus_dma_segment_t *segs; 836 int nsegs; 837 int *rsegs; 838 int flags; 839 { 840 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 841 842 return (iommu_dvmamem_alloc(tag, &sc->sc_is, size, alignment, boundary, 843 segs, nsegs, rsegs, flags)); 844 } 845 846 void 847 sbus_dmamem_free(tag, segs, nsegs) 848 bus_dma_tag_t tag; 849 bus_dma_segment_t *segs; 850 int nsegs; 851 { 852 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 853 854 iommu_dvmamem_free(tag, &sc->sc_is, segs, nsegs); 855 } 856 857 int 858 sbus_dmamem_map(tag, segs, nsegs, size, kvap, flags) 859 bus_dma_tag_t tag; 860 bus_dma_segment_t *segs; 861 int nsegs; 862 size_t size; 863 caddr_t *kvap; 864 int flags; 865 { 866 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 867 868 return (iommu_dvmamem_map(tag, &sc->sc_is, segs, nsegs, size, kvap, flags)); 869 } 870 871 void 872 sbus_dmamem_unmap(tag, kva, size) 873 bus_dma_tag_t tag; 874 caddr_t kva; 875 size_t size; 876 { 877 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 878 879 iommu_dvmamem_unmap(tag, &sc->sc_is, kva, size); 880 } 881
Indexes created Thu Oct 02 14:10:14 GMT 2025