sbus.c revision 1.40
1 /* $NetBSD: sbus.c,v 1.40 2001/03/14 00:52:19 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Copyright (c) 1999 Eduardo Horvath 85 * 86 * Redistribution and use in source and binary forms, with or without 87 * modification, are permitted provided that the following conditions 88 * are met: 89 * 1. Redistributions of source code must retain the above copyright 90 * notice, this list of conditions and the following disclaimer. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 */ 105 106 107 /* 108 * Sbus stuff. 109 */ 110 #include "opt_ddb.h" 111 112 #include <sys/param.h> 113 #include <sys/extent.h> 114 #include <sys/malloc.h> 115 #include <sys/systm.h> 116 #include <sys/device.h> 117 #include <sys/reboot.h> 118 119 #include <machine/bus.h> 120 #include <sparc64/sparc64/cache.h> 121 #include <sparc64/dev/iommureg.h> 122 #include <sparc64/dev/iommuvar.h> 123 #include <sparc64/dev/sbusreg.h> 124 #include <dev/sbus/sbusvar.h> 125 126 #include <machine/autoconf.h> 127 #include <machine/cpu.h> 128 #include <machine/sparc64.h> 129 130 #ifdef DEBUG 131 #define SDB_DVMA 0x1 132 #define SDB_INTR 0x2 133 int sbus_debug = 0; 134 #define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 135 #else 136 #define DPRINTF(l, s) 137 #endif 138 139 void sbusreset __P((int)); 140 141 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 142 static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *)); 143 static int sbus_get_intr __P((struct sbus_softc *, int, 144 struct sbus_intr **, int *, int)); 145 static int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 146 int, bus_space_handle_t *)); 147 static int sbus_overtemp __P((void *)); 148 static int _sbus_bus_map __P(( 149 bus_space_tag_t, 150 bus_type_t, 151 bus_addr_t, /*offset*/ 152 bus_size_t, /*size*/ 153 int, /*flags*/ 154 vaddr_t, /*preferred virtual address */ 155 bus_space_handle_t *)); 156 static void *sbus_intr_establish __P(( 157 bus_space_tag_t, 158 int, /*Sbus interrupt level*/ 159 int, /*`device class' priority*/ 160 int, /*flags*/ 161 int (*) __P((void *)), /*handler*/ 162 void *)); /*handler arg*/ 163 164 165 /* autoconfiguration driver */ 166 int sbus_match __P((struct device *, struct cfdata *, void *)); 167 void sbus_attach __P((struct device *, struct device *, void *)); 168 169 170 struct cfattach sbus_ca = { 171 sizeof(struct sbus_softc), sbus_match, sbus_attach 172 }; 173 174 extern struct cfdriver sbus_cd; 175 176 /* 177 * DVMA routines 178 */ 179 int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 180 bus_size_t, struct proc *, int)); 181 void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 182 int sbus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 183 bus_dma_segment_t *, int, bus_size_t, int)); 184 void sbus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 185 bus_size_t, int)); 186 int sbus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 187 bus_size_t alignment, bus_size_t boundary, 188 bus_dma_segment_t *segs, int nsegs, int *rsegs, 189 int flags)); 190 void sbus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 191 int nsegs)); 192 int sbus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 193 int nsegs, size_t size, caddr_t *kvap, int flags)); 194 void sbus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 195 size_t size)); 196 197 /* 198 * Child devices receive the Sbus interrupt level in their attach 199 * arguments. We translate these to CPU IPLs using the following 200 * tables. Note: obio bus interrupt levels are identical to the 201 * processor IPL. 202 * 203 * The second set of tables is used when the Sbus interrupt level 204 * cannot be had from the PROM as an `interrupt' property. We then 205 * fall back on the `intr' property which contains the CPU IPL. 206 */ 207 208 /* Translate Sbus interrupt level to processor IPL */ 209 static int intr_sbus2ipl_4c[] = { 210 0, 1, 2, 3, 5, 7, 8, 9 211 }; 212 static int intr_sbus2ipl_4m[] = { 213 0, 2, 3, 5, 7, 9, 11, 13 214 }; 215 216 /* 217 * This value is or'ed into the attach args' interrupt level cookie 218 * if the interrupt level comes from an `intr' property, i.e. it is 219 * not an Sbus interrupt level. 220 */ 221 #define SBUS_INTR_COMPAT 0x80000000 222 223 224 /* 225 * Print the location of some sbus-attached device (called just 226 * before attaching that device). If `sbus' is not NULL, the 227 * device was found but not configured; print the sbus as well. 228 * Return UNCONF (config_find ignores this if the device was configured). 229 */ 230 int 231 sbus_print(args, busname) 232 void *args; 233 const char *busname; 234 { 235 struct sbus_attach_args *sa = args; 236 int i; 237 238 if (busname) 239 printf("%s at %s", sa->sa_name, busname); 240 printf(" slot %ld offset 0x%lx", (long)sa->sa_slot, 241 (u_long)sa->sa_offset); 242 for (i = 0; i < sa->sa_nintr; i++) { 243 struct sbus_intr *sbi = &sa->sa_intr[i]; 244 245 printf(" vector %lx ipl %ld", 246 (u_long)sbi->sbi_vec, 247 (long)INTLEV(sbi->sbi_pri)); 248 } 249 return (UNCONF); 250 } 251 252 int 253 sbus_match(parent, cf, aux) 254 struct device *parent; 255 struct cfdata *cf; 256 void *aux; 257 { 258 struct mainbus_attach_args *ma = aux; 259 260 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 261 } 262 263 /* 264 * Attach an Sbus. 265 */ 266 void 267 sbus_attach(parent, self, aux) 268 struct device *parent; 269 struct device *self; 270 void *aux; 271 { 272 struct sbus_softc *sc = (struct sbus_softc *)self; 273 struct mainbus_attach_args *ma = aux; 274 struct intrhand *ih; 275 int ipl; 276 char *name; 277 int node = ma->ma_node; 278 279 int node0, error; 280 bus_space_tag_t sbt; 281 struct sbus_attach_args sa; 282 283 sc->sc_bustag = ma->ma_bustag; 284 sc->sc_dmatag = ma->ma_dmatag; 285 sc->sc_sysio = (struct sysioreg*)(u_long)ma->ma_address[0]; /* Use prom mapping for sysio. */ 286 sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */ 287 288 /* Setup interrupt translation tables */ 289 sc->sc_intr2ipl = CPU_ISSUN4C 290 ? intr_sbus2ipl_4c 291 : intr_sbus2ipl_4m; 292 293 /* 294 * Record clock frequency for synchronous SCSI. 295 * IS THIS THE CORRECT DEFAULT?? 296 */ 297 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 298 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 299 300 sbt = sbus_alloc_bustag(sc); 301 sc->sc_dmatag = sbus_alloc_dmatag(sc); 302 303 /* 304 * Get the SBus burst transfer size if burst transfers are supported 305 */ 306 sc->sc_burst = getpropint(node, "burst-sizes", 0); 307 308 /* 309 * Collect address translations from the OBP. 310 */ 311 error = getprop(node, "ranges", sizeof(struct sbus_range), 312 &sc->sc_nrange, (void **)&sc->sc_range); 313 if (error) 314 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 315 316 /* initailise the IOMMU */ 317 318 /* punch in our copies */ 319 sc->sc_is.is_bustag = sc->sc_bustag; 320 sc->sc_is.is_iommu = &sc->sc_sysio->sys_iommu; 321 sc->sc_is.is_sb = &sc->sc_sysio->sys_strbuf; 322 323 /* give us a nice name.. */ 324 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 325 if (name == 0) 326 panic("couldn't malloc iommu name"); 327 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 328 329 iommu_init(name, &sc->sc_is, 0); 330 331 /* Enable the over temp intr */ 332 ih = (struct intrhand *) 333 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 334 ih->ih_map = &sc->sc_sysio->therm_int_map; 335 ih->ih_clr = NULL; /* &sc->sc_sysio->therm_clr_int; */ 336 ih->ih_fun = sbus_overtemp; 337 ipl = 1; 338 ih->ih_pil = (1<<ipl); 339 ih->ih_number = INTVEC(*(ih->ih_map)); 340 intr_establish(ipl, ih); 341 *(ih->ih_map) |= INTMAP_V; 342 343 /* 344 * Loop through ROM children, fixing any relative addresses 345 * and then configuring each device. 346 * `specials' is an array of device names that are treated 347 * specially: 348 */ 349 node0 = firstchild(node); 350 for (node = node0; node; node = nextsibling(node)) { 351 char *name = getpropstring(node, "name"); 352 353 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 354 node, &sa) != 0) { 355 printf("sbus_attach: %s: incomplete\n", name); 356 continue; 357 } 358 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 359 sbus_destroy_attach_args(&sa); 360 } 361 } 362 363 int 364 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 365 struct sbus_softc *sc; 366 bus_space_tag_t bustag; 367 bus_dma_tag_t dmatag; 368 int node; 369 struct sbus_attach_args *sa; 370 { 371 /*struct sbus_reg sbusreg;*/ 372 /*int base;*/ 373 int error; 374 int n; 375 376 bzero(sa, sizeof(struct sbus_attach_args)); 377 error = getprop(node, "name", 1, &n, (void **)&sa->sa_name); 378 if (error != 0) 379 return (error); 380 sa->sa_name[n] = '\0'; 381 382 sa->sa_bustag = bustag; 383 sa->sa_dmatag = dmatag; 384 sa->sa_node = node; 385 sa->sa_frequency = sc->sc_clockfreq; 386 387 error = getprop(node, "reg", sizeof(struct sbus_reg), 388 &sa->sa_nreg, (void **)&sa->sa_reg); 389 if (error != 0) { 390 char buf[32]; 391 if (error != ENOENT || 392 !node_has_property(node, "device_type") || 393 strcmp(getpropstringA(node, "device_type", buf), 394 "hierarchical") != 0) 395 return (error); 396 } 397 for (n = 0; n < sa->sa_nreg; n++) { 398 /* Convert to relative addressing, if necessary */ 399 u_int32_t base = sa->sa_reg[n].sbr_offset; 400 if (SBUS_ABS(base)) { 401 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 402 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 403 } 404 } 405 406 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr, 407 sa->sa_slot)) != 0) 408 return (error); 409 410 error = getprop(node, "address", sizeof(u_int32_t), 411 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 412 if (error != 0 && error != ENOENT) 413 return (error); 414 415 return (0); 416 } 417 418 void 419 sbus_destroy_attach_args(sa) 420 struct sbus_attach_args *sa; 421 { 422 if (sa->sa_name != NULL) 423 free(sa->sa_name, M_DEVBUF); 424 425 if (sa->sa_nreg != 0) 426 free(sa->sa_reg, M_DEVBUF); 427 428 if (sa->sa_intr) 429 free(sa->sa_intr, M_DEVBUF); 430 431 if (sa->sa_promvaddrs) 432 free((void *)sa->sa_promvaddrs, M_DEVBUF); 433 434 bzero(sa, sizeof(struct sbus_attach_args)); /*DEBUG*/ 435 } 436 437 438 int 439 _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp) 440 bus_space_tag_t t; 441 bus_type_t btype; 442 bus_addr_t offset; 443 bus_size_t size; 444 int flags; 445 vaddr_t vaddr; 446 bus_space_handle_t *hp; 447 { 448 struct sbus_softc *sc = t->cookie; 449 int64_t slot = btype; 450 int i; 451 452 for (i = 0; i < sc->sc_nrange; i++) { 453 bus_addr_t paddr; 454 455 if (sc->sc_range[i].cspace != slot) 456 continue; 457 458 /* We've found the connection to the parent bus */ 459 paddr = sc->sc_range[i].poffset + offset; 460 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 461 DPRINTF(SDB_DVMA, 462 ("\n_sbus_bus_map: mapping paddr slot %lx offset %lx poffset %lx paddr %lx\n", 463 (long)slot, (long)offset, (long)sc->sc_range[i].poffset, 464 (long)paddr)); 465 return (bus_space_map2(sc->sc_bustag, 0, paddr, 466 size, flags, vaddr, hp)); 467 } 468 469 return (EINVAL); 470 } 471 472 int 473 sbus_bus_mmap(t, btype, paddr, flags, hp) 474 bus_space_tag_t t; 475 bus_type_t btype; 476 bus_addr_t paddr; 477 int flags; 478 bus_space_handle_t *hp; 479 { 480 bus_addr_t offset = paddr; 481 int slot = btype; 482 struct sbus_softc *sc = t->cookie; 483 int i; 484 485 for (i = 0; i < sc->sc_nrange; i++) { 486 bus_addr_t paddr; 487 488 if (sc->sc_range[i].cspace != slot) 489 continue; 490 491 paddr = sc->sc_range[i].poffset + offset; 492 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 493 return (bus_space_mmap(sc->sc_bustag, 0, paddr, 494 flags, hp)); 495 } 496 497 return (-1); 498 } 499 500 501 /* 502 * Each attached device calls sbus_establish after it initializes 503 * its sbusdev portion. 504 */ 505 void 506 sbus_establish(sd, dev) 507 register struct sbusdev *sd; 508 register struct device *dev; 509 { 510 register struct sbus_softc *sc; 511 register struct device *curdev; 512 513 /* 514 * We have to look for the sbus by name, since it is not necessarily 515 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 516 * We don't just use the device structure of the above-attached 517 * sbus, since we might (in the future) support multiple sbus's. 518 */ 519 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 520 if (!curdev || !curdev->dv_xname) 521 panic("sbus_establish: can't find sbus parent for %s", 522 sd->sd_dev->dv_xname 523 ? sd->sd_dev->dv_xname 524 : "<unknown>" ); 525 526 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 527 break; 528 } 529 sc = (struct sbus_softc *) curdev; 530 531 sd->sd_dev = dev; 532 sd->sd_bchain = sc->sc_sbdev; 533 sc->sc_sbdev = sd; 534 } 535 536 /* 537 * Reset the given sbus. 538 */ 539 void 540 sbusreset(sbus) 541 int sbus; 542 { 543 register struct sbusdev *sd; 544 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 545 struct device *dev; 546 547 printf("reset %s:", sc->sc_dev.dv_xname); 548 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 549 if (sd->sd_reset) { 550 dev = sd->sd_dev; 551 (*sd->sd_reset)(dev); 552 printf(" %s", dev->dv_xname); 553 } 554 } 555 /* Reload iommu regs */ 556 iommu_reset(&sc->sc_is); 557 } 558 559 /* 560 * Handle an overtemp situation. 561 */ 562 int 563 sbus_overtemp(arg) 564 void *arg; 565 { 566 /* Should try a clean shutdown first */ 567 printf("DANGER: OVERTEMP detected\nShutting down...\n"); 568 delay(20); 569 cpu_reboot(RB_POWERDOWN|RB_HALT, NULL); 570 } 571 572 /* 573 * Get interrupt attributes for an Sbus device. 574 */ 575 int 576 sbus_get_intr(sc, node, ipp, np, slot) 577 struct sbus_softc *sc; 578 int node; 579 struct sbus_intr **ipp; 580 int *np; 581 int slot; 582 { 583 int *ipl; 584 int n, i; 585 char buf[32]; 586 587 /* 588 * The `interrupts' property contains the Sbus interrupt level. 589 */ 590 ipl = NULL; 591 if (getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 592 struct sbus_intr *ip; 593 int pri; 594 595 /* Default to interrupt level 2 -- otherwise unused */ 596 pri = INTLEVENCODE(2); 597 598 /* Change format to an `struct sbus_intr' array */ 599 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 600 if (ip == NULL) 601 return (ENOMEM); 602 603 /* 604 * Now things get ugly. We need to take this value which is 605 * the interrupt vector number and encode the IPL into it 606 * somehow. Luckily, the interrupt vector has lots of free 607 * space and we can easily stuff the IPL in there for a while. 608 */ 609 getpropstringA(node, "device_type", buf); 610 if (!buf[0]) 611 getpropstringA(node, "name", buf); 612 613 for (i = 0; intrmap[i].in_class; i++) 614 if (strcmp(intrmap[i].in_class, buf) == 0) { 615 pri = INTLEVENCODE(intrmap[i].in_lev); 616 break; 617 } 618 619 /* 620 * Sbus card devices need the slot number encoded into 621 * the vector as this is generally not done. 622 */ 623 if ((ipl[0] & INTMAP_OBIO) == 0) 624 pri |= slot << 3; 625 626 for (n = 0; n < *np; n++) { 627 /* 628 * We encode vector and priority into sbi_pri so we 629 * can pass them as a unit. This will go away if 630 * sbus_establish ever takes an sbus_intr instead 631 * of an integer level. 632 * Stuff the real vector in sbi_vec. 633 */ 634 635 ip[n].sbi_pri = pri|ipl[n]; 636 ip[n].sbi_vec = ipl[n]; 637 } 638 free(ipl, M_DEVBUF); 639 *ipp = ip; 640 } 641 642 return (0); 643 } 644 645 646 /* 647 * Install an interrupt handler for an Sbus device. 648 */ 649 void * 650 sbus_intr_establish(t, pri, level, flags, handler, arg) 651 bus_space_tag_t t; 652 int pri; 653 int level; 654 int flags; 655 int (*handler) __P((void *)); 656 void *arg; 657 { 658 struct sbus_softc *sc = t->cookie; 659 struct intrhand *ih; 660 int ipl; 661 long vec = pri; 662 663 ih = (struct intrhand *) 664 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 665 if (ih == NULL) 666 return (NULL); 667 668 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 669 ipl = vec; 670 else if ((vec & SBUS_INTR_COMPAT) != 0) 671 ipl = vec & ~SBUS_INTR_COMPAT; 672 else { 673 /* Decode and remove IPL */ 674 ipl = INTLEV(vec); 675 vec = INTVEC(vec); 676 DPRINTF(SDB_INTR, 677 ("\nsbus: intr[%ld]%lx: %lx\nHunting for IRQ...\n", 678 (long)ipl, (long)vec, (u_long)intrlev[vec])); 679 if ((vec & INTMAP_OBIO) == 0) { 680 /* We're in an SBUS slot */ 681 /* Register the map and clear intr registers */ 682 683 int slot = INTSLOT(pri); 684 685 ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[slot]; 686 ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[vec]; 687 #ifdef DEBUG 688 if (sbus_debug & SDB_INTR) { 689 int64_t intrmap = *ih->ih_map; 690 691 printf("SBUS %lx IRQ as %llx in slot %d\n", 692 (long)vec, (long long)intrmap, slot); 693 printf("\tmap addr %p clr addr %p\n", 694 ih->ih_map, ih->ih_clr); 695 } 696 #endif 697 /* Enable the interrupt */ 698 vec |= INTMAP_V; 699 /* Insert IGN */ 700 vec |= sc->sc_ign; 701 bus_space_write_8(sc->sc_bustag, 702 (bus_space_handle_t)(u_long)ih->ih_map, 0, vec); 703 } else { 704 int64_t *intrptr = &sc->sc_sysio->scsi_int_map; 705 int64_t intrmap = 0; 706 int i; 707 708 /* Insert IGN */ 709 vec |= sc->sc_ign; 710 for (i = 0; &intrptr[i] <= 711 (int64_t *)&sc->sc_sysio->reserved_int_map && 712 INTVEC(intrmap = intrptr[i]) != INTVEC(vec); i++) 713 ; 714 if (INTVEC(intrmap) == INTVEC(vec)) { 715 DPRINTF(SDB_INTR, 716 ("OBIO %lx IRQ as %lx in slot %d\n", 717 vec, (long)intrmap, i)); 718 /* Register the map and clear intr registers */ 719 ih->ih_map = &intrptr[i]; 720 intrptr = (int64_t *)&sc->sc_sysio->scsi_clr_int; 721 ih->ih_clr = &intrptr[i]; 722 /* Enable the interrupt */ 723 intrmap |= INTMAP_V; 724 bus_space_write_8(sc->sc_bustag, 725 (bus_space_handle_t)(u_long)ih->ih_map, 0, 726 (u_long)intrmap); 727 } else 728 panic("IRQ not found!"); 729 } 730 } 731 #ifdef DEBUG 732 if (sbus_debug & SDB_INTR) { long i; for (i = 0; i < 400000000; i++); } 733 #endif 734 735 ih->ih_fun = handler; 736 ih->ih_arg = arg; 737 ih->ih_number = vec; 738 ih->ih_pil = (1<<ipl); 739 intr_establish(ipl, ih); 740 return (ih); 741 } 742 743 static bus_space_tag_t 744 sbus_alloc_bustag(sc) 745 struct sbus_softc *sc; 746 { 747 bus_space_tag_t sbt; 748 749 sbt = (bus_space_tag_t) 750 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 751 if (sbt == NULL) 752 return (NULL); 753 754 bzero(sbt, sizeof *sbt); 755 sbt->cookie = sc; 756 sbt->parent = sc->sc_bustag; 757 sbt->type = SBUS_BUS_SPACE; 758 sbt->sparc_bus_map = _sbus_bus_map; 759 sbt->sparc_bus_mmap = sbus_bus_mmap; 760 sbt->sparc_intr_establish = sbus_intr_establish; 761 return (sbt); 762 } 763 764 765 static bus_dma_tag_t 766 sbus_alloc_dmatag(sc) 767 struct sbus_softc *sc; 768 { 769 bus_dma_tag_t sdt, psdt = sc->sc_dmatag; 770 771 sdt = (bus_dma_tag_t) 772 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 773 if (sdt == NULL) 774 /* Panic? */ 775 return (psdt); 776 777 sdt->_cookie = sc; 778 sdt->_parent = psdt; 779 #define PCOPY(x) sdt->x = psdt->x 780 PCOPY(_dmamap_create); 781 PCOPY(_dmamap_destroy); 782 sdt->_dmamap_load = sbus_dmamap_load; 783 PCOPY(_dmamap_load_mbuf); 784 PCOPY(_dmamap_load_uio); 785 sdt->_dmamap_load_raw = sbus_dmamap_load_raw; 786 sdt->_dmamap_unload = sbus_dmamap_unload; 787 sdt->_dmamap_sync = sbus_dmamap_sync; 788 sdt->_dmamem_alloc = sbus_dmamem_alloc; 789 sdt->_dmamem_free = sbus_dmamem_free; 790 sdt->_dmamem_map = sbus_dmamem_map; 791 sdt->_dmamem_unmap = sbus_dmamem_unmap; 792 PCOPY(_dmamem_mmap); 793 #undef PCOPY 794 sc->sc_dmatag = sdt; 795 return (sdt); 796 } 797 798 int 799 sbus_dmamap_load(tag, map, buf, buflen, p, flags) 800 bus_dma_tag_t tag; 801 bus_dmamap_t map; 802 void *buf; 803 bus_size_t buflen; 804 struct proc *p; 805 int flags; 806 { 807 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 808 809 return (iommu_dvmamap_load(tag, &sc->sc_is, map, buf, buflen, p, flags)); 810 } 811 812 int 813 sbus_dmamap_load_raw(tag, map, segs, nsegs, size, flags) 814 bus_dma_tag_t tag; 815 bus_dmamap_t map; 816 bus_dma_segment_t *segs; 817 int nsegs; 818 bus_size_t size; 819 int flags; 820 { 821 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 822 823 return (iommu_dvmamap_load_raw(tag, &sc->sc_is, map, segs, nsegs, flags, size)); 824 } 825 826 void 827 sbus_dmamap_unload(tag, map) 828 bus_dma_tag_t tag; 829 bus_dmamap_t map; 830 { 831 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 832 833 iommu_dvmamap_unload(tag, &sc->sc_is, map); 834 } 835 836 void 837 sbus_dmamap_sync(tag, map, offset, len, ops) 838 bus_dma_tag_t tag; 839 bus_dmamap_t map; 840 bus_addr_t offset; 841 bus_size_t len; 842 int ops; 843 { 844 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 845 846 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 847 /* Flush the CPU then the IOMMU */ 848 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 849 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 850 } 851 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 852 /* Flush the IOMMU then the CPU */ 853 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 854 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 855 } 856 } 857 858 int 859 sbus_dmamem_alloc(tag, size, alignment, boundary, segs, nsegs, rsegs, flags) 860 bus_dma_tag_t tag; 861 bus_size_t size; 862 bus_size_t alignment; 863 bus_size_t boundary; 864 bus_dma_segment_t *segs; 865 int nsegs; 866 int *rsegs; 867 int flags; 868 { 869 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 870 871 return (iommu_dvmamem_alloc(tag, &sc->sc_is, size, alignment, boundary, 872 segs, nsegs, rsegs, flags)); 873 } 874 875 void 876 sbus_dmamem_free(tag, segs, nsegs) 877 bus_dma_tag_t tag; 878 bus_dma_segment_t *segs; 879 int nsegs; 880 { 881 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 882 883 iommu_dvmamem_free(tag, &sc->sc_is, segs, nsegs); 884 } 885 886 int 887 sbus_dmamem_map(tag, segs, nsegs, size, kvap, flags) 888 bus_dma_tag_t tag; 889 bus_dma_segment_t *segs; 890 int nsegs; 891 size_t size; 892 caddr_t *kvap; 893 int flags; 894 { 895 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 896 897 return (iommu_dvmamem_map(tag, &sc->sc_is, segs, nsegs, size, kvap, flags)); 898 } 899 900 void 901 sbus_dmamem_unmap(tag, kva, size) 902 bus_dma_tag_t tag; 903 caddr_t kva; 904 size_t size; 905 { 906 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 907 908 iommu_dvmamem_unmap(tag, &sc->sc_is, kva, size); 909 } 910
Indexes created Thu Oct 02 14:10:14 GMT 2025