sbus.c revision 1.44
1 /* $NetBSD: sbus.c,v 1.44 2001/09/24 23:49:32 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Copyright (c) 1999 Eduardo Horvath 85 * 86 * Redistribution and use in source and binary forms, with or without 87 * modification, are permitted provided that the following conditions 88 * are met: 89 * 1. Redistributions of source code must retain the above copyright 90 * notice, this list of conditions and the following disclaimer. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 */ 105 106 107 /* 108 * Sbus stuff. 109 */ 110 #include "opt_ddb.h" 111 112 #include <sys/param.h> 113 #include <sys/extent.h> 114 #include <sys/malloc.h> 115 #include <sys/systm.h> 116 #include <sys/device.h> 117 #include <sys/reboot.h> 118 119 #include <machine/bus.h> 120 #include <sparc64/sparc64/cache.h> 121 #include <sparc64/dev/iommureg.h> 122 #include <sparc64/dev/iommuvar.h> 123 #include <sparc64/dev/sbusreg.h> 124 #include <dev/sbus/sbusvar.h> 125 126 #include <uvm/uvm_prot.h> 127 128 #include <machine/autoconf.h> 129 #include <machine/cpu.h> 130 #include <machine/sparc64.h> 131 132 #ifdef DEBUG 133 #define SDB_DVMA 0x1 134 #define SDB_INTR 0x2 135 int sbus_debug = 0; 136 #define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 137 #else 138 #define DPRINTF(l, s) 139 #endif 140 141 void sbusreset __P((int)); 142 143 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 144 static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *)); 145 static int sbus_get_intr __P((struct sbus_softc *, int, 146 struct sbus_intr **, int *, int)); 147 int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 148 int, bus_space_handle_t *)); 149 static int sbus_overtemp __P((void *)); 150 static int _sbus_bus_map __P(( 151 bus_space_tag_t, 152 bus_type_t, 153 bus_addr_t, /*offset*/ 154 bus_size_t, /*size*/ 155 int, /*flags*/ 156 vaddr_t, /*preferred virtual address */ 157 bus_space_handle_t *)); 158 static void *sbus_intr_establish __P(( 159 bus_space_tag_t, 160 int, /*Sbus interrupt level*/ 161 int, /*`device class' priority*/ 162 int, /*flags*/ 163 int (*) __P((void *)), /*handler*/ 164 void *)); /*handler arg*/ 165 166 167 /* autoconfiguration driver */ 168 int sbus_match __P((struct device *, struct cfdata *, void *)); 169 void sbus_attach __P((struct device *, struct device *, void *)); 170 171 172 struct cfattach sbus_ca = { 173 sizeof(struct sbus_softc), sbus_match, sbus_attach 174 }; 175 176 extern struct cfdriver sbus_cd; 177 178 /* 179 * DVMA routines 180 */ 181 int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 182 bus_size_t, struct proc *, int)); 183 void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 184 int sbus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 185 bus_dma_segment_t *, int, bus_size_t, int)); 186 void sbus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 187 bus_size_t, int)); 188 int sbus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 189 bus_size_t alignment, bus_size_t boundary, 190 bus_dma_segment_t *segs, int nsegs, int *rsegs, 191 int flags)); 192 void sbus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 193 int nsegs)); 194 int sbus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 195 int nsegs, size_t size, caddr_t *kvap, int flags)); 196 void sbus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 197 size_t size)); 198 199 /* 200 * Child devices receive the Sbus interrupt level in their attach 201 * arguments. We translate these to CPU IPLs using the following 202 * tables. Note: obio bus interrupt levels are identical to the 203 * processor IPL. 204 * 205 * The second set of tables is used when the Sbus interrupt level 206 * cannot be had from the PROM as an `interrupt' property. We then 207 * fall back on the `intr' property which contains the CPU IPL. 208 */ 209 210 /* Translate Sbus interrupt level to processor IPL */ 211 static int intr_sbus2ipl_4c[] = { 212 0, 1, 2, 3, 5, 7, 8, 9 213 }; 214 static int intr_sbus2ipl_4m[] = { 215 0, 2, 3, 5, 7, 9, 11, 13 216 }; 217 218 /* 219 * This value is or'ed into the attach args' interrupt level cookie 220 * if the interrupt level comes from an `intr' property, i.e. it is 221 * not an Sbus interrupt level. 222 */ 223 #define SBUS_INTR_COMPAT 0x80000000 224 225 226 /* 227 * Print the location of some sbus-attached device (called just 228 * before attaching that device). If `sbus' is not NULL, the 229 * device was found but not configured; print the sbus as well. 230 * Return UNCONF (config_find ignores this if the device was configured). 231 */ 232 int 233 sbus_print(args, busname) 234 void *args; 235 const char *busname; 236 { 237 struct sbus_attach_args *sa = args; 238 int i; 239 240 if (busname) 241 printf("%s at %s", sa->sa_name, busname); 242 printf(" slot %ld offset 0x%lx", (long)sa->sa_slot, 243 (u_long)sa->sa_offset); 244 for (i = 0; i < sa->sa_nintr; i++) { 245 struct sbus_intr *sbi = &sa->sa_intr[i]; 246 247 printf(" vector %lx ipl %ld", 248 (u_long)sbi->sbi_vec, 249 (long)INTLEV(sbi->sbi_pri)); 250 } 251 return (UNCONF); 252 } 253 254 int 255 sbus_match(parent, cf, aux) 256 struct device *parent; 257 struct cfdata *cf; 258 void *aux; 259 { 260 struct mainbus_attach_args *ma = aux; 261 262 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 263 } 264 265 /* 266 * Attach an Sbus. 267 */ 268 void 269 sbus_attach(parent, self, aux) 270 struct device *parent; 271 struct device *self; 272 void *aux; 273 { 274 struct sbus_softc *sc = (struct sbus_softc *)self; 275 struct mainbus_attach_args *ma = aux; 276 struct intrhand *ih; 277 int ipl; 278 char *name; 279 int node = ma->ma_node; 280 281 int node0, error; 282 bus_space_tag_t sbt; 283 struct sbus_attach_args sa; 284 285 sc->sc_bustag = ma->ma_bustag; 286 sc->sc_dmatag = ma->ma_dmatag; 287 sc->sc_sysio = (struct sysioreg*)(u_long)ma->ma_address[0]; /* Use prom mapping for sysio. */ 288 sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */ 289 290 /* Setup interrupt translation tables */ 291 sc->sc_intr2ipl = CPU_ISSUN4C 292 ? intr_sbus2ipl_4c 293 : intr_sbus2ipl_4m; 294 295 /* 296 * Record clock frequency for synchronous SCSI. 297 * IS THIS THE CORRECT DEFAULT?? 298 */ 299 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 300 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 301 302 sbt = sbus_alloc_bustag(sc); 303 sc->sc_dmatag = sbus_alloc_dmatag(sc); 304 305 /* 306 * Get the SBus burst transfer size if burst transfers are supported 307 */ 308 sc->sc_burst = getpropint(node, "burst-sizes", 0); 309 310 /* 311 * Collect address translations from the OBP. 312 */ 313 error = getprop(node, "ranges", sizeof(struct sbus_range), 314 &sc->sc_nrange, (void **)&sc->sc_range); 315 if (error) 316 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 317 318 /* initailise the IOMMU */ 319 320 /* punch in our copies */ 321 sc->sc_is.is_bustag = sc->sc_bustag; 322 sc->sc_is.is_iommu = &sc->sc_sysio->sys_iommu; 323 sc->sc_is.is_sb = &sc->sc_sysio->sys_strbuf; 324 325 /* give us a nice name.. */ 326 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 327 if (name == 0) 328 panic("couldn't malloc iommu name"); 329 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 330 331 iommu_init(name, &sc->sc_is, 0, -1); 332 333 /* Enable the over temp intr */ 334 ih = (struct intrhand *) 335 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 336 ih->ih_map = &sc->sc_sysio->therm_int_map; 337 ih->ih_clr = NULL; /* &sc->sc_sysio->therm_clr_int; */ 338 ih->ih_fun = sbus_overtemp; 339 ipl = 1; 340 ih->ih_pil = (1<<ipl); 341 ih->ih_number = INTVEC(*(ih->ih_map)); 342 intr_establish(ipl, ih); 343 *(ih->ih_map) |= INTMAP_V; 344 345 /* 346 * Note: the stupid SBUS IOMMU ignores the high bits of an address, so a 347 * NULL DMA pointer will be translated by the first page of the IOTSB. 348 * To avoid bugs we'll alloc and ignore the first entry in the IOTSB. 349 */ 350 { 351 u_long dummy; 352 353 if (extent_alloc_subregion(sc->sc_is.is_dvmamap, 354 sc->sc_is.is_dvmabase, sc->sc_is.is_dvmabase + NBPG, NBPG, 355 NBPG, 0, EX_NOWAIT|EX_BOUNDZERO, (u_long *)&dummy) != 0) 356 panic("sbus iommu: can't toss first dvma page"); 357 } 358 359 /* 360 * Loop through ROM children, fixing any relative addresses 361 * and then configuring each device. 362 * `specials' is an array of device names that are treated 363 * specially: 364 */ 365 node0 = firstchild(node); 366 for (node = node0; node; node = nextsibling(node)) { 367 char *name = getpropstring(node, "name"); 368 369 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 370 node, &sa) != 0) { 371 printf("sbus_attach: %s: incomplete\n", name); 372 continue; 373 } 374 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 375 sbus_destroy_attach_args(&sa); 376 } 377 } 378 379 int 380 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 381 struct sbus_softc *sc; 382 bus_space_tag_t bustag; 383 bus_dma_tag_t dmatag; 384 int node; 385 struct sbus_attach_args *sa; 386 { 387 /*struct sbus_reg sbusreg;*/ 388 /*int base;*/ 389 int error; 390 int n; 391 392 bzero(sa, sizeof(struct sbus_attach_args)); 393 error = getprop(node, "name", 1, &n, (void **)&sa->sa_name); 394 if (error != 0) 395 return (error); 396 sa->sa_name[n] = '\0'; 397 398 sa->sa_bustag = bustag; 399 sa->sa_dmatag = dmatag; 400 sa->sa_node = node; 401 sa->sa_frequency = sc->sc_clockfreq; 402 403 error = getprop(node, "reg", sizeof(struct sbus_reg), 404 &sa->sa_nreg, (void **)&sa->sa_reg); 405 if (error != 0) { 406 char buf[32]; 407 if (error != ENOENT || 408 !node_has_property(node, "device_type") || 409 strcmp(getpropstringA(node, "device_type", buf), 410 "hierarchical") != 0) 411 return (error); 412 } 413 for (n = 0; n < sa->sa_nreg; n++) { 414 /* Convert to relative addressing, if necessary */ 415 u_int32_t base = sa->sa_reg[n].sbr_offset; 416 if (SBUS_ABS(base)) { 417 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 418 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 419 } 420 } 421 422 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr, 423 sa->sa_slot)) != 0) 424 return (error); 425 426 error = getprop(node, "address", sizeof(u_int32_t), 427 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 428 if (error != 0 && error != ENOENT) 429 return (error); 430 431 return (0); 432 } 433 434 void 435 sbus_destroy_attach_args(sa) 436 struct sbus_attach_args *sa; 437 { 438 if (sa->sa_name != NULL) 439 free(sa->sa_name, M_DEVBUF); 440 441 if (sa->sa_nreg != 0) 442 free(sa->sa_reg, M_DEVBUF); 443 444 if (sa->sa_intr) 445 free(sa->sa_intr, M_DEVBUF); 446 447 if (sa->sa_promvaddrs) 448 free((void *)sa->sa_promvaddrs, M_DEVBUF); 449 450 bzero(sa, sizeof(struct sbus_attach_args)); /*DEBUG*/ 451 } 452 453 454 int 455 _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp) 456 bus_space_tag_t t; 457 bus_type_t btype; 458 bus_addr_t offset; 459 bus_size_t size; 460 int flags; 461 vaddr_t vaddr; 462 bus_space_handle_t *hp; 463 { 464 struct sbus_softc *sc = t->cookie; 465 int64_t slot = btype; 466 int i; 467 468 for (i = 0; i < sc->sc_nrange; i++) { 469 bus_addr_t paddr; 470 471 if (sc->sc_range[i].cspace != slot) 472 continue; 473 474 /* We've found the connection to the parent bus */ 475 paddr = sc->sc_range[i].poffset + offset; 476 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 477 DPRINTF(SDB_DVMA, 478 ("\n_sbus_bus_map: mapping paddr slot %lx offset %lx poffset %lx paddr %lx\n", 479 (long)slot, (long)offset, (long)sc->sc_range[i].poffset, 480 (long)paddr)); 481 return (bus_space_map2(sc->sc_bustag, 0, paddr, 482 size, flags, vaddr, hp)); 483 } 484 485 return (EINVAL); 486 } 487 488 int 489 sbus_bus_mmap(t, btype, paddr, flags, hp) 490 bus_space_tag_t t; 491 bus_type_t btype; 492 bus_addr_t paddr; 493 int flags; 494 bus_space_handle_t *hp; 495 { 496 bus_addr_t offset = paddr; 497 int slot = btype; 498 struct sbus_softc *sc = t->cookie; 499 int i; 500 501 for (i = 0; i < sc->sc_nrange; i++) { 502 bus_addr_t paddr; 503 504 if (sc->sc_range[i].cspace != slot) 505 continue; 506 507 paddr = sc->sc_range[i].poffset + offset; 508 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 509 *hp = bus_space_mmap(sc->sc_bustag, paddr, 0, 510 VM_PROT_READ|VM_PROT_WRITE, flags); 511 } 512 513 return (*hp == -1 ? -1 : 0); 514 } 515 516 bus_addr_t 517 sbus_bus_addr(t, btype, offset) 518 bus_space_tag_t t; 519 u_int btype; 520 u_int offset; 521 { 522 bus_addr_t baddr; 523 int slot = btype; 524 struct sbus_softc *sc = t->cookie; 525 int i; 526 527 for (i = 0; i < sc->sc_nrange; i++) { 528 if (sc->sc_range[i].cspace != slot) 529 continue; 530 531 baddr = sc->sc_range[i].poffset + offset; 532 baddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 533 } 534 535 return (baddr); 536 } 537 538 539 /* 540 * Each attached device calls sbus_establish after it initializes 541 * its sbusdev portion. 542 */ 543 void 544 sbus_establish(sd, dev) 545 register struct sbusdev *sd; 546 register struct device *dev; 547 { 548 register struct sbus_softc *sc; 549 register struct device *curdev; 550 551 /* 552 * We have to look for the sbus by name, since it is not necessarily 553 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 554 * We don't just use the device structure of the above-attached 555 * sbus, since we might (in the future) support multiple sbus's. 556 */ 557 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 558 if (!curdev || !curdev->dv_xname) 559 panic("sbus_establish: can't find sbus parent for %s", 560 sd->sd_dev->dv_xname 561 ? sd->sd_dev->dv_xname 562 : "<unknown>" ); 563 564 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 565 break; 566 } 567 sc = (struct sbus_softc *) curdev; 568 569 sd->sd_dev = dev; 570 sd->sd_bchain = sc->sc_sbdev; 571 sc->sc_sbdev = sd; 572 } 573 574 /* 575 * Reset the given sbus. 576 */ 577 void 578 sbusreset(sbus) 579 int sbus; 580 { 581 register struct sbusdev *sd; 582 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 583 struct device *dev; 584 585 printf("reset %s:", sc->sc_dev.dv_xname); 586 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 587 if (sd->sd_reset) { 588 dev = sd->sd_dev; 589 (*sd->sd_reset)(dev); 590 printf(" %s", dev->dv_xname); 591 } 592 } 593 /* Reload iommu regs */ 594 iommu_reset(&sc->sc_is); 595 } 596 597 /* 598 * Handle an overtemp situation. 599 * 600 * SPARCs have temperature sensors which generate interrupts 601 * if the machine's temperature exceeds a certain threshold. 602 * This handles the interrupt and powers off the machine. 603 * The same needs to be done to PCI controller drivers. 604 */ 605 int 606 sbus_overtemp(arg) 607 void *arg; 608 { 609 /* Should try a clean shutdown first */ 610 printf("DANGER: OVER TEMPERATURE detected\nShutting down...\n"); 611 delay(20); 612 cpu_reboot(RB_POWERDOWN|RB_HALT, NULL); 613 } 614 615 /* 616 * Get interrupt attributes for an Sbus device. 617 */ 618 int 619 sbus_get_intr(sc, node, ipp, np, slot) 620 struct sbus_softc *sc; 621 int node; 622 struct sbus_intr **ipp; 623 int *np; 624 int slot; 625 { 626 int *ipl; 627 int n, i; 628 char buf[32]; 629 630 /* 631 * The `interrupts' property contains the Sbus interrupt level. 632 */ 633 ipl = NULL; 634 if (getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 635 struct sbus_intr *ip; 636 int pri; 637 638 /* Default to interrupt level 2 -- otherwise unused */ 639 pri = INTLEVENCODE(2); 640 641 /* Change format to an `struct sbus_intr' array */ 642 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 643 if (ip == NULL) 644 return (ENOMEM); 645 646 /* 647 * Now things get ugly. We need to take this value which is 648 * the interrupt vector number and encode the IPL into it 649 * somehow. Luckily, the interrupt vector has lots of free 650 * space and we can easily stuff the IPL in there for a while. 651 */ 652 getpropstringA(node, "device_type", buf); 653 if (!buf[0]) 654 getpropstringA(node, "name", buf); 655 656 for (i = 0; intrmap[i].in_class; i++) 657 if (strcmp(intrmap[i].in_class, buf) == 0) { 658 pri = INTLEVENCODE(intrmap[i].in_lev); 659 break; 660 } 661 662 /* 663 * Sbus card devices need the slot number encoded into 664 * the vector as this is generally not done. 665 */ 666 if ((ipl[0] & INTMAP_OBIO) == 0) 667 pri |= slot << 3; 668 669 for (n = 0; n < *np; n++) { 670 /* 671 * We encode vector and priority into sbi_pri so we 672 * can pass them as a unit. This will go away if 673 * sbus_establish ever takes an sbus_intr instead 674 * of an integer level. 675 * Stuff the real vector in sbi_vec. 676 */ 677 678 ip[n].sbi_pri = pri|ipl[n]; 679 ip[n].sbi_vec = ipl[n]; 680 } 681 free(ipl, M_DEVBUF); 682 *ipp = ip; 683 } 684 685 return (0); 686 } 687 688 689 /* 690 * Install an interrupt handler for an Sbus device. 691 */ 692 void * 693 sbus_intr_establish(t, pri, level, flags, handler, arg) 694 bus_space_tag_t t; 695 int pri; 696 int level; 697 int flags; 698 int (*handler) __P((void *)); 699 void *arg; 700 { 701 struct sbus_softc *sc = t->cookie; 702 struct intrhand *ih; 703 int ipl; 704 long vec = pri; 705 706 ih = (struct intrhand *) 707 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 708 if (ih == NULL) 709 return (NULL); 710 711 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 712 ipl = vec; 713 else if ((vec & SBUS_INTR_COMPAT) != 0) 714 ipl = vec & ~SBUS_INTR_COMPAT; 715 else { 716 /* Decode and remove IPL */ 717 ipl = INTLEV(vec); 718 vec = INTVEC(vec); 719 DPRINTF(SDB_INTR, 720 ("\nsbus: intr[%ld]%lx: %lx\nHunting for IRQ...\n", 721 (long)ipl, (long)vec, (u_long)intrlev[vec])); 722 if ((vec & INTMAP_OBIO) == 0) { 723 /* We're in an SBUS slot */ 724 /* Register the map and clear intr registers */ 725 726 int slot = INTSLOT(pri); 727 728 ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[slot]; 729 ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[vec]; 730 #ifdef DEBUG 731 if (sbus_debug & SDB_INTR) { 732 int64_t intrmap = *ih->ih_map; 733 734 printf("SBUS %lx IRQ as %llx in slot %d\n", 735 (long)vec, (long long)intrmap, slot); 736 printf("\tmap addr %p clr addr %p\n", 737 ih->ih_map, ih->ih_clr); 738 } 739 #endif 740 /* Enable the interrupt */ 741 vec |= INTMAP_V; 742 /* Insert IGN */ 743 vec |= sc->sc_ign; 744 bus_space_write_8(sc->sc_bustag, 745 (bus_space_handle_t)(u_long)ih->ih_map, 0, vec); 746 } else { 747 int64_t *intrptr = &sc->sc_sysio->scsi_int_map; 748 int64_t intrmap = 0; 749 int i; 750 751 /* Insert IGN */ 752 vec |= sc->sc_ign; 753 for (i = 0; &intrptr[i] <= 754 (int64_t *)&sc->sc_sysio->reserved_int_map && 755 INTVEC(intrmap = intrptr[i]) != INTVEC(vec); i++) 756 ; 757 if (INTVEC(intrmap) == INTVEC(vec)) { 758 DPRINTF(SDB_INTR, 759 ("OBIO %lx IRQ as %lx in slot %d\n", 760 vec, (long)intrmap, i)); 761 /* Register the map and clear intr registers */ 762 ih->ih_map = &intrptr[i]; 763 intrptr = (int64_t *)&sc->sc_sysio->scsi_clr_int; 764 ih->ih_clr = &intrptr[i]; 765 /* Enable the interrupt */ 766 intrmap |= INTMAP_V; 767 bus_space_write_8(sc->sc_bustag, 768 (bus_space_handle_t)(u_long)ih->ih_map, 0, 769 (u_long)intrmap); 770 } else 771 panic("IRQ not found!"); 772 } 773 } 774 #ifdef DEBUG 775 if (sbus_debug & SDB_INTR) { long i; for (i = 0; i < 400000000; i++); } 776 #endif 777 778 ih->ih_fun = handler; 779 ih->ih_arg = arg; 780 ih->ih_number = vec; 781 ih->ih_pil = (1<<ipl); 782 intr_establish(ipl, ih); 783 return (ih); 784 } 785 786 static bus_space_tag_t 787 sbus_alloc_bustag(sc) 788 struct sbus_softc *sc; 789 { 790 bus_space_tag_t sbt; 791 792 sbt = (bus_space_tag_t) 793 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 794 if (sbt == NULL) 795 return (NULL); 796 797 bzero(sbt, sizeof *sbt); 798 sbt->cookie = sc; 799 sbt->parent = sc->sc_bustag; 800 sbt->type = SBUS_BUS_SPACE; 801 sbt->sparc_bus_map = _sbus_bus_map; 802 sbt->sparc_bus_mmap = sc->sc_bustag->sparc_bus_mmap; 803 sbt->sparc_intr_establish = sbus_intr_establish; 804 return (sbt); 805 } 806 807 808 static bus_dma_tag_t 809 sbus_alloc_dmatag(sc) 810 struct sbus_softc *sc; 811 { 812 bus_dma_tag_t sdt, psdt = sc->sc_dmatag; 813 814 sdt = (bus_dma_tag_t) 815 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 816 if (sdt == NULL) 817 /* Panic? */ 818 return (psdt); 819 820 sdt->_cookie = sc; 821 sdt->_parent = psdt; 822 #define PCOPY(x) sdt->x = psdt->x 823 PCOPY(_dmamap_create); 824 PCOPY(_dmamap_destroy); 825 sdt->_dmamap_load = sbus_dmamap_load; 826 PCOPY(_dmamap_load_mbuf); 827 PCOPY(_dmamap_load_uio); 828 sdt->_dmamap_load_raw = sbus_dmamap_load_raw; 829 sdt->_dmamap_unload = sbus_dmamap_unload; 830 sdt->_dmamap_sync = sbus_dmamap_sync; 831 sdt->_dmamem_alloc = sbus_dmamem_alloc; 832 sdt->_dmamem_free = sbus_dmamem_free; 833 sdt->_dmamem_map = sbus_dmamem_map; 834 sdt->_dmamem_unmap = sbus_dmamem_unmap; 835 PCOPY(_dmamem_mmap); 836 #undef PCOPY 837 sc->sc_dmatag = sdt; 838 return (sdt); 839 } 840 841 int 842 sbus_dmamap_load(tag, map, buf, buflen, p, flags) 843 bus_dma_tag_t tag; 844 bus_dmamap_t map; 845 void *buf; 846 bus_size_t buflen; 847 struct proc *p; 848 int flags; 849 { 850 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 851 852 return (iommu_dvmamap_load(tag, &sc->sc_is, map, buf, buflen, p, flags)); 853 } 854 855 int 856 sbus_dmamap_load_raw(tag, map, segs, nsegs, size, flags) 857 bus_dma_tag_t tag; 858 bus_dmamap_t map; 859 bus_dma_segment_t *segs; 860 int nsegs; 861 bus_size_t size; 862 int flags; 863 { 864 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 865 866 return (iommu_dvmamap_load_raw(tag, &sc->sc_is, map, segs, nsegs, flags, size)); 867 } 868 869 void 870 sbus_dmamap_unload(tag, map) 871 bus_dma_tag_t tag; 872 bus_dmamap_t map; 873 { 874 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 875 876 iommu_dvmamap_unload(tag, &sc->sc_is, map); 877 } 878 879 void 880 sbus_dmamap_sync(tag, map, offset, len, ops) 881 bus_dma_tag_t tag; 882 bus_dmamap_t map; 883 bus_addr_t offset; 884 bus_size_t len; 885 int ops; 886 { 887 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 888 889 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 890 /* Flush the CPU then the IOMMU */ 891 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 892 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 893 } 894 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 895 /* Flush the IOMMU then the CPU */ 896 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 897 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 898 } 899 } 900 901 int 902 sbus_dmamem_alloc(tag, size, alignment, boundary, segs, nsegs, rsegs, flags) 903 bus_dma_tag_t tag; 904 bus_size_t size; 905 bus_size_t alignment; 906 bus_size_t boundary; 907 bus_dma_segment_t *segs; 908 int nsegs; 909 int *rsegs; 910 int flags; 911 { 912 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 913 914 return (iommu_dvmamem_alloc(tag, &sc->sc_is, size, alignment, boundary, 915 segs, nsegs, rsegs, flags)); 916 } 917 918 void 919 sbus_dmamem_free(tag, segs, nsegs) 920 bus_dma_tag_t tag; 921 bus_dma_segment_t *segs; 922 int nsegs; 923 { 924 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 925 926 iommu_dvmamem_free(tag, &sc->sc_is, segs, nsegs); 927 } 928 929 int 930 sbus_dmamem_map(tag, segs, nsegs, size, kvap, flags) 931 bus_dma_tag_t tag; 932 bus_dma_segment_t *segs; 933 int nsegs; 934 size_t size; 935 caddr_t *kvap; 936 int flags; 937 { 938 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 939 940 return (iommu_dvmamem_map(tag, &sc->sc_is, segs, nsegs, size, kvap, flags)); 941 } 942 943 void 944 sbus_dmamem_unmap(tag, kva, size) 945 bus_dma_tag_t tag; 946 caddr_t kva; 947 size_t size; 948 { 949 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 950 951 iommu_dvmamem_unmap(tag, &sc->sc_is, kva, size); 952 } 953
Indexes created Thu Oct 02 14:10:14 GMT 2025