sbus.c revision 1.47
1 /* $NetBSD: sbus.c,v 1.47 2002/03/14 20:51:35 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Copyright (c) 1999 Eduardo Horvath 85 * 86 * Redistribution and use in source and binary forms, with or without 87 * modification, are permitted provided that the following conditions 88 * are met: 89 * 1. Redistributions of source code must retain the above copyright 90 * notice, this list of conditions and the following disclaimer. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 */ 105 106 107 /* 108 * Sbus stuff. 109 */ 110 #include "opt_ddb.h" 111 112 #include <sys/param.h> 113 #include <sys/extent.h> 114 #include <sys/malloc.h> 115 #include <sys/systm.h> 116 #include <sys/device.h> 117 #include <sys/reboot.h> 118 119 #include <machine/bus.h> 120 #include <sparc64/sparc64/cache.h> 121 #include <sparc64/dev/iommureg.h> 122 #include <sparc64/dev/iommuvar.h> 123 #include <sparc64/dev/sbusreg.h> 124 #include <dev/sbus/sbusvar.h> 125 126 #include <uvm/uvm_prot.h> 127 128 #include <machine/autoconf.h> 129 #include <machine/cpu.h> 130 #include <machine/sparc64.h> 131 132 #ifdef DEBUG 133 #define SDB_DVMA 0x1 134 #define SDB_INTR 0x2 135 int sbus_debug = 0; 136 #define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 137 #else 138 #define DPRINTF(l, s) 139 #endif 140 141 void sbusreset __P((int)); 142 143 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 144 static bus_dma_tag_t sbus_alloc_dmatag __P((struct sbus_softc *)); 145 static int sbus_get_intr __P((struct sbus_softc *, int, 146 struct sbus_intr **, int *, int)); 147 int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 148 int, bus_space_handle_t *)); 149 static int sbus_overtemp __P((void *)); 150 static int _sbus_bus_map __P(( 151 bus_space_tag_t, 152 bus_addr_t, /*offset*/ 153 bus_size_t, /*size*/ 154 int, /*flags*/ 155 vaddr_t, /* XXX unused -- compat w/sparc */ 156 bus_space_handle_t *)); 157 static void *sbus_intr_establish __P(( 158 bus_space_tag_t, 159 int, /*Sbus interrupt level*/ 160 int, /*`device class' priority*/ 161 int, /*flags*/ 162 int (*) __P((void *)), /*handler*/ 163 void *)); /*handler arg*/ 164 165 166 /* autoconfiguration driver */ 167 int sbus_match __P((struct device *, struct cfdata *, void *)); 168 void sbus_attach __P((struct device *, struct device *, void *)); 169 170 171 struct cfattach sbus_ca = { 172 sizeof(struct sbus_softc), sbus_match, sbus_attach 173 }; 174 175 extern struct cfdriver sbus_cd; 176 177 /* 178 * DVMA routines 179 */ 180 int sbus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 181 bus_size_t, struct proc *, int)); 182 void sbus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 183 int sbus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 184 bus_dma_segment_t *, int, bus_size_t, int)); 185 void sbus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 186 bus_size_t, int)); 187 int sbus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 188 bus_size_t alignment, bus_size_t boundary, 189 bus_dma_segment_t *segs, int nsegs, int *rsegs, 190 int flags)); 191 void sbus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 192 int nsegs)); 193 int sbus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 194 int nsegs, size_t size, caddr_t *kvap, int flags)); 195 void sbus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 196 size_t size)); 197 198 /* 199 * Child devices receive the Sbus interrupt level in their attach 200 * arguments. We translate these to CPU IPLs using the following 201 * tables. Note: obio bus interrupt levels are identical to the 202 * processor IPL. 203 * 204 * The second set of tables is used when the Sbus interrupt level 205 * cannot be had from the PROM as an `interrupt' property. We then 206 * fall back on the `intr' property which contains the CPU IPL. 207 */ 208 209 /* Translate Sbus interrupt level to processor IPL */ 210 static int intr_sbus2ipl_4c[] = { 211 0, 1, 2, 3, 5, 7, 8, 9 212 }; 213 static int intr_sbus2ipl_4m[] = { 214 0, 2, 3, 5, 7, 9, 11, 13 215 }; 216 217 /* 218 * This value is or'ed into the attach args' interrupt level cookie 219 * if the interrupt level comes from an `intr' property, i.e. it is 220 * not an Sbus interrupt level. 221 */ 222 #define SBUS_INTR_COMPAT 0x80000000 223 224 225 /* 226 * Print the location of some sbus-attached device (called just 227 * before attaching that device). If `sbus' is not NULL, the 228 * device was found but not configured; print the sbus as well. 229 * Return UNCONF (config_find ignores this if the device was configured). 230 */ 231 int 232 sbus_print(args, busname) 233 void *args; 234 const char *busname; 235 { 236 struct sbus_attach_args *sa = args; 237 int i; 238 239 if (busname) 240 printf("%s at %s", sa->sa_name, busname); 241 printf(" slot %ld offset 0x%lx", (long)sa->sa_slot, 242 (u_long)sa->sa_offset); 243 for (i = 0; i < sa->sa_nintr; i++) { 244 struct sbus_intr *sbi = &sa->sa_intr[i]; 245 246 printf(" vector %lx ipl %ld", 247 (u_long)sbi->sbi_vec, 248 (long)INTLEV(sbi->sbi_pri)); 249 } 250 return (UNCONF); 251 } 252 253 int 254 sbus_match(parent, cf, aux) 255 struct device *parent; 256 struct cfdata *cf; 257 void *aux; 258 { 259 struct mainbus_attach_args *ma = aux; 260 261 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 262 } 263 264 /* 265 * Attach an Sbus. 266 */ 267 void 268 sbus_attach(parent, self, aux) 269 struct device *parent; 270 struct device *self; 271 void *aux; 272 { 273 struct sbus_softc *sc = (struct sbus_softc *)self; 274 struct mainbus_attach_args *ma = aux; 275 struct intrhand *ih; 276 int ipl; 277 char *name; 278 int node = ma->ma_node; 279 280 int node0, error; 281 bus_space_tag_t sbt; 282 struct sbus_attach_args sa; 283 284 sc->sc_bustag = ma->ma_bustag; 285 sc->sc_dmatag = ma->ma_dmatag; 286 sc->sc_sysio = (struct sysioreg*)(u_long)ma->ma_address[0]; /* Use prom mapping for sysio. */ 287 sc->sc_ign = ma->ma_interrupts[0] & INTMAP_IGN; /* Find interrupt group no */ 288 289 /* Setup interrupt translation tables */ 290 sc->sc_intr2ipl = CPU_ISSUN4C 291 ? intr_sbus2ipl_4c 292 : intr_sbus2ipl_4m; 293 294 /* 295 * Record clock frequency for synchronous SCSI. 296 * IS THIS THE CORRECT DEFAULT?? 297 */ 298 sc->sc_clockfreq = PROM_getpropint(node, "clock-frequency", 25*1000*1000); 299 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 300 301 sbt = sbus_alloc_bustag(sc); 302 sc->sc_dmatag = sbus_alloc_dmatag(sc); 303 304 /* 305 * Get the SBus burst transfer size if burst transfers are supported 306 */ 307 sc->sc_burst = PROM_getpropint(node, "burst-sizes", 0); 308 309 /* 310 * Collect address translations from the OBP. 311 */ 312 error = PROM_getprop(node, "ranges", sizeof(struct sbus_range), 313 &sc->sc_nrange, (void **)&sc->sc_range); 314 if (error) 315 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 316 317 /* initailise the IOMMU */ 318 319 /* punch in our copies */ 320 sc->sc_is.is_bustag = sc->sc_bustag; 321 sc->sc_is.is_iommu = &sc->sc_sysio->sys_iommu; 322 sc->sc_is.is_sb[0] = &sc->sc_sysio->sys_strbuf; 323 sc->sc_is.is_sb[1] = NULL; 324 325 /* give us a nice name.. */ 326 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 327 if (name == 0) 328 panic("couldn't malloc iommu name"); 329 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 330 331 iommu_init(name, &sc->sc_is, 0, -1); 332 333 /* Enable the over temp intr */ 334 ih = (struct intrhand *) 335 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 336 ih->ih_map = &sc->sc_sysio->therm_int_map; 337 ih->ih_clr = NULL; /* &sc->sc_sysio->therm_clr_int; */ 338 ih->ih_fun = sbus_overtemp; 339 ipl = 1; 340 ih->ih_pil = (1<<ipl); 341 ih->ih_number = INTVEC(*(ih->ih_map)); 342 intr_establish(ipl, ih); 343 *(ih->ih_map) |= INTMAP_V; 344 345 /* 346 * Note: the stupid SBUS IOMMU ignores the high bits of an address, so a 347 * NULL DMA pointer will be translated by the first page of the IOTSB. 348 * To avoid bugs we'll alloc and ignore the first entry in the IOTSB. 349 */ 350 { 351 u_long dummy; 352 353 if (extent_alloc_subregion(sc->sc_is.is_dvmamap, 354 sc->sc_is.is_dvmabase, sc->sc_is.is_dvmabase + NBPG, NBPG, 355 NBPG, 0, EX_NOWAIT|EX_BOUNDZERO, (u_long *)&dummy) != 0) 356 panic("sbus iommu: can't toss first dvma page"); 357 } 358 359 /* 360 * Loop through ROM children, fixing any relative addresses 361 * and then configuring each device. 362 * `specials' is an array of device names that are treated 363 * specially: 364 */ 365 node0 = firstchild(node); 366 for (node = node0; node; node = nextsibling(node)) { 367 char *name = PROM_getpropstring(node, "name"); 368 369 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 370 node, &sa) != 0) { 371 printf("sbus_attach: %s: incomplete\n", name); 372 continue; 373 } 374 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 375 sbus_destroy_attach_args(&sa); 376 } 377 } 378 379 int 380 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 381 struct sbus_softc *sc; 382 bus_space_tag_t bustag; 383 bus_dma_tag_t dmatag; 384 int node; 385 struct sbus_attach_args *sa; 386 { 387 /*struct sbus_reg sbusreg;*/ 388 /*int base;*/ 389 int error; 390 int n; 391 392 bzero(sa, sizeof(struct sbus_attach_args)); 393 error = PROM_getprop(node, "name", 1, &n, (void **)&sa->sa_name); 394 if (error != 0) 395 return (error); 396 sa->sa_name[n] = '\0'; 397 398 sa->sa_bustag = bustag; 399 sa->sa_dmatag = dmatag; 400 sa->sa_node = node; 401 sa->sa_frequency = sc->sc_clockfreq; 402 403 error = PROM_getprop(node, "reg", sizeof(struct sbus_reg), 404 &sa->sa_nreg, (void **)&sa->sa_reg); 405 if (error != 0) { 406 char buf[32]; 407 if (error != ENOENT || 408 !node_has_property(node, "device_type") || 409 strcmp(PROM_getpropstringA(node, "device_type", buf), 410 "hierarchical") != 0) 411 return (error); 412 } 413 for (n = 0; n < sa->sa_nreg; n++) { 414 /* Convert to relative addressing, if necessary */ 415 u_int32_t base = sa->sa_reg[n].sbr_offset; 416 if (SBUS_ABS(base)) { 417 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 418 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 419 } 420 } 421 422 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr, 423 sa->sa_slot)) != 0) 424 return (error); 425 426 error = PROM_getprop(node, "address", sizeof(u_int32_t), 427 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 428 if (error != 0 && error != ENOENT) 429 return (error); 430 431 return (0); 432 } 433 434 void 435 sbus_destroy_attach_args(sa) 436 struct sbus_attach_args *sa; 437 { 438 if (sa->sa_name != NULL) 439 free(sa->sa_name, M_DEVBUF); 440 441 if (sa->sa_nreg != 0) 442 free(sa->sa_reg, M_DEVBUF); 443 444 if (sa->sa_intr) 445 free(sa->sa_intr, M_DEVBUF); 446 447 if (sa->sa_promvaddrs) 448 free((void *)sa->sa_promvaddrs, M_DEVBUF); 449 450 bzero(sa, sizeof(struct sbus_attach_args)); /*DEBUG*/ 451 } 452 453 454 int 455 _sbus_bus_map(t, addr, size, flags, v, hp) 456 bus_space_tag_t t; 457 bus_addr_t addr; 458 bus_size_t size; 459 int flags; 460 vaddr_t v; 461 bus_space_handle_t *hp; 462 { 463 struct sbus_softc *sc = t->cookie; 464 int64_t slot = BUS_ADDR_IOSPACE(addr); 465 int64_t offset = BUS_ADDR_PADDR(addr); 466 int i; 467 468 for (i = 0; i < sc->sc_nrange; i++) { 469 bus_addr_t paddr; 470 471 if (sc->sc_range[i].cspace != slot) 472 continue; 473 474 /* We've found the connection to the parent bus */ 475 paddr = sc->sc_range[i].poffset + offset; 476 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 477 DPRINTF(SDB_DVMA, 478 ("\n_sbus_bus_map: mapping paddr slot %lx offset %lx poffset %lx paddr %lx\n", 479 (long)slot, (long)offset, (long)sc->sc_range[i].poffset, 480 (long)paddr)); 481 return (bus_space_map(sc->sc_bustag, paddr, size, flags, hp)); 482 } 483 484 return (EINVAL); 485 } 486 487 int 488 sbus_bus_mmap(t, btype, paddr, flags, hp) 489 bus_space_tag_t t; 490 bus_type_t btype; 491 bus_addr_t paddr; 492 int flags; 493 bus_space_handle_t *hp; 494 { 495 bus_addr_t offset = paddr; 496 int slot = btype; 497 struct sbus_softc *sc = t->cookie; 498 int i; 499 500 for (i = 0; i < sc->sc_nrange; i++) { 501 bus_addr_t paddr; 502 503 if (sc->sc_range[i].cspace != slot) 504 continue; 505 506 paddr = sc->sc_range[i].poffset + offset; 507 paddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 508 *hp = bus_space_mmap(sc->sc_bustag, paddr, 0, 509 VM_PROT_READ|VM_PROT_WRITE, flags); 510 } 511 512 return (*hp == -1 ? -1 : 0); 513 } 514 515 bus_addr_t 516 sbus_bus_addr(t, btype, offset) 517 bus_space_tag_t t; 518 u_int btype; 519 u_int offset; 520 { 521 bus_addr_t baddr; 522 int slot = btype; 523 struct sbus_softc *sc = t->cookie; 524 int i; 525 526 for (i = 0; i < sc->sc_nrange; i++) { 527 if (sc->sc_range[i].cspace != slot) 528 continue; 529 530 baddr = sc->sc_range[i].poffset + offset; 531 baddr |= ((bus_addr_t)sc->sc_range[i].pspace<<32); 532 } 533 534 return (baddr); 535 } 536 537 538 /* 539 * Each attached device calls sbus_establish after it initializes 540 * its sbusdev portion. 541 */ 542 void 543 sbus_establish(sd, dev) 544 register struct sbusdev *sd; 545 register struct device *dev; 546 { 547 register struct sbus_softc *sc; 548 register struct device *curdev; 549 550 /* 551 * We have to look for the sbus by name, since it is not necessarily 552 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 553 * We don't just use the device structure of the above-attached 554 * sbus, since we might (in the future) support multiple sbus's. 555 */ 556 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 557 if (!curdev || !curdev->dv_xname) 558 panic("sbus_establish: can't find sbus parent for %s", 559 sd->sd_dev->dv_xname 560 ? sd->sd_dev->dv_xname 561 : "<unknown>" ); 562 563 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 564 break; 565 } 566 sc = (struct sbus_softc *) curdev; 567 568 sd->sd_dev = dev; 569 sd->sd_bchain = sc->sc_sbdev; 570 sc->sc_sbdev = sd; 571 } 572 573 /* 574 * Reset the given sbus. 575 */ 576 void 577 sbusreset(sbus) 578 int sbus; 579 { 580 register struct sbusdev *sd; 581 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 582 struct device *dev; 583 584 printf("reset %s:", sc->sc_dev.dv_xname); 585 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 586 if (sd->sd_reset) { 587 dev = sd->sd_dev; 588 (*sd->sd_reset)(dev); 589 printf(" %s", dev->dv_xname); 590 } 591 } 592 /* Reload iommu regs */ 593 iommu_reset(&sc->sc_is); 594 } 595 596 /* 597 * Handle an overtemp situation. 598 * 599 * SPARCs have temperature sensors which generate interrupts 600 * if the machine's temperature exceeds a certain threshold. 601 * This handles the interrupt and powers off the machine. 602 * The same needs to be done to PCI controller drivers. 603 */ 604 int 605 sbus_overtemp(arg) 606 void *arg; 607 { 608 /* Should try a clean shutdown first */ 609 printf("DANGER: OVER TEMPERATURE detected\nShutting down...\n"); 610 delay(20); 611 cpu_reboot(RB_POWERDOWN|RB_HALT, NULL); 612 } 613 614 /* 615 * Get interrupt attributes for an Sbus device. 616 */ 617 int 618 sbus_get_intr(sc, node, ipp, np, slot) 619 struct sbus_softc *sc; 620 int node; 621 struct sbus_intr **ipp; 622 int *np; 623 int slot; 624 { 625 int *ipl; 626 int n, i; 627 char buf[32]; 628 629 /* 630 * The `interrupts' property contains the Sbus interrupt level. 631 */ 632 ipl = NULL; 633 if (PROM_getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 634 struct sbus_intr *ip; 635 int pri; 636 637 /* Default to interrupt level 2 -- otherwise unused */ 638 pri = INTLEVENCODE(2); 639 640 /* Change format to an `struct sbus_intr' array */ 641 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 642 if (ip == NULL) 643 return (ENOMEM); 644 645 /* 646 * Now things get ugly. We need to take this value which is 647 * the interrupt vector number and encode the IPL into it 648 * somehow. Luckily, the interrupt vector has lots of free 649 * space and we can easily stuff the IPL in there for a while. 650 */ 651 PROM_getpropstringA(node, "device_type", buf); 652 if (!buf[0]) 653 PROM_getpropstringA(node, "name", buf); 654 655 for (i = 0; intrmap[i].in_class; i++) 656 if (strcmp(intrmap[i].in_class, buf) == 0) { 657 pri = INTLEVENCODE(intrmap[i].in_lev); 658 break; 659 } 660 661 /* 662 * Sbus card devices need the slot number encoded into 663 * the vector as this is generally not done. 664 */ 665 if ((ipl[0] & INTMAP_OBIO) == 0) 666 pri |= slot << 3; 667 668 for (n = 0; n < *np; n++) { 669 /* 670 * We encode vector and priority into sbi_pri so we 671 * can pass them as a unit. This will go away if 672 * sbus_establish ever takes an sbus_intr instead 673 * of an integer level. 674 * Stuff the real vector in sbi_vec. 675 */ 676 677 ip[n].sbi_pri = pri|ipl[n]; 678 ip[n].sbi_vec = ipl[n]; 679 } 680 free(ipl, M_DEVBUF); 681 *ipp = ip; 682 } 683 684 return (0); 685 } 686 687 688 /* 689 * Install an interrupt handler for an Sbus device. 690 */ 691 void * 692 sbus_intr_establish(t, pri, level, flags, handler, arg) 693 bus_space_tag_t t; 694 int pri; 695 int level; 696 int flags; 697 int (*handler) __P((void *)); 698 void *arg; 699 { 700 struct sbus_softc *sc = t->cookie; 701 struct intrhand *ih; 702 int ipl; 703 long vec = pri; 704 705 ih = (struct intrhand *) 706 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 707 if (ih == NULL) 708 return (NULL); 709 710 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 711 ipl = vec; 712 else if ((vec & SBUS_INTR_COMPAT) != 0) 713 ipl = vec & ~SBUS_INTR_COMPAT; 714 else { 715 /* Decode and remove IPL */ 716 ipl = INTLEV(vec); 717 vec = INTVEC(vec); 718 DPRINTF(SDB_INTR, 719 ("\nsbus: intr[%ld]%lx: %lx\nHunting for IRQ...\n", 720 (long)ipl, (long)vec, (u_long)intrlev[vec])); 721 if ((vec & INTMAP_OBIO) == 0) { 722 /* We're in an SBUS slot */ 723 /* Register the map and clear intr registers */ 724 725 int slot = INTSLOT(pri); 726 727 ih->ih_map = &(&sc->sc_sysio->sbus_slot0_int)[slot]; 728 ih->ih_clr = &sc->sc_sysio->sbus0_clr_int[vec]; 729 #ifdef DEBUG 730 if (sbus_debug & SDB_INTR) { 731 int64_t intrmap = *ih->ih_map; 732 733 printf("SBUS %lx IRQ as %llx in slot %d\n", 734 (long)vec, (long long)intrmap, slot); 735 printf("\tmap addr %p clr addr %p\n", 736 ih->ih_map, ih->ih_clr); 737 } 738 #endif 739 /* Enable the interrupt */ 740 vec |= INTMAP_V; 741 /* Insert IGN */ 742 vec |= sc->sc_ign; 743 bus_space_write_8(sc->sc_bustag, 744 (bus_space_handle_t)(u_long)ih->ih_map, 0, vec); 745 } else { 746 int64_t *intrptr = &sc->sc_sysio->scsi_int_map; 747 int64_t intrmap = 0; 748 int i; 749 750 /* Insert IGN */ 751 vec |= sc->sc_ign; 752 for (i = 0; &intrptr[i] <= 753 (int64_t *)&sc->sc_sysio->reserved_int_map && 754 INTVEC(intrmap = intrptr[i]) != INTVEC(vec); i++) 755 ; 756 if (INTVEC(intrmap) == INTVEC(vec)) { 757 DPRINTF(SDB_INTR, 758 ("OBIO %lx IRQ as %lx in slot %d\n", 759 vec, (long)intrmap, i)); 760 /* Register the map and clear intr registers */ 761 ih->ih_map = &intrptr[i]; 762 intrptr = (int64_t *)&sc->sc_sysio->scsi_clr_int; 763 ih->ih_clr = &intrptr[i]; 764 /* Enable the interrupt */ 765 intrmap |= INTMAP_V; 766 bus_space_write_8(sc->sc_bustag, 767 (bus_space_handle_t)(u_long)ih->ih_map, 0, 768 (u_long)intrmap); 769 } else 770 panic("IRQ not found!"); 771 } 772 } 773 #ifdef DEBUG 774 if (sbus_debug & SDB_INTR) { long i; for (i = 0; i < 400000000; i++); } 775 #endif 776 777 ih->ih_fun = handler; 778 ih->ih_arg = arg; 779 ih->ih_number = vec; 780 ih->ih_pil = (1<<ipl); 781 intr_establish(ipl, ih); 782 return (ih); 783 } 784 785 static bus_space_tag_t 786 sbus_alloc_bustag(sc) 787 struct sbus_softc *sc; 788 { 789 bus_space_tag_t sbt; 790 791 sbt = (bus_space_tag_t) 792 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 793 if (sbt == NULL) 794 return (NULL); 795 796 bzero(sbt, sizeof *sbt); 797 sbt->cookie = sc; 798 sbt->parent = sc->sc_bustag; 799 sbt->type = SBUS_BUS_SPACE; 800 sbt->sparc_bus_map = _sbus_bus_map; 801 sbt->sparc_bus_mmap = sc->sc_bustag->sparc_bus_mmap; 802 sbt->sparc_intr_establish = sbus_intr_establish; 803 return (sbt); 804 } 805 806 807 static bus_dma_tag_t 808 sbus_alloc_dmatag(sc) 809 struct sbus_softc *sc; 810 { 811 bus_dma_tag_t sdt, psdt = sc->sc_dmatag; 812 813 sdt = (bus_dma_tag_t) 814 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 815 if (sdt == NULL) 816 /* Panic? */ 817 return (psdt); 818 819 sdt->_cookie = sc; 820 sdt->_parent = psdt; 821 #define PCOPY(x) sdt->x = psdt->x 822 PCOPY(_dmamap_create); 823 PCOPY(_dmamap_destroy); 824 sdt->_dmamap_load = sbus_dmamap_load; 825 PCOPY(_dmamap_load_mbuf); 826 PCOPY(_dmamap_load_uio); 827 sdt->_dmamap_load_raw = sbus_dmamap_load_raw; 828 sdt->_dmamap_unload = sbus_dmamap_unload; 829 sdt->_dmamap_sync = sbus_dmamap_sync; 830 sdt->_dmamem_alloc = sbus_dmamem_alloc; 831 sdt->_dmamem_free = sbus_dmamem_free; 832 sdt->_dmamem_map = sbus_dmamem_map; 833 sdt->_dmamem_unmap = sbus_dmamem_unmap; 834 PCOPY(_dmamem_mmap); 835 #undef PCOPY 836 sc->sc_dmatag = sdt; 837 return (sdt); 838 } 839 840 int 841 sbus_dmamap_load(tag, map, buf, buflen, p, flags) 842 bus_dma_tag_t tag; 843 bus_dmamap_t map; 844 void *buf; 845 bus_size_t buflen; 846 struct proc *p; 847 int flags; 848 { 849 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 850 851 return (iommu_dvmamap_load(tag, &sc->sc_is, map, buf, buflen, p, flags)); 852 } 853 854 int 855 sbus_dmamap_load_raw(tag, map, segs, nsegs, size, flags) 856 bus_dma_tag_t tag; 857 bus_dmamap_t map; 858 bus_dma_segment_t *segs; 859 int nsegs; 860 bus_size_t size; 861 int flags; 862 { 863 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 864 865 return (iommu_dvmamap_load_raw(tag, &sc->sc_is, map, segs, nsegs, flags, size)); 866 } 867 868 void 869 sbus_dmamap_unload(tag, map) 870 bus_dma_tag_t tag; 871 bus_dmamap_t map; 872 { 873 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 874 875 iommu_dvmamap_unload(tag, &sc->sc_is, map); 876 } 877 878 void 879 sbus_dmamap_sync(tag, map, offset, len, ops) 880 bus_dma_tag_t tag; 881 bus_dmamap_t map; 882 bus_addr_t offset; 883 bus_size_t len; 884 int ops; 885 { 886 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 887 888 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 889 /* Flush the CPU then the IOMMU */ 890 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 891 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 892 } 893 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 894 /* Flush the IOMMU then the CPU */ 895 iommu_dvmamap_sync(tag, &sc->sc_is, map, offset, len, ops); 896 bus_dmamap_sync(tag->_parent, map, offset, len, ops); 897 } 898 } 899 900 int 901 sbus_dmamem_alloc(tag, size, alignment, boundary, segs, nsegs, rsegs, flags) 902 bus_dma_tag_t tag; 903 bus_size_t size; 904 bus_size_t alignment; 905 bus_size_t boundary; 906 bus_dma_segment_t *segs; 907 int nsegs; 908 int *rsegs; 909 int flags; 910 { 911 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 912 913 return (iommu_dvmamem_alloc(tag, &sc->sc_is, size, alignment, boundary, 914 segs, nsegs, rsegs, flags)); 915 } 916 917 void 918 sbus_dmamem_free(tag, segs, nsegs) 919 bus_dma_tag_t tag; 920 bus_dma_segment_t *segs; 921 int nsegs; 922 { 923 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 924 925 iommu_dvmamem_free(tag, &sc->sc_is, segs, nsegs); 926 } 927 928 int 929 sbus_dmamem_map(tag, segs, nsegs, size, kvap, flags) 930 bus_dma_tag_t tag; 931 bus_dma_segment_t *segs; 932 int nsegs; 933 size_t size; 934 caddr_t *kvap; 935 int flags; 936 { 937 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 938 939 return (iommu_dvmamem_map(tag, &sc->sc_is, segs, nsegs, size, kvap, flags)); 940 } 941 942 void 943 sbus_dmamem_unmap(tag, kva, size) 944 bus_dma_tag_t tag; 945 caddr_t kva; 946 size_t size; 947 { 948 struct sbus_softc *sc = (struct sbus_softc *)tag->_cookie; 949 950 iommu_dvmamem_unmap(tag, &sc->sc_is, kva, size); 951 } 952
Indexes created Thu Oct 02 14:10:14 GMT 2025