sbusreg.h revision 1.1
1 /* $NetBSD: sbusreg.h,v 1.1 1998/06/20 04:58:51 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Sun-4c S-bus definitions. (Should be made generic!) 49 * 50 * Sbus slot 0 is not a separate slot; it talks to the onboard I/O devices. 51 * It is, however, addressed just like any `real' Sbus. 52 * 53 * Sbus device addresses are obtained from the FORTH PROMs. They come 54 * in `absolute' and `relative' address flavors, so we have to handle both. 55 * Relative addresses do *not* include the slot number. 56 */ 57 #define SBUS_BASE 0xf8000000 58 #define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off)) 59 #define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE) 60 #define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25) 61 #define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff) 62 63 /* 64 * Sun4u S-bus definitions. Here's where we deal w/the machine 65 * dependencies of sysio. 66 * 67 * SYSIO implements or is the interface to several things: 68 * 69 * o The SBUS interface itself 70 * o The IOMMU 71 * o The DVMA units 72 * o The interrupt controller 73 * o The counter/timers 74 * 75 * Since it has registers to control lots of different things 76 * as well as several on-board SBUS devices and external SBUS 77 * slots scattered throughout its address space, it's a pain. 78 * 79 * One good point, however, is that all registers are 64-bit. 80 */ 81 82 struct sysioreg { 83 struct upareg { 84 u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */ 85 u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */ 86 } sys_upa; 87 88 u_int64_t sys_csr; /* SYSIO control/status register */ /* 1fe.0000.0010 */ 89 u_int64_t pad0; 90 u_int64_t sys_ecccr; /* ECC control register */ /* 1fe.0000.0020 */ 91 u_int64_t reserved; /* 1fe.0000.0028 */ 92 u_int64_t sys_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */ 93 u_int64_t sys_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */ 94 u_int64_t sys_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */ 95 u_int64_t sys_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */ 96 97 u_int64_t pad1[22]; 98 99 struct perfmon { 100 u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */ 101 u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */ 102 } sys_pm; 103 104 u_int64_t pad2[990]; 105 106 struct sbusreg { 107 u_int64_t sbus_cr; /* SBUS Control Register */ /* 1fe.0000.2000 */ 108 u_int64_t reserved; /* 1fe.0000.2008 */ 109 u_int64_t sbus_afsr; /* SBUS AFSR */ /* 1fe.0000.2010 */ 110 u_int64_t sbus_afar; /* SBUS AFAR */ /* 1fe.0000.2018 */ 111 u_int64_t sbus_config0; /* SBUS Slot 0 config register */ /* 1fe.0000.2020 */ 112 u_int64_t sbus_config1; /* SBUS Slot 1 config register */ /* 1fe.0000.2028 */ 113 u_int64_t sbus_config2; /* SBUS Slot 2 config register */ /* 1fe.0000.2030 */ 114 u_int64_t sbus_config3; /* SBUS Slot 3 config register */ /* 1fe.0000.2038 */ 115 u_int64_t sbus_config13; /* Slot 13 config register <audio> */ /* 1fe.0000.2040 */ 116 u_int64_t sbus_config14; /* Slot 14 config register <macio> */ /* 1fe.0000.2048 */ 117 u_int64_t sbus_config15; /* Slot 15 config register <slavio> */ /* 1fe.0000.2050 */ 118 } sys_sbus; 119 120 u_int64_t pad3[117]; 121 122 struct iommureg { 123 u_int64_t iommu_cr; /* IOMMU control register */ /* 1fe.0000.2400 */ 124 #define IOMMUCR_TSB1K 0x000000000000000000LL /* Nummber of entries in IOTSB */ 125 #define IOMMUCR_TSB2K 0x000000000000010000LL 126 #define IOMMUCR_TSB4K 0x000000000000020000LL 127 #define IOMMUCR_TSB8K 0x000000000000030000LL 128 #define IOMMUCR_TSB16K 0x000000000000040000LL 129 #define IOMMUCR_TSB32K 0x000000000000050000LL 130 #define IOMMUCR_TSB64K 0x000000000000060000LL 131 #define IOMMUCR_TSB128K 0x000000000000070000LL 132 #define IOMMUCR_8KPG 0x000000000000000000LL /* 8K iommu page size */ 133 #define IOMMUCR_64KPG 0x000000000000000004LL /* 64K iommu page size */ 134 #define IOMMUCR_DE 0x000000000000000002LL /* Diag enable */ 135 #define IOMMUCR_EN 0x000000000000000001LL /* Enable IOMMU */ 136 u_int64_t iommu_tsb; /* IOMMU TSB base register */ /* 1fe.0000.2408 */ 137 u_int64_t iommu_flush; /* IOMMU flush register */ /* 1fe.0000.2410 */ 138 } sys_iommu; 139 140 u_int64_t pad4[125]; 141 142 struct strbuf { 143 u_int64_t strbuf_ctl; /* streaming buffer control reg */ /* 1fe.0000.2800 */ 144 #define STRBUF_EN 0x000000000000000001LL 145 #define STRBUF_D 0x000000000000000002LL 146 u_int64_t strbuf_pgflush; /* streaming buffer page flush */ /* 1fe.0000.2808 */ 147 u_int64_t strbuf_flushsync; /* streaming buffer flush sync */ /* 1fe.0000.2810 */ 148 } sys_strbuf; 149 150 u_int64_t pad5[125]; 151 152 u_int64_t sbus_slot0_int; /* SBUS slot 0 interrupt map reg */ /* 1fe.0000.2c00 */ 153 u_int64_t sbus_slot1_int; /* SBUS slot 1 interrupt map reg */ /* 1fe.0000.2c08 */ 154 u_int64_t sbus_slot2_int; /* SBUS slot 2 interrupt map reg */ /* 1fe.0000.2c10 */ 155 u_int64_t sbus_slot3_int; /* SBUS slot 3 interrupt map reg */ /* 1fe.0000.2c18 */ 156 u_int64_t intr_retry; /* interrupt retry timer reg */ /* 1fe.0000.2c20 */ 157 158 u_int64_t pad6[123]; 159 160 u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3000 */ 161 u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.3008 */ 162 u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.3010 */ 163 u_int64_t audio_int_map; /* audio interrupt map reg */ /* 1fe.0000.3018 */ 164 u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.3020 */ 165 u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.3028 */ 166 u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.3030 */ 167 u_int64_t therm_int_map; /* thermal warn interrupt map reg */ /* 1fe.0000.3038 */ 168 u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.3040 */ 169 u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.3048 */ 170 u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.3050 */ 171 u_int64_t pad7; 172 u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.3060 */ 173 u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.3068 */ 174 u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.3070 */ 175 u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.3078 */ 176 u_int64_t sbus_async_int_map; /* SBUS error interrupt map reg */ /* 1fe.0000.3080 */ 177 u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.3088 */ 178 u_int64_t upagr_int_map; /* UPA graphics interrupt map reg */ /* 1fe.0000.3090 */ 179 u_int64_t reserved_int_map; /* reserved interrupt map reg */ /* 1fe.0000.3098 */ 180 181 u_int64_t pad8[108]; 182 183 /* Note: clear interrupt 0 registers are not really used */ 184 u_int64_t sbus0_clr_int[8]; /* SBUS slot 0 clear int regs 0..7 */ /* 1fe.0000.3400-3438 */ 185 u_int64_t sbus1_clr_int[8]; /* SBUS slot 1 clear int regs 0..7 */ /* 1fe.0000.3440-3478 */ 186 u_int64_t sbus2_clr_int[8]; /* SBUS slot 2 clear int regs 0..7 */ /* 1fe.0000.3480-34b8 */ 187 u_int64_t sbus3_clr_int[8]; /* SBUS slot 3 clear int regs 0..7 */ /* 1fe.0000.34c0-34f8 */ 188 189 u_int64_t pad9[96]; 190 191 u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.3800 */ 192 u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.3808 */ 193 u_int64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.3810 */ 194 u_int64_t audio_clr_int; /* audio clear int reg */ /* 1fe.0000.3818 */ 195 u_int64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.3820 */ 196 u_int64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.3828 */ 197 u_int64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.3830 */ 198 u_int64_t therm_clr_int; /* thermal warn clear int reg */ /* 1fe.0000.3838 */ 199 u_int64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.3840 */ 200 u_int64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.3848 */ 201 u_int64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.3850 */ 202 u_int64_t pad10; 203 u_int64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.3860 */ 204 u_int64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.3868 */ 205 u_int64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.3870 */ 206 u_int64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.3878 */ 207 u_int64_t sbus_clr_async_int; /* SBUS error clr interrupt reg */ /* 1fe.0000.3880 */ 208 u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.3888 */ 209 210 u_int64_t pad11[110]; 211 212 struct timer_counter { 213 u_int64_t tc_count; /* timer/counter 0/1 count register */ /* ife.0000.3c00,3c10 */ 214 u_int64_t tc_limit; /* timer/counter 0/1 limit register */ /* ife.0000.3c08,3c18 */ 215 } tc[2]; 216 217 u_int64_t pad12[252]; 218 219 u_int64_t sys_svadiag; /* SBUS virtual addr diag reg */ /* 1fe.0000.4400 */ 220 221 u_int64_t pad13[31]; 222 223 u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */ 224 u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.4580-45ff */ 225 u_int64_t tlb_data_diag[32]; /* TLB data RAM diag */ /* 1fe.0000.4600-46ff */ 226 227 u_int64_t pad14[32]; 228 229 u_int64_t sbus_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.4800 */ 230 u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.4808 */ 231 232 u_int64_t pad15[254]; 233 234 u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.5000-53f8 */ 235 u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.5400-57f8 */ 236 u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.5800-5878 */ 237 u_int64_t pad16[16]; 238 u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.5900-5978 */ 239 }; 240 241 /* 242 * sun4u iommu stuff. Probably belongs elsewhere. 243 */ 244 245 #define IOTTE_V 0x8000000000000000LL /* Entry valid */ 246 #define IOTTE_64K 0x2000000000000000LL /* 8K or 64K page? */ 247 #define IOTTE_8K 0x0000000000000000LL 248 #define IOTTE_STREAM 0x1000000000000000LL /* Is page streamable? */ 249 #define IOTTE_LOCAL 0x0800000000000000LL /* Accesses to same bus segment? */ 250 #define IOTTE_PAMASK 0x000001ffffffe000LL /* Let's assume this is correct */ 251 #define IOTTE_C 0x0000000000000010LL /* Accesses to cacheable space */ 252 #define IOTTE_W 0x0000000000000002LL /* Writeable */ 253 254 #define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K)) 255 #if 0 256 /* This version generates a pointer to a int64_t */ 257 #define IOTSBSLOT(va,sz) ((((((vm_offset_t)(va))-(0xff800000<<(sz))))>>(13-3))&(~7)) 258 #else 259 /* Here we just try to create an array index */ 260 #define IOTSBSLOT(va,sz) ((((((vm_offset_t)(va))-(0xff800000<<(sz))))>>(13))) 261 #endif 262 263 /* 264 * intr map stuff. Probably belongs elsewhere. 265 */ 266 267 #define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */ 268 #define INTMAP_TID 0x07c000000LL /* UPA target ID mask */ 269 #define INTMAP_IGN 0x0000007c0LL /* Interrupt group no. */ 270 #define INTMAP_INO 0x00000003fLL /* Interrupt number */ 271 #define INTMAP_INR (INTMAP_IGN|INTMAP_INO) 272 #define INTMAP_SLOT 0x000000018LL /* SBUS slot # */ 273 #define INTMAP_OBIO 0x000000020LL /* Onboard device */ 274 #define INTMAP_LSHIFT 11 /* Encode level in vector */ 275 #define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT) 276 #define INTLEV(x) (((x)>>INTMAP_LSHIFT)&0x0f) 277 #define INTVEC(x) ((x)&INTMAP_INR) 278 #define INTSLOT(x) (((x)>>3)&0x7) 279 #define INTPRI(x) ((x)&0x7) 280
Indexes created Thu Oct 02 14:10:14 GMT 2025