schizo.c revision 1.12
1 /* $NetBSD: schizo.c,v 1.12 2010/01/06 05:55:01 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/extent.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/time.h> 38 #include <sys/reboot.h> 39 40 #define _SPARC_BUS_DMA_PRIVATE 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/psl.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <sparc64/dev/iommureg.h> 49 #include <sparc64/dev/iommuvar.h> 50 #include <sparc64/dev/schizoreg.h> 51 #include <sparc64/dev/schizovar.h> 52 #include <sparc64/sparc64/cache.h> 53 54 #ifdef DEBUG 55 #define SDB_PROM 0x01 56 #define SDB_BUSMAP 0x02 57 #define SDB_INTR 0x04 58 #define SDB_INTMAP 0x08 59 #define SDB_CONF 0x10 60 int schizo_debug = 0x0; 61 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 62 #else 63 #define DPRINTF(l, s) 64 #endif 65 66 extern struct sparc_pci_chipset _sparc_pci_chipset; 67 68 static int schizo_match(struct device *, struct cfdata *, void *); 69 static void schizo_attach(struct device *, struct device *, void *); 70 static int schizo_print(void *aux, const char *p); 71 72 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 73 schizo_match, schizo_attach, NULL, NULL); 74 75 void schizo_init(struct schizo_softc *); 76 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 77 78 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 79 int (*handler)(void *), void *, int, const char *); 80 int schizo_ue(void *); 81 int schizo_ce(void *); 82 int schizo_safari_error(void *); 83 int schizo_pci_error(void *); 84 85 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 86 pci_chipset_tag_t); 87 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 91 int); 92 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 93 94 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 97 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 98 int flags, vaddr_t unused, bus_space_handle_t *hp); 99 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 100 off_t off, int prot, int flags); 101 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 102 void *, void(*)(void)); 103 static int schizo_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 104 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 105 int, int (*)(void *), void *); 106 static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 107 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 108 bus_size_t, int, bus_dmamap_t *); 109 110 int 111 schizo_match(struct device *parent, struct cfdata *match, void *aux) 112 { 113 struct mainbus_attach_args *ma = aux; 114 char *str; 115 116 if (strcmp(ma->ma_name, "pci") != 0) 117 return (0); 118 119 str = prom_getpropstring(ma->ma_node, "model"); 120 if (strcmp(str, "schizo") == 0) 121 return (1); 122 123 str = prom_getpropstring(ma->ma_node, "compatible"); 124 if (strcmp(str, "pci108e,8001") == 0) 125 return (1); 126 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 127 return (1); 128 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 129 return (1); 130 131 return (0); 132 } 133 134 void 135 schizo_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct schizo_softc *sc = (struct schizo_softc *)self; 138 struct mainbus_attach_args *ma = aux; 139 uint64_t eccctrl; 140 char *str; 141 142 printf(": addr %lx", ma->ma_reg[0].ur_paddr); 143 str = prom_getpropstring(ma->ma_node, "compatible"); 144 if (strcmp(str, "pci108e,a801") == 0) 145 sc->sc_tomatillo = 1; 146 147 sc->sc_node = ma->ma_node; 148 sc->sc_dmat = ma->ma_dmatag; 149 sc->sc_bustag = ma->ma_bustag; 150 sc->sc_ctrl = ma->ma_reg[1].ur_paddr - 0x10000UL; 151 sc->sc_reg0 = ma->ma_reg[0]; 152 153 if (bus_space_map(sc->sc_bustag, sc->sc_ctrl, 154 sizeof(struct schizo_regs), 0, 155 &sc->sc_ctrlh)) { 156 printf(": failed to map registers\n"); 157 return; 158 } 159 160 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 161 162 /* enable schizo ecc error interrupts */ 163 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 164 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 165 SCZ_ECCCTRL_UE_INTEN | 166 SCZ_ECCCTRL_CE_INTEN; 167 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 168 169 schizo_init(sc); 170 } 171 172 void 173 schizo_init(struct schizo_softc *sc) 174 { 175 struct schizo_pbm *pbm; 176 struct pcibus_attach_args pba; 177 int *busranges = NULL, nranges; 178 u_int64_t /*match,*/ reg; 179 180 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 181 if (pbm == NULL) 182 panic("schizo: can't alloc schizo pbm"); 183 184 pbm->sp_sc = sc; 185 pbm->sp_regt = sc->sc_bustag; 186 187 if ((sc->sc_reg0.ur_paddr & 0x00700000) == 0x00600000) 188 pbm->sp_bus_a = 1; 189 else 190 pbm->sp_bus_a = 0; 191 192 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 193 &pbm->sp_nrange, (void **)&pbm->sp_range)) 194 panic("schizo: can't get ranges"); 195 196 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 197 (void **)&busranges)) 198 panic("schizo: can't get bus-range"); 199 200 printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 201 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 202 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 203 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 204 205 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 206 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 207 offsetof(struct schizo_regs, pbm_b), 208 sizeof(struct schizo_pbm_regs), 209 &pbm->sp_regh)) { 210 panic("schizo: unable to create PBM handle"); 211 } 212 213 printf("%s: ", sc->sc_dv.dv_xname); 214 schizo_init_iommu(sc, pbm); 215 216 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 217 pbm->sp_iot = schizo_alloc_io_tag(pbm); 218 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 219 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 220 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 221 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 222 223 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 224 panic("schizo: could not map config space"); 225 226 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 227 &_sparc_pci_chipset); 228 pbm->sp_pc->spc_busmax = busranges[1]; 229 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 230 M_DEVBUF, M_NOWAIT | M_ZERO); 231 if (pbm->sp_pc->spc_busnode == NULL) 232 panic("schizo: malloc busnode"); 233 234 pba.pba_bus = busranges[0]; 235 pba.pba_bridgetag = NULL; 236 pba.pba_pc = pbm->sp_pc; 237 pba.pba_flags = pbm->sp_flags; 238 pba.pba_dmat = pbm->sp_dmat; 239 pba.pba_dmat64 = NULL; /* XXX */ 240 pba.pba_memt = pbm->sp_memt; 241 pba.pba_iot = pbm->sp_iot; 242 243 free(busranges, M_DEVBUF); 244 245 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 246 247 /* clear out the bus errors */ 248 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 249 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 250 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 251 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 252 253 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 254 /* enable/disable error interrupts and arbiter */ 255 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 256 reg &= ~SCZ_PCICTRL_SBH_INT; 257 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 258 259 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 260 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 261 SCZ_PCIDIAG_D_INTSYNC); 262 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 263 264 if (pbm->sp_bus_a) 265 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 266 pbm, SCZ_PCIERR_A_INO, "pci_a"); 267 else 268 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 269 pbm, SCZ_PCIERR_B_INO, "pci_b"); 270 271 /* double mapped */ 272 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 273 "ue"); 274 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 275 "ce"); 276 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 277 SCZ_SERR_INO, "safari"); 278 279 config_found(&sc->sc_dv, &pba, schizo_print); 280 } 281 282 int 283 schizo_ue(void *vsc) 284 { 285 struct schizo_softc *sc = vsc; 286 287 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 288 return (1); 289 } 290 291 int 292 schizo_ce(void *vsc) 293 { 294 struct schizo_softc *sc = vsc; 295 296 panic("%s: correctable error", sc->sc_dv.dv_xname); 297 return (1); 298 } 299 300 int 301 schizo_pci_error(void *vpbm) 302 { 303 struct schizo_pbm *sp = vpbm; 304 struct schizo_softc *sc = sp->sp_sc; 305 u_int64_t afsr, afar, ctrl, tfar; 306 u_int32_t csr; 307 char bits[128]; 308 309 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 310 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 311 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 312 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 313 314 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 315 sp->sp_bus_a ? 'A' : 'B'); 316 317 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 318 printf("PCIAFSR=%s\n", bits); 319 printf("PCIAFAR=%lx\n", afar); 320 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 321 printf("PCICTRL=%s\n", bits); 322 #ifdef PCI_COMMAND_STATUS_BITS 323 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 324 printf("PCICSR=%s\n", bits); 325 #endif 326 327 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 328 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 329 printf("IOMMUCTRL=%lx\n", ctrl); 330 331 if ((ctrl & TOM_IOMMU_ERR) == 0) 332 goto clear_error; 333 334 if (sc->sc_tomatillo) { 335 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 336 printf("IOMMUTFAR=%lx\n", tfar); 337 } 338 339 /* These are non-fatal if target abort was signalled. */ 340 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 341 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 342 ctrl & TOM_IOMMU_BADVA_ERR) { 343 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 344 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 345 goto clear_error; 346 } 347 } 348 } 349 350 panic("%s: fatal", sc->sc_dv.dv_xname); 351 352 clear_error: 353 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 354 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 355 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 356 return (1); 357 } 358 359 int 360 schizo_safari_error(void *vsc) 361 { 362 struct schizo_softc *sc = vsc; 363 364 printf("%s: safari error\n", sc->sc_dv.dv_xname); 365 366 printf("ERRLOG=%lx\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 367 printf("UE_AFSR=%lx\n", schizo_read(sc, SCZ_UE_AFSR)); 368 printf("UE_AFAR=%lx\n", schizo_read(sc, SCZ_UE_AFAR)); 369 printf("CE_AFSR=%lx\n", schizo_read(sc, SCZ_CE_AFSR)); 370 printf("CE_AFAR=%lx\n", schizo_read(sc, SCZ_CE_AFAR)); 371 372 panic("%s: fatal", sc->sc_dv.dv_xname); 373 return (1); 374 } 375 376 void 377 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 378 { 379 struct iommu_state *is = &pbm->sp_is; 380 int *vdma = NULL, nitem, tsbsize = 7; 381 u_int32_t iobase = -1; 382 vaddr_t va; 383 char *name; 384 385 va = (vaddr_t)pbm->sp_flush[0x40]; 386 387 /* punch in our copies */ 388 is->is_bustag = pbm->sp_regt; 389 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 390 offsetof(struct schizo_pbm_regs, iommu), 391 sizeof(struct schizo_iommureg), &is->is_iommu)) { 392 printf("schizo: unable to create streaming buffer handle\n"); 393 is->is_sb[0]->sb_flush = NULL; 394 } 395 396 /* initialize our strbuf_ctl */ 397 is->is_sb[0] = &pbm->sp_sb; 398 pbm->sp_sb.sb_is = is; 399 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 400 401 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 402 offsetof(struct schizo_pbm_regs, strbuf), 403 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb)) { 404 } 405 406 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 407 if (name == NULL) 408 panic("couldn't malloc iommu name"); 409 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 410 411 /* 412 * Separate the men from the boys. If the `virtual-dma' 413 * property exists, use it. 414 */ 415 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 416 (void **)&vdma)) { 417 /* Damn. Gotta use these values. */ 418 iobase = vdma[0]; 419 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 420 switch (vdma[1]) { 421 TSBCASE(1); TSBCASE(2); TSBCASE(3); 422 TSBCASE(4); TSBCASE(5); TSBCASE(6); 423 default: 424 printf("bogus tsb size %x, using 7\n", vdma[1]); 425 TSBCASE(7); 426 } 427 #undef TSBCASE 428 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 429 free(vdma, M_DEVBUF); 430 } else { 431 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 432 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 433 } 434 435 iommu_init(name, is, tsbsize, iobase); 436 } 437 438 int 439 schizo_print(void *aux, const char *p) 440 { 441 442 if (p == NULL) 443 return (UNCONF); 444 return (QUIET); 445 } 446 447 pcireg_t 448 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 449 { 450 struct schizo_pbm *sp = pc->cookie; 451 pcireg_t val = (pcireg_t)~0; 452 453 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 454 if (PCITAG_NODE(tag) != -1) 455 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 456 PCITAG_OFFSET(tag) + reg); 457 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 458 return (val); 459 } 460 461 void 462 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 463 { 464 struct schizo_pbm *sp = pc->cookie; 465 466 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 467 (long)tag, reg, (int)data)); 468 469 /* If we don't know it, just punt it. */ 470 if (PCITAG_NODE(tag) == -1) { 471 DPRINTF(SDB_CONF, (" .. bad addr\n")); 472 return; 473 } 474 475 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 476 PCITAG_OFFSET(tag) + reg, data); 477 DPRINTF(SDB_CONF, (" .. done\n")); 478 } 479 480 void 481 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 482 int (*handler)(void *), void *arg, int ino, const char *what) 483 { 484 struct intrhand *ih; 485 u_int64_t mapoff, clroff; 486 487 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 488 ino, sc->sc_ign, handler, arg)); 489 490 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 491 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 492 ino |= sc->sc_ign; 493 494 DPRINTF(SDB_INTR, (" mapoff %lx clroff %lx\n", mapoff, clroff)); 495 496 ih = (struct intrhand *) 497 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 498 if (ih == NULL) 499 return; 500 ih->ih_arg = arg; 501 ih->ih_map = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + mapoff); 502 ih->ih_clr = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + clroff); 503 ih->ih_fun = handler; 504 ih->ih_pil = (1<<ipl); 505 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 506 intr_establish(ipl, ipl != IPL_VM, ih); 507 508 schizo_pbm_write(pbm, mapoff, 509 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 510 } 511 512 bus_space_tag_t 513 schizo_alloc_mem_tag(struct schizo_pbm *sp) 514 { 515 return (schizo_alloc_bus_tag(sp, "mem", 516 PCI_MEMORY_BUS_SPACE)); 517 } 518 519 bus_space_tag_t 520 schizo_alloc_io_tag(struct schizo_pbm *sp) 521 { 522 return (schizo_alloc_bus_tag(sp, "io", 523 PCI_IO_BUS_SPACE)); 524 } 525 526 bus_space_tag_t 527 schizo_alloc_config_tag(struct schizo_pbm *sp) 528 { 529 return (schizo_alloc_bus_tag(sp, "cfg", 530 PCI_CONFIG_BUS_SPACE)); 531 } 532 533 bus_space_tag_t 534 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 535 { 536 struct schizo_softc *sc = pbm->sp_sc; 537 bus_space_tag_t bt; 538 539 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 540 M_DEVBUF, M_NOWAIT | M_ZERO); 541 if (bt == NULL) 542 panic("schizo: could not allocate bus tag"); 543 544 bt->cookie = pbm; 545 bt->parent = sc->sc_bustag; 546 bt->type = type; 547 bt->sparc_bus_map = schizo_bus_map; 548 bt->sparc_bus_mmap = schizo_bus_mmap; 549 bt->sparc_intr_establish = schizo_intr_establish; 550 return (bt); 551 } 552 553 bus_dma_tag_t 554 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 555 { 556 struct schizo_softc *sc = pbm->sp_sc; 557 bus_dma_tag_t dt, pdt = sc->sc_dmat; 558 559 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 560 if (dt == NULL) 561 panic("schizo: could not alloc dma tag"); 562 563 dt->_cookie = pbm; 564 dt->_parent = pdt; 565 #define PCOPY(x) dt->x = pdt->x 566 dt->_dmamap_create = schizo_dmamap_create; 567 PCOPY(_dmamap_destroy); 568 dt->_dmamap_load = iommu_dvmamap_load; 569 PCOPY(_dmamap_load_mbuf); 570 PCOPY(_dmamap_load_uio); 571 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 572 dt->_dmamap_unload = iommu_dvmamap_unload; 573 dt->_dmamap_sync = iommu_dvmamap_sync; 574 dt->_dmamem_alloc = iommu_dvmamem_alloc; 575 dt->_dmamem_free = iommu_dvmamem_free; 576 dt->_dmamem_map = iommu_dvmamem_map; 577 dt->_dmamem_unmap = iommu_dvmamem_unmap; 578 PCOPY(_dmamem_mmap); 579 #undef PCOPY 580 return (dt); 581 } 582 583 pci_chipset_tag_t 584 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 585 { 586 pci_chipset_tag_t npc; 587 588 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 589 if (npc == NULL) 590 panic("schizo: could not allocate pci_chipset_tag_t"); 591 memcpy(npc, pc, sizeof *pc); 592 npc->cookie = pbm; 593 npc->rootnode = node; 594 npc->spc_conf_read = schizo_conf_read; 595 npc->spc_conf_write = schizo_conf_write; 596 npc->spc_intr_map = schizo_pci_intr_map; 597 npc->spc_intr_establish = schizo_pci_intr_establish; 598 npc->spc_find_ino = schizo_pci_find_ino; 599 return (npc); 600 } 601 602 int 603 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 604 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 605 bus_dmamap_t *dmamp) 606 { 607 struct schizo_pbm *pbm = t->_cookie; 608 int error; 609 610 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 611 boundary, flags, dmamp); 612 if (error == 0) 613 (*dmamp)->_dm_cookie = &pbm->sp_sb; 614 return error; 615 } 616 617 static struct schizo_range * 618 get_schizorange(struct schizo_pbm *pbm, int ss) 619 { 620 int i; 621 622 for (i = 0; i < pbm->sp_nrange; i++) { 623 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 624 return (&pbm->sp_range[i]); 625 } 626 /* not found */ 627 return (NULL); 628 } 629 630 int 631 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 632 int flags, vaddr_t unused, bus_space_handle_t *hp) 633 { 634 bus_addr_t paddr; 635 struct schizo_pbm *pbm = t->cookie; 636 struct schizo_softc *sc = pbm->sp_sc; 637 struct schizo_range *sr; 638 int ss; 639 640 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 641 t->type, 642 (unsigned long long)offset, 643 (unsigned long long)size, 644 flags)); 645 646 ss = sparc_pci_childspace(t->type); 647 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 648 649 sr = get_schizorange(pbm, ss); 650 if (sr != NULL) { 651 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 652 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 653 "space %lx offset %lx paddr %qx\n", 654 __func__, (long)ss, (long)offset, 655 (unsigned long long)paddr)); 656 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 657 flags, 0, hp)); 658 } 659 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 660 return (EINVAL); 661 } 662 663 static paddr_t 664 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 665 int flags) 666 { 667 bus_addr_t offset = paddr; 668 struct schizo_pbm *pbm = t->cookie; 669 struct schizo_softc *sc = pbm->sp_sc; 670 struct schizo_range *sr; 671 int ss; 672 673 ss = sparc_pci_childspace(t->type); 674 675 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 676 prot, flags, (unsigned long long)paddr)); 677 678 sr = get_schizorange(pbm, ss); 679 if (sr != NULL) { 680 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 681 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 682 "space %lx offset %lx paddr %qx\n", 683 __func__, (long)ss, (long)offset, 684 (unsigned long long)paddr)); 685 return (bus_space_mmap(sc->sc_bustag, paddr, off, 686 prot, flags)); 687 } 688 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 689 return (-1); 690 } 691 692 /* 693 * Set the IGN for this schizo into the handle. 694 */ 695 int 696 schizo_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 697 { 698 struct schizo_pbm *pbm = pa->pa_pc->cookie; 699 struct schizo_softc *sc = pbm->sp_sc; 700 701 *ihp |= sc->sc_ign; 702 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 703 return (0); 704 } 705 706 static void * 707 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 708 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 709 { 710 struct schizo_pbm *pbm = t->cookie; 711 struct schizo_softc *sc = pbm->sp_sc; 712 struct intrhand *ih = NULL; 713 uint64_t mapoff, clroff; 714 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 715 int ino; 716 long vec; 717 718 vec = INTVEC(ihandle); 719 ino = INTINO(vec); 720 721 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 722 if (ih == NULL) 723 return (NULL); 724 725 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 726 ihandle, level, handler, arg)); 727 728 if (level == IPL_NONE) 729 level = INTLEV(vec); 730 if (level == IPL_NONE) { 731 printf(": no IPL, setting IPL 2.\n"); 732 level = 2; 733 } 734 735 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 736 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 737 738 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %lx clroff %lx\n", 739 __func__, ino, intrlev[ino], mapoff, clroff)); 740 741 intrmapptr = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + mapoff); 742 intrclrptr = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + clroff); 743 744 if (INTIGN(vec) == 0) 745 ino |= schizo_pbm_read(pbm, mapoff) & INTMAP_IGN; 746 else 747 ino |= vec & INTMAP_IGN; 748 749 /* Register the map and clear intr registers */ 750 ih->ih_map = intrmapptr; 751 ih->ih_clr = intrclrptr; 752 753 ih->ih_fun = handler; 754 ih->ih_arg = arg; 755 ih->ih_pil = level; 756 ih->ih_number = ino; 757 758 DPRINTF(SDB_INTR, ( 759 "; installing handler %p arg %p with inr %x pil %u\n", 760 handler, arg, ino, (u_int)ih->ih_pil)); 761 762 intr_establish(ih->ih_pil, level != IPL_VM, ih); 763 764 /* 765 * Enable the interrupt now we have the handler installed. 766 * Read the current value as we can't change it besides the 767 * valid bit so so make sure only this bit is changed. 768 */ 769 if (intrmapptr) { 770 u_int64_t imap; 771 772 imap = schizo_pbm_read(pbm, mapoff); 773 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 774 (unsigned long long)imap)); 775 imap |= INTMAP_V; 776 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 777 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 778 (unsigned long long)imap)); 779 schizo_pbm_write(pbm, mapoff, imap); 780 imap = schizo_pbm_read(pbm, mapoff); 781 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 782 (unsigned long long)imap)); 783 ih->ih_number |= imap & INTMAP_INR; 784 } 785 if (intrclrptr) { 786 /* set state to IDLE */ 787 schizo_pbm_write(pbm, clroff, 0); 788 } 789 790 return (ih); 791 } 792 793 static void * 794 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 795 int (*func)(void *), void *arg) 796 { 797 void *cookie; 798 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 799 800 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 801 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 802 803 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 804 return (cookie); 805 } 806 807 static int 808 schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 809 { 810 #if 0 811 struct schizo_pbm *pbm = pa->pa_pc->cookie; 812 struct schizo_softc *sc = pbm->sp_sc; 813 u_int bus; 814 u_int dev; 815 u_int pin; 816 #endif 817 818 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 819 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 820 (int)PCITAG_DEV(pa->pa_tag), 821 (int)PCITAG_FUN(pa->pa_tag))); 822 DPRINTF(SDB_INTMAP, 823 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 824 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 825 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 826 PCITAG_NODE(pa->pa_intrtag), 827 (int)PCITAG_BUS(pa->pa_intrtag), 828 (int)PCITAG_DEV(pa->pa_intrtag), 829 (int)PCITAG_FUN(pa->pa_intrtag))); 830 831 #if 0 832 bus = (pp->pp_id == PSYCHO_PBM_B); 833 /* 834 * If we are on a ppb, use the devno on the underlying bus when forming 835 * the ivec. 836 */ 837 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 838 dev = PCITAG_DEV(pa->pa_intrtag); 839 else 840 dev = pa->pa_device; 841 dev--; 842 843 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 844 pp->pp_id == PSYCHO_PBM_B) 845 dev--; 846 847 pin = pa->pa_intrpin - 1; 848 DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 849 sc->sc_mode, pp->pp_id, dev, pin)); 850 851 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 852 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 853 #endif 854 855 return (0); 856 } 857
Indexes created Tue Sep 30 20:09:53 GMT 2025