schizo.c revision 1.14
1 /* $NetBSD: schizo.c,v 1.14 2010/02/13 11:55:48 nakayama Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/extent.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/time.h> 38 #include <sys/reboot.h> 39 40 #define _SPARC_BUS_DMA_PRIVATE 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/psl.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <sparc64/dev/iommureg.h> 49 #include <sparc64/dev/iommuvar.h> 50 #include <sparc64/dev/schizoreg.h> 51 #include <sparc64/dev/schizovar.h> 52 #include <sparc64/sparc64/cache.h> 53 54 #ifdef DEBUG 55 #define SDB_PROM 0x01 56 #define SDB_BUSMAP 0x02 57 #define SDB_INTR 0x04 58 #define SDB_INTMAP 0x08 59 #define SDB_CONF 0x10 60 int schizo_debug = 0x0; 61 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 62 #else 63 #define DPRINTF(l, s) 64 #endif 65 66 extern struct sparc_pci_chipset _sparc_pci_chipset; 67 68 static int schizo_match(struct device *, struct cfdata *, void *); 69 static void schizo_attach(struct device *, struct device *, void *); 70 static int schizo_print(void *aux, const char *p); 71 72 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 73 schizo_match, schizo_attach, NULL, NULL); 74 75 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 76 77 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 78 int (*handler)(void *), void *, int, const char *); 79 int schizo_ue(void *); 80 int schizo_ce(void *); 81 int schizo_safari_error(void *); 82 int schizo_pci_error(void *); 83 84 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 85 pci_chipset_tag_t); 86 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 87 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 90 int); 91 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 92 93 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 94 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 95 96 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 97 int flags, vaddr_t unused, bus_space_handle_t *hp); 98 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 99 off_t off, int prot, int flags); 100 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 101 void *, void(*)(void)); 102 static int schizo_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 103 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 104 int, int (*)(void *), void *); 105 static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 106 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 107 bus_size_t, int, bus_dmamap_t *); 108 109 int 110 schizo_match(struct device *parent, struct cfdata *match, void *aux) 111 { 112 struct mainbus_attach_args *ma = aux; 113 char *str; 114 115 if (strcmp(ma->ma_name, "pci") != 0) 116 return (0); 117 118 str = prom_getpropstring(ma->ma_node, "model"); 119 if (strcmp(str, "schizo") == 0) 120 return (1); 121 122 str = prom_getpropstring(ma->ma_node, "compatible"); 123 if (strcmp(str, "pci108e,8001") == 0) 124 return (1); 125 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 126 return (1); 127 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 128 return (1); 129 130 return (0); 131 } 132 133 void 134 schizo_attach(struct device *parent, struct device *self, void *aux) 135 { 136 struct schizo_softc *sc = (struct schizo_softc *)self; 137 struct mainbus_attach_args *ma = aux; 138 struct schizo_pbm *pbm; 139 struct pcibus_attach_args pba; 140 uint64_t reg, eccctrl; 141 int *busranges = NULL, nranges; 142 char *str; 143 144 printf(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 145 str = prom_getpropstring(ma->ma_node, "compatible"); 146 if (strcmp(str, "pci108e,a801") == 0) 147 sc->sc_tomatillo = 1; 148 149 sc->sc_node = ma->ma_node; 150 sc->sc_dmat = ma->ma_dmatag; 151 sc->sc_bustag = ma->ma_bustag; 152 153 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 154 sizeof(struct schizo_regs), 0, 155 &sc->sc_ctrlh)) { 156 printf(": failed to map registers\n"); 157 return; 158 } 159 160 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 161 162 /* enable schizo ecc error interrupts */ 163 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 164 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 165 SCZ_ECCCTRL_UE_INTEN | 166 SCZ_ECCCTRL_CE_INTEN; 167 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 168 169 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 170 if (pbm == NULL) 171 panic("schizo: can't alloc schizo pbm"); 172 173 pbm->sp_sc = sc; 174 pbm->sp_regt = sc->sc_bustag; 175 176 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 177 pbm->sp_bus_a = 1; 178 else 179 pbm->sp_bus_a = 0; 180 181 /* 182 * Map interrupt registers 183 */ 184 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 185 ma->ma_reg[0].ur_len, 186 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 187 printf(": failed to interrupt map registers\n"); 188 return; 189 } 190 191 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 192 &pbm->sp_nrange, (void **)&pbm->sp_range)) 193 panic("schizo: can't get ranges"); 194 195 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 196 (void **)&busranges)) 197 panic("schizo: can't get bus-range"); 198 199 printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 200 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 201 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 202 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 203 204 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 205 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 206 offsetof(struct schizo_regs, pbm_b), 207 sizeof(struct schizo_pbm_regs), 208 &pbm->sp_regh)) { 209 panic("schizo: unable to create PBM handle"); 210 } 211 212 printf("%s: ", sc->sc_dv.dv_xname); 213 schizo_init_iommu(sc, pbm); 214 215 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 216 pbm->sp_iot = schizo_alloc_io_tag(pbm); 217 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 218 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 219 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 220 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 221 222 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 223 panic("schizo: could not map config space"); 224 225 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 226 &_sparc_pci_chipset); 227 pbm->sp_pc->spc_busmax = busranges[1]; 228 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 229 M_DEVBUF, M_NOWAIT | M_ZERO); 230 if (pbm->sp_pc->spc_busnode == NULL) 231 panic("schizo: malloc busnode"); 232 233 pba.pba_bus = busranges[0]; 234 pba.pba_bridgetag = NULL; 235 pba.pba_pc = pbm->sp_pc; 236 pba.pba_flags = pbm->sp_flags; 237 pba.pba_dmat = pbm->sp_dmat; 238 pba.pba_dmat64 = NULL; /* XXX */ 239 pba.pba_memt = pbm->sp_memt; 240 pba.pba_iot = pbm->sp_iot; 241 242 free(busranges, M_DEVBUF); 243 244 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 245 246 /* clear out the bus errors */ 247 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 248 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 249 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 250 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 251 252 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 253 /* enable/disable error interrupts and arbiter */ 254 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 255 reg &= ~SCZ_PCICTRL_SBH_INT; 256 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 257 258 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 259 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 260 SCZ_PCIDIAG_D_INTSYNC); 261 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 262 263 if (pbm->sp_bus_a) 264 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 265 pbm, SCZ_PCIERR_A_INO, "pci_a"); 266 else 267 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 268 pbm, SCZ_PCIERR_B_INO, "pci_b"); 269 270 /* double mapped */ 271 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 272 "ue"); 273 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 274 "ce"); 275 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 276 SCZ_SERR_INO, "safari"); 277 278 config_found(&sc->sc_dv, &pba, schizo_print); 279 } 280 281 int 282 schizo_ue(void *vsc) 283 { 284 struct schizo_softc *sc = vsc; 285 286 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 287 return (1); 288 } 289 290 int 291 schizo_ce(void *vsc) 292 { 293 struct schizo_softc *sc = vsc; 294 295 panic("%s: correctable error", sc->sc_dv.dv_xname); 296 return (1); 297 } 298 299 int 300 schizo_pci_error(void *vpbm) 301 { 302 struct schizo_pbm *sp = vpbm; 303 struct schizo_softc *sc = sp->sp_sc; 304 u_int64_t afsr, afar, ctrl, tfar; 305 u_int32_t csr; 306 char bits[128]; 307 308 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 309 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 310 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 311 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 312 313 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 314 sp->sp_bus_a ? 'A' : 'B'); 315 316 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 317 printf("PCIAFSR=%s\n", bits); 318 printf("PCIAFAR=%" PRIx64 "\n", afar); 319 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 320 printf("PCICTRL=%s\n", bits); 321 #ifdef PCI_COMMAND_STATUS_BITS 322 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 323 printf("PCICSR=%s\n", bits); 324 #endif 325 326 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 327 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 328 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 329 330 if ((ctrl & TOM_IOMMU_ERR) == 0) 331 goto clear_error; 332 333 if (sc->sc_tomatillo) { 334 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 335 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 336 } 337 338 /* These are non-fatal if target abort was signalled. */ 339 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 340 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 341 ctrl & TOM_IOMMU_BADVA_ERR) { 342 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 343 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 344 goto clear_error; 345 } 346 } 347 } 348 349 panic("%s: fatal", sc->sc_dv.dv_xname); 350 351 clear_error: 352 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 353 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 354 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 355 return (1); 356 } 357 358 int 359 schizo_safari_error(void *vsc) 360 { 361 struct schizo_softc *sc = vsc; 362 363 printf("%s: safari error\n", sc->sc_dv.dv_xname); 364 365 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 366 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 367 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 368 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 369 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 370 371 panic("%s: fatal", sc->sc_dv.dv_xname); 372 return (1); 373 } 374 375 void 376 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 377 { 378 struct iommu_state *is = &pbm->sp_is; 379 int *vdma = NULL, nitem, tsbsize = 7; 380 u_int32_t iobase = -1; 381 vaddr_t va; 382 char *name; 383 384 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 385 } 386 387 va = (vaddr_t)pbm->sp_flush[0x40]; 388 389 /* punch in our copies */ 390 is->is_bustag = pbm->sp_regt; 391 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 392 offsetof(struct schizo_pbm_regs, iommu), 393 sizeof(struct schizo_iommureg), &is->is_iommu)) { 394 printf("schizo: unable to create streaming buffer handle\n"); 395 is->is_sb[0]->sb_flush = NULL; 396 } 397 398 /* initialize our strbuf_ctl */ 399 is->is_sb[0] = &pbm->sp_sb; 400 pbm->sp_sb.sb_is = is; 401 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 402 403 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 404 offsetof(struct schizo_pbm_regs, strbuf), 405 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb)) { 406 } 407 408 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 409 if (name == NULL) 410 panic("couldn't malloc iommu name"); 411 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 412 413 /* 414 * Separate the men from the boys. If the `virtual-dma' 415 * property exists, use it. 416 */ 417 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 418 (void **)&vdma)) { 419 /* Damn. Gotta use these values. */ 420 iobase = vdma[0]; 421 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 422 switch (vdma[1]) { 423 TSBCASE(1); TSBCASE(2); TSBCASE(3); 424 TSBCASE(4); TSBCASE(5); TSBCASE(6); 425 default: 426 printf("bogus tsb size %x, using 7\n", vdma[1]); 427 TSBCASE(7); 428 } 429 #undef TSBCASE 430 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 431 free(vdma, M_DEVBUF); 432 } else { 433 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 434 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 435 } 436 437 iommu_init(name, is, tsbsize, iobase); 438 } 439 440 int 441 schizo_print(void *aux, const char *p) 442 { 443 444 if (p == NULL) 445 return (UNCONF); 446 return (QUIET); 447 } 448 449 pcireg_t 450 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 451 { 452 struct schizo_pbm *sp = pc->cookie; 453 pcireg_t val = (pcireg_t)~0; 454 455 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 456 if (PCITAG_NODE(tag) != -1) 457 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 458 PCITAG_OFFSET(tag) + reg); 459 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 460 return (val); 461 } 462 463 void 464 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 465 { 466 struct schizo_pbm *sp = pc->cookie; 467 468 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 469 (long)tag, reg, (int)data)); 470 471 /* If we don't know it, just punt it. */ 472 if (PCITAG_NODE(tag) == -1) { 473 DPRINTF(SDB_CONF, (" .. bad addr\n")); 474 return; 475 } 476 477 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 478 PCITAG_OFFSET(tag) + reg, data); 479 DPRINTF(SDB_CONF, (" .. done\n")); 480 } 481 482 void 483 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 484 int (*handler)(void *), void *arg, int ino, const char *what) 485 { 486 struct intrhand *ih; 487 u_int64_t mapoff, clroff; 488 uintptr_t intrregs; 489 490 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 491 ino, sc->sc_ign, handler, arg)); 492 493 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 494 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 495 ino |= sc->sc_ign; 496 497 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 498 mapoff, clroff)); 499 500 ih = (struct intrhand *) 501 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 502 if (ih == NULL) 503 return; 504 ih->ih_arg = arg; 505 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 506 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 507 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 508 ih->ih_fun = handler; 509 ih->ih_pil = (1<<ipl); 510 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 511 intr_establish(ipl, ipl != IPL_VM, ih); 512 513 schizo_pbm_write(pbm, mapoff, 514 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 515 } 516 517 bus_space_tag_t 518 schizo_alloc_mem_tag(struct schizo_pbm *sp) 519 { 520 return (schizo_alloc_bus_tag(sp, "mem", 521 PCI_MEMORY_BUS_SPACE)); 522 } 523 524 bus_space_tag_t 525 schizo_alloc_io_tag(struct schizo_pbm *sp) 526 { 527 return (schizo_alloc_bus_tag(sp, "io", 528 PCI_IO_BUS_SPACE)); 529 } 530 531 bus_space_tag_t 532 schizo_alloc_config_tag(struct schizo_pbm *sp) 533 { 534 return (schizo_alloc_bus_tag(sp, "cfg", 535 PCI_CONFIG_BUS_SPACE)); 536 } 537 538 bus_space_tag_t 539 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 540 { 541 struct schizo_softc *sc = pbm->sp_sc; 542 bus_space_tag_t bt; 543 544 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 545 M_DEVBUF, M_NOWAIT | M_ZERO); 546 if (bt == NULL) 547 panic("schizo: could not allocate bus tag"); 548 549 bt->cookie = pbm; 550 bt->parent = sc->sc_bustag; 551 bt->type = type; 552 bt->sparc_bus_map = schizo_bus_map; 553 bt->sparc_bus_mmap = schizo_bus_mmap; 554 bt->sparc_intr_establish = schizo_intr_establish; 555 return (bt); 556 } 557 558 bus_dma_tag_t 559 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 560 { 561 struct schizo_softc *sc = pbm->sp_sc; 562 bus_dma_tag_t dt, pdt = sc->sc_dmat; 563 564 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 565 if (dt == NULL) 566 panic("schizo: could not alloc dma tag"); 567 568 dt->_cookie = pbm; 569 dt->_parent = pdt; 570 #define PCOPY(x) dt->x = pdt->x 571 dt->_dmamap_create = schizo_dmamap_create; 572 PCOPY(_dmamap_destroy); 573 dt->_dmamap_load = iommu_dvmamap_load; 574 PCOPY(_dmamap_load_mbuf); 575 PCOPY(_dmamap_load_uio); 576 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 577 dt->_dmamap_unload = iommu_dvmamap_unload; 578 dt->_dmamap_sync = iommu_dvmamap_sync; 579 dt->_dmamem_alloc = iommu_dvmamem_alloc; 580 dt->_dmamem_free = iommu_dvmamem_free; 581 dt->_dmamem_map = iommu_dvmamem_map; 582 dt->_dmamem_unmap = iommu_dvmamem_unmap; 583 PCOPY(_dmamem_mmap); 584 #undef PCOPY 585 return (dt); 586 } 587 588 pci_chipset_tag_t 589 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 590 { 591 pci_chipset_tag_t npc; 592 593 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 594 if (npc == NULL) 595 panic("schizo: could not allocate pci_chipset_tag_t"); 596 memcpy(npc, pc, sizeof *pc); 597 npc->cookie = pbm; 598 npc->rootnode = node; 599 npc->spc_conf_read = schizo_conf_read; 600 npc->spc_conf_write = schizo_conf_write; 601 npc->spc_intr_map = schizo_pci_intr_map; 602 npc->spc_intr_establish = schizo_pci_intr_establish; 603 npc->spc_find_ino = schizo_pci_find_ino; 604 return (npc); 605 } 606 607 int 608 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 609 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 610 bus_dmamap_t *dmamp) 611 { 612 struct schizo_pbm *pbm = t->_cookie; 613 int error; 614 615 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 616 boundary, flags, dmamp); 617 if (error == 0) 618 (*dmamp)->_dm_cookie = &pbm->sp_sb; 619 return error; 620 } 621 622 static struct schizo_range * 623 get_schizorange(struct schizo_pbm *pbm, int ss) 624 { 625 int i; 626 627 for (i = 0; i < pbm->sp_nrange; i++) { 628 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 629 return (&pbm->sp_range[i]); 630 } 631 /* not found */ 632 return (NULL); 633 } 634 635 int 636 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 637 int flags, vaddr_t unused, bus_space_handle_t *hp) 638 { 639 bus_addr_t paddr; 640 struct schizo_pbm *pbm = t->cookie; 641 struct schizo_softc *sc = pbm->sp_sc; 642 struct schizo_range *sr; 643 int ss; 644 645 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 646 t->type, 647 (unsigned long long)offset, 648 (unsigned long long)size, 649 flags)); 650 651 ss = sparc_pci_childspace(t->type); 652 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 653 654 sr = get_schizorange(pbm, ss); 655 if (sr != NULL) { 656 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 657 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 658 "space %lx offset %lx paddr %qx\n", 659 __func__, (long)ss, (long)offset, 660 (unsigned long long)paddr)); 661 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 662 flags, 0, hp)); 663 } 664 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 665 return (EINVAL); 666 } 667 668 static paddr_t 669 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 670 int flags) 671 { 672 bus_addr_t offset = paddr; 673 struct schizo_pbm *pbm = t->cookie; 674 struct schizo_softc *sc = pbm->sp_sc; 675 struct schizo_range *sr; 676 int ss; 677 678 ss = sparc_pci_childspace(t->type); 679 680 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 681 prot, flags, (unsigned long long)paddr)); 682 683 sr = get_schizorange(pbm, ss); 684 if (sr != NULL) { 685 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 686 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 687 "space %lx offset %lx paddr %qx\n", 688 __func__, (long)ss, (long)offset, 689 (unsigned long long)paddr)); 690 return (bus_space_mmap(sc->sc_bustag, paddr, off, 691 prot, flags)); 692 } 693 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 694 return (-1); 695 } 696 697 /* 698 * Set the IGN for this schizo into the handle. 699 */ 700 int 701 schizo_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 702 { 703 struct schizo_pbm *pbm = pa->pa_pc->cookie; 704 struct schizo_softc *sc = pbm->sp_sc; 705 706 *ihp |= sc->sc_ign; 707 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 708 return (0); 709 } 710 711 static void * 712 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 713 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 714 { 715 struct schizo_pbm *pbm = t->cookie; 716 struct intrhand *ih = NULL; 717 uint64_t mapoff, clroff; 718 uintptr_t intrregs; 719 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 720 int ino; 721 long vec; 722 723 vec = INTVEC(ihandle); 724 ino = INTINO(vec); 725 726 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 727 if (ih == NULL) 728 return (NULL); 729 730 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 731 ihandle, level, handler, arg)); 732 733 if (level == IPL_NONE) 734 level = INTLEV(vec); 735 if (level == IPL_NONE) { 736 printf(": no IPL, setting IPL 2.\n"); 737 level = 2; 738 } 739 740 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 741 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 742 743 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 744 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 745 746 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 747 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 748 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 749 750 if (INTIGN(vec) == 0) 751 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 752 else 753 ino |= vec & INTMAP_IGN; 754 755 /* Register the map and clear intr registers */ 756 ih->ih_map = intrmapptr; 757 ih->ih_clr = intrclrptr; 758 759 ih->ih_fun = handler; 760 ih->ih_arg = arg; 761 ih->ih_pil = level; 762 ih->ih_number = ino; 763 764 DPRINTF(SDB_INTR, ( 765 "; installing handler %p arg %p with inr %x pil %u\n", 766 handler, arg, ino, (u_int)ih->ih_pil)); 767 768 intr_establish(ih->ih_pil, level != IPL_VM, ih); 769 770 /* 771 * Enable the interrupt now we have the handler installed. 772 * Read the current value as we can't change it besides the 773 * valid bit so so make sure only this bit is changed. 774 */ 775 if (intrmapptr) { 776 u_int64_t imap; 777 778 imap = schizo_pbm_readintr(pbm, mapoff); 779 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 780 (unsigned long long)imap)); 781 imap |= INTMAP_V; 782 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 783 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 784 (unsigned long long)imap)); 785 schizo_pbm_writeintr(pbm, mapoff, imap); 786 imap = schizo_pbm_readintr(pbm, mapoff); 787 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 788 (unsigned long long)imap)); 789 ih->ih_number |= imap & INTMAP_INR; 790 } 791 if (intrclrptr) { 792 /* set state to IDLE */ 793 schizo_pbm_writeintr(pbm, clroff, 0); 794 } 795 796 return (ih); 797 } 798 799 static void * 800 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 801 int (*func)(void *), void *arg) 802 { 803 void *cookie; 804 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 805 806 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 807 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 808 809 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 810 return (cookie); 811 } 812 813 static int 814 schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 815 { 816 #if 0 817 struct schizo_pbm *pbm = pa->pa_pc->cookie; 818 struct schizo_softc *sc = pbm->sp_sc; 819 u_int bus; 820 u_int dev; 821 u_int pin; 822 #endif 823 824 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 825 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 826 (int)PCITAG_DEV(pa->pa_tag), 827 (int)PCITAG_FUN(pa->pa_tag))); 828 DPRINTF(SDB_INTMAP, 829 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 830 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 831 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 832 PCITAG_NODE(pa->pa_intrtag), 833 (int)PCITAG_BUS(pa->pa_intrtag), 834 (int)PCITAG_DEV(pa->pa_intrtag), 835 (int)PCITAG_FUN(pa->pa_intrtag))); 836 837 #if 0 838 bus = (pp->pp_id == PSYCHO_PBM_B); 839 /* 840 * If we are on a ppb, use the devno on the underlying bus when forming 841 * the ivec. 842 */ 843 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 844 dev = PCITAG_DEV(pa->pa_intrtag); 845 else 846 dev = pa->pa_device; 847 dev--; 848 849 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 850 pp->pp_id == PSYCHO_PBM_B) 851 dev--; 852 853 pin = pa->pa_intrpin - 1; 854 DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 855 sc->sc_mode, pp->pp_id, dev, pin)); 856 857 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 858 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 859 #endif 860 861 return (0); 862 } 863
Indexes created Tue Sep 30 20:09:53 GMT 2025