schizo.c revision 1.15
1 /* $NetBSD: schizo.c,v 1.15 2010/03/11 03:30:16 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/extent.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/time.h> 38 #include <sys/reboot.h> 39 40 #define _SPARC_BUS_DMA_PRIVATE 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/psl.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <sparc64/dev/iommureg.h> 49 #include <sparc64/dev/iommuvar.h> 50 #include <sparc64/dev/schizoreg.h> 51 #include <sparc64/dev/schizovar.h> 52 #include <sparc64/sparc64/cache.h> 53 54 #ifdef DEBUG 55 #define SDB_PROM 0x01 56 #define SDB_BUSMAP 0x02 57 #define SDB_INTR 0x04 58 #define SDB_INTMAP 0x08 59 #define SDB_CONF 0x10 60 int schizo_debug = 0x0; 61 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 62 #else 63 #define DPRINTF(l, s) 64 #endif 65 66 extern struct sparc_pci_chipset _sparc_pci_chipset; 67 68 static int schizo_match(struct device *, struct cfdata *, void *); 69 static void schizo_attach(struct device *, struct device *, void *); 70 static int schizo_print(void *aux, const char *p); 71 72 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 73 schizo_match, schizo_attach, NULL, NULL); 74 75 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 76 77 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 78 int (*handler)(void *), void *, int, const char *); 79 int schizo_ue(void *); 80 int schizo_ce(void *); 81 int schizo_safari_error(void *); 82 int schizo_pci_error(void *); 83 84 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 85 pci_chipset_tag_t); 86 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 87 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 90 int); 91 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 92 93 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 94 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 95 96 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 97 int flags, vaddr_t unused, bus_space_handle_t *hp); 98 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 99 off_t off, int prot, int flags); 100 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 101 void *, void(*)(void)); 102 static int schizo_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 103 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 104 int, int (*)(void *), void *); 105 static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 106 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 107 bus_size_t, int, bus_dmamap_t *); 108 109 int 110 schizo_match(struct device *parent, struct cfdata *match, void *aux) 111 { 112 struct mainbus_attach_args *ma = aux; 113 char *str; 114 115 if (strcmp(ma->ma_name, "pci") != 0) 116 return (0); 117 118 str = prom_getpropstring(ma->ma_node, "model"); 119 if (strcmp(str, "schizo") == 0) 120 return (1); 121 122 str = prom_getpropstring(ma->ma_node, "compatible"); 123 if (strcmp(str, "pci108e,8001") == 0) 124 return (1); 125 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 126 return (1); 127 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 128 return (1); 129 130 return (0); 131 } 132 133 void 134 schizo_attach(struct device *parent, struct device *self, void *aux) 135 { 136 struct schizo_softc *sc = (struct schizo_softc *)self; 137 struct mainbus_attach_args *ma = aux; 138 struct schizo_pbm *pbm; 139 struct iommu_state *is; 140 struct pcibus_attach_args pba; 141 uint64_t reg, eccctrl; 142 int *busranges = NULL, nranges; 143 char *str; 144 145 printf(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 146 str = prom_getpropstring(ma->ma_node, "compatible"); 147 if (strcmp(str, "pci108e,a801") == 0) 148 sc->sc_tomatillo = 1; 149 150 sc->sc_node = ma->ma_node; 151 sc->sc_dmat = ma->ma_dmatag; 152 sc->sc_bustag = ma->ma_bustag; 153 154 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 155 sizeof(struct schizo_regs), 0, 156 &sc->sc_ctrlh)) { 157 printf(": failed to map registers\n"); 158 return; 159 } 160 161 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 162 163 /* enable schizo ecc error interrupts */ 164 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 165 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 166 SCZ_ECCCTRL_UE_INTEN | 167 SCZ_ECCCTRL_CE_INTEN; 168 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 169 170 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 171 if (pbm == NULL) 172 panic("schizo: can't alloc schizo pbm"); 173 174 pbm->sp_sc = sc; 175 pbm->sp_regt = sc->sc_bustag; 176 177 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 178 pbm->sp_bus_a = 1; 179 else 180 pbm->sp_bus_a = 0; 181 182 /* 183 * Map interrupt registers 184 */ 185 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 186 ma->ma_reg[0].ur_len, 187 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 188 printf(": failed to interrupt map registers\n"); 189 return; 190 } 191 192 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 193 &pbm->sp_nrange, (void **)&pbm->sp_range)) 194 panic("schizo: can't get ranges"); 195 196 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 197 (void **)&busranges)) 198 panic("schizo: can't get bus-range"); 199 200 printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 201 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 202 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 203 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 204 205 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 206 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 207 offsetof(struct schizo_regs, pbm_b), 208 sizeof(struct schizo_pbm_regs), 209 &pbm->sp_regh)) { 210 panic("schizo: unable to create PBM handle"); 211 } 212 213 is = &pbm->sp_is; 214 pbm->sp_sb.sb_is = is; 215 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 216 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 217 218 /* 219 * Initialize the strbuf_ctl. 220 * 221 * The flush sync buffer must be 64-byte aligned. 222 */ 223 is->is_sb[0] = &pbm->sp_sb; 224 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 225 226 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 227 offsetof(struct schizo_pbm_regs, strbuf), 228 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 229 } else { 230 aprint_debug("%s: no streaming buffers\n", sc->sc_dv.dv_xname); 231 } 232 233 printf("%s: ", sc->sc_dv.dv_xname); 234 schizo_init_iommu(sc, pbm); 235 236 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 237 pbm->sp_iot = schizo_alloc_io_tag(pbm); 238 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 239 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 240 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 241 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 242 243 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 244 panic("schizo: could not map config space"); 245 246 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 247 &_sparc_pci_chipset); 248 pbm->sp_pc->spc_busmax = busranges[1]; 249 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 250 M_DEVBUF, M_NOWAIT | M_ZERO); 251 if (pbm->sp_pc->spc_busnode == NULL) 252 panic("schizo: malloc busnode"); 253 254 pba.pba_bus = busranges[0]; 255 pba.pba_bridgetag = NULL; 256 pba.pba_pc = pbm->sp_pc; 257 pba.pba_flags = pbm->sp_flags; 258 pba.pba_dmat = pbm->sp_dmat; 259 pba.pba_dmat64 = NULL; /* XXX */ 260 pba.pba_memt = pbm->sp_memt; 261 pba.pba_iot = pbm->sp_iot; 262 263 free(busranges, M_DEVBUF); 264 265 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 266 267 /* clear out the bus errors */ 268 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 269 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 270 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 271 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 272 273 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 274 /* enable/disable error interrupts and arbiter */ 275 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 276 reg &= ~SCZ_PCICTRL_SBH_INT; 277 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 278 279 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 280 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 281 SCZ_PCIDIAG_D_INTSYNC); 282 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 283 284 if (pbm->sp_bus_a) 285 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 286 pbm, SCZ_PCIERR_A_INO, "pci_a"); 287 else 288 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 289 pbm, SCZ_PCIERR_B_INO, "pci_b"); 290 291 /* double mapped */ 292 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 293 "ue"); 294 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 295 "ce"); 296 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 297 SCZ_SERR_INO, "safari"); 298 299 config_found(&sc->sc_dv, &pba, schizo_print); 300 } 301 302 int 303 schizo_ue(void *vsc) 304 { 305 struct schizo_softc *sc = vsc; 306 307 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 308 return (1); 309 } 310 311 int 312 schizo_ce(void *vsc) 313 { 314 struct schizo_softc *sc = vsc; 315 316 panic("%s: correctable error", sc->sc_dv.dv_xname); 317 return (1); 318 } 319 320 int 321 schizo_pci_error(void *vpbm) 322 { 323 struct schizo_pbm *sp = vpbm; 324 struct schizo_softc *sc = sp->sp_sc; 325 u_int64_t afsr, afar, ctrl, tfar; 326 u_int32_t csr; 327 char bits[128]; 328 329 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 330 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 331 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 332 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 333 334 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 335 sp->sp_bus_a ? 'A' : 'B'); 336 337 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 338 printf("PCIAFSR=%s\n", bits); 339 printf("PCIAFAR=%" PRIx64 "\n", afar); 340 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 341 printf("PCICTRL=%s\n", bits); 342 #ifdef PCI_COMMAND_STATUS_BITS 343 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 344 printf("PCICSR=%s\n", bits); 345 #endif 346 347 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 348 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 349 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 350 351 if ((ctrl & TOM_IOMMU_ERR) == 0) 352 goto clear_error; 353 354 if (sc->sc_tomatillo) { 355 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 356 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 357 } 358 359 /* These are non-fatal if target abort was signalled. */ 360 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 361 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 362 ctrl & TOM_IOMMU_BADVA_ERR) { 363 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 364 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 365 goto clear_error; 366 } 367 } 368 } 369 370 panic("%s: fatal", sc->sc_dv.dv_xname); 371 372 clear_error: 373 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 374 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 375 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 376 return (1); 377 } 378 379 int 380 schizo_safari_error(void *vsc) 381 { 382 struct schizo_softc *sc = vsc; 383 384 printf("%s: safari error\n", sc->sc_dv.dv_xname); 385 386 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 387 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 388 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 389 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 390 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 391 392 panic("%s: fatal", sc->sc_dv.dv_xname); 393 return (1); 394 } 395 396 void 397 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 398 { 399 struct iommu_state *is = &pbm->sp_is; 400 int *vdma = NULL, nitem, tsbsize = 7; 401 u_int32_t iobase = -1; 402 char *name; 403 404 /* punch in our copies */ 405 is->is_bustag = pbm->sp_regt; 406 bus_space_subregion(is->is_bustag, pbm->sp_regh, 407 offsetof(struct schizo_pbm_regs, iommu), 408 sizeof(struct schizo_iommureg), 409 &is->is_iommu); 410 411 /* 412 * Separate the men from the boys. If the `virtual-dma' 413 * property exists, use it. 414 */ 415 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 416 (void **)&vdma)) { 417 /* Damn. Gotta use these values. */ 418 iobase = vdma[0]; 419 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 420 switch (vdma[1]) { 421 TSBCASE(1); TSBCASE(2); TSBCASE(3); 422 TSBCASE(4); TSBCASE(5); TSBCASE(6); 423 default: 424 printf("bogus tsb size %x, using 7\n", vdma[1]); 425 TSBCASE(7); 426 } 427 #undef TSBCASE 428 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 429 free(vdma, M_DEVBUF); 430 } else { 431 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 432 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 433 } 434 435 /* give us a nice name.. */ 436 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 437 if (name == NULL) 438 panic("couldn't malloc iommu name"); 439 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 440 441 iommu_init(name, is, tsbsize, iobase); 442 } 443 444 int 445 schizo_print(void *aux, const char *p) 446 { 447 448 if (p == NULL) 449 return (UNCONF); 450 return (QUIET); 451 } 452 453 pcireg_t 454 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 455 { 456 struct schizo_pbm *sp = pc->cookie; 457 pcireg_t val = (pcireg_t)~0; 458 459 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 460 if (PCITAG_NODE(tag) != -1) 461 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 462 PCITAG_OFFSET(tag) + reg); 463 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 464 return (val); 465 } 466 467 void 468 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 469 { 470 struct schizo_pbm *sp = pc->cookie; 471 472 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 473 (long)tag, reg, (int)data)); 474 475 /* If we don't know it, just punt it. */ 476 if (PCITAG_NODE(tag) == -1) { 477 DPRINTF(SDB_CONF, (" .. bad addr\n")); 478 return; 479 } 480 481 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 482 PCITAG_OFFSET(tag) + reg, data); 483 DPRINTF(SDB_CONF, (" .. done\n")); 484 } 485 486 void 487 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 488 int (*handler)(void *), void *arg, int ino, const char *what) 489 { 490 struct intrhand *ih; 491 u_int64_t mapoff, clroff; 492 uintptr_t intrregs; 493 494 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 495 ino, sc->sc_ign, handler, arg)); 496 497 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 498 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 499 ino |= sc->sc_ign; 500 501 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 502 mapoff, clroff)); 503 504 ih = (struct intrhand *) 505 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 506 if (ih == NULL) 507 return; 508 ih->ih_arg = arg; 509 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 510 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 511 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 512 ih->ih_fun = handler; 513 ih->ih_pil = (1<<ipl); 514 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 515 intr_establish(ipl, ipl != IPL_VM, ih); 516 517 schizo_pbm_write(pbm, mapoff, 518 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 519 } 520 521 bus_space_tag_t 522 schizo_alloc_mem_tag(struct schizo_pbm *sp) 523 { 524 return (schizo_alloc_bus_tag(sp, "mem", 525 PCI_MEMORY_BUS_SPACE)); 526 } 527 528 bus_space_tag_t 529 schizo_alloc_io_tag(struct schizo_pbm *sp) 530 { 531 return (schizo_alloc_bus_tag(sp, "io", 532 PCI_IO_BUS_SPACE)); 533 } 534 535 bus_space_tag_t 536 schizo_alloc_config_tag(struct schizo_pbm *sp) 537 { 538 return (schizo_alloc_bus_tag(sp, "cfg", 539 PCI_CONFIG_BUS_SPACE)); 540 } 541 542 bus_space_tag_t 543 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 544 { 545 struct schizo_softc *sc = pbm->sp_sc; 546 bus_space_tag_t bt; 547 548 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 549 M_DEVBUF, M_NOWAIT | M_ZERO); 550 if (bt == NULL) 551 panic("schizo: could not allocate bus tag"); 552 553 bt->cookie = pbm; 554 bt->parent = sc->sc_bustag; 555 bt->type = type; 556 bt->sparc_bus_map = schizo_bus_map; 557 bt->sparc_bus_mmap = schizo_bus_mmap; 558 bt->sparc_intr_establish = schizo_intr_establish; 559 return (bt); 560 } 561 562 bus_dma_tag_t 563 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 564 { 565 struct schizo_softc *sc = pbm->sp_sc; 566 bus_dma_tag_t dt, pdt = sc->sc_dmat; 567 568 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 569 if (dt == NULL) 570 panic("schizo: could not alloc dma tag"); 571 572 dt->_cookie = pbm; 573 dt->_parent = pdt; 574 #define PCOPY(x) dt->x = pdt->x 575 dt->_dmamap_create = schizo_dmamap_create; 576 PCOPY(_dmamap_destroy); 577 dt->_dmamap_load = iommu_dvmamap_load; 578 PCOPY(_dmamap_load_mbuf); 579 PCOPY(_dmamap_load_uio); 580 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 581 dt->_dmamap_unload = iommu_dvmamap_unload; 582 dt->_dmamap_sync = iommu_dvmamap_sync; 583 dt->_dmamem_alloc = iommu_dvmamem_alloc; 584 dt->_dmamem_free = iommu_dvmamem_free; 585 dt->_dmamem_map = iommu_dvmamem_map; 586 dt->_dmamem_unmap = iommu_dvmamem_unmap; 587 PCOPY(_dmamem_mmap); 588 #undef PCOPY 589 return (dt); 590 } 591 592 pci_chipset_tag_t 593 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 594 { 595 pci_chipset_tag_t npc; 596 597 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 598 if (npc == NULL) 599 panic("schizo: could not allocate pci_chipset_tag_t"); 600 memcpy(npc, pc, sizeof *pc); 601 npc->cookie = pbm; 602 npc->rootnode = node; 603 npc->spc_conf_read = schizo_conf_read; 604 npc->spc_conf_write = schizo_conf_write; 605 npc->spc_intr_map = schizo_pci_intr_map; 606 npc->spc_intr_establish = schizo_pci_intr_establish; 607 npc->spc_find_ino = schizo_pci_find_ino; 608 return (npc); 609 } 610 611 int 612 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 613 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 614 bus_dmamap_t *dmamp) 615 { 616 struct schizo_pbm *pbm = t->_cookie; 617 int error; 618 619 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 620 boundary, flags, dmamp); 621 if (error == 0) 622 (*dmamp)->_dm_cookie = &pbm->sp_sb; 623 return error; 624 } 625 626 static struct schizo_range * 627 get_schizorange(struct schizo_pbm *pbm, int ss) 628 { 629 int i; 630 631 for (i = 0; i < pbm->sp_nrange; i++) { 632 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 633 return (&pbm->sp_range[i]); 634 } 635 /* not found */ 636 return (NULL); 637 } 638 639 int 640 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 641 int flags, vaddr_t unused, bus_space_handle_t *hp) 642 { 643 bus_addr_t paddr; 644 struct schizo_pbm *pbm = t->cookie; 645 struct schizo_softc *sc = pbm->sp_sc; 646 struct schizo_range *sr; 647 int ss; 648 649 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 650 t->type, 651 (unsigned long long)offset, 652 (unsigned long long)size, 653 flags)); 654 655 ss = sparc_pci_childspace(t->type); 656 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 657 658 sr = get_schizorange(pbm, ss); 659 if (sr != NULL) { 660 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 661 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 662 "space %lx offset %lx paddr %qx\n", 663 __func__, (long)ss, (long)offset, 664 (unsigned long long)paddr)); 665 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 666 flags, 0, hp)); 667 } 668 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 669 return (EINVAL); 670 } 671 672 static paddr_t 673 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 674 int flags) 675 { 676 bus_addr_t offset = paddr; 677 struct schizo_pbm *pbm = t->cookie; 678 struct schizo_softc *sc = pbm->sp_sc; 679 struct schizo_range *sr; 680 int ss; 681 682 ss = sparc_pci_childspace(t->type); 683 684 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 685 prot, flags, (unsigned long long)paddr)); 686 687 sr = get_schizorange(pbm, ss); 688 if (sr != NULL) { 689 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 690 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 691 "space %lx offset %lx paddr %qx\n", 692 __func__, (long)ss, (long)offset, 693 (unsigned long long)paddr)); 694 return (bus_space_mmap(sc->sc_bustag, paddr, off, 695 prot, flags)); 696 } 697 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 698 return (-1); 699 } 700 701 /* 702 * Set the IGN for this schizo into the handle. 703 */ 704 int 705 schizo_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 706 { 707 struct schizo_pbm *pbm = pa->pa_pc->cookie; 708 struct schizo_softc *sc = pbm->sp_sc; 709 710 *ihp |= sc->sc_ign; 711 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 712 return (0); 713 } 714 715 static void * 716 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 717 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 718 { 719 struct schizo_pbm *pbm = t->cookie; 720 struct intrhand *ih = NULL; 721 uint64_t mapoff, clroff; 722 uintptr_t intrregs; 723 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 724 int ino; 725 long vec; 726 727 vec = INTVEC(ihandle); 728 ino = INTINO(vec); 729 730 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 731 if (ih == NULL) 732 return (NULL); 733 734 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 735 ihandle, level, handler, arg)); 736 737 if (level == IPL_NONE) 738 level = INTLEV(vec); 739 if (level == IPL_NONE) { 740 printf(": no IPL, setting IPL 2.\n"); 741 level = 2; 742 } 743 744 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 745 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 746 747 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 748 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 749 750 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 751 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 752 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 753 754 if (INTIGN(vec) == 0) 755 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 756 else 757 ino |= vec & INTMAP_IGN; 758 759 /* Register the map and clear intr registers */ 760 ih->ih_map = intrmapptr; 761 ih->ih_clr = intrclrptr; 762 763 ih->ih_fun = handler; 764 ih->ih_arg = arg; 765 ih->ih_pil = level; 766 ih->ih_number = ino; 767 768 DPRINTF(SDB_INTR, ( 769 "; installing handler %p arg %p with inr %x pil %u\n", 770 handler, arg, ino, (u_int)ih->ih_pil)); 771 772 intr_establish(ih->ih_pil, level != IPL_VM, ih); 773 774 /* 775 * Enable the interrupt now we have the handler installed. 776 * Read the current value as we can't change it besides the 777 * valid bit so so make sure only this bit is changed. 778 */ 779 if (intrmapptr) { 780 u_int64_t imap; 781 782 imap = schizo_pbm_readintr(pbm, mapoff); 783 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 784 (unsigned long long)imap)); 785 imap |= INTMAP_V; 786 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 787 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 788 (unsigned long long)imap)); 789 schizo_pbm_writeintr(pbm, mapoff, imap); 790 imap = schizo_pbm_readintr(pbm, mapoff); 791 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 792 (unsigned long long)imap)); 793 ih->ih_number |= imap & INTMAP_INR; 794 } 795 if (intrclrptr) { 796 /* set state to IDLE */ 797 schizo_pbm_writeintr(pbm, clroff, 0); 798 } 799 800 return (ih); 801 } 802 803 static void * 804 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 805 int (*func)(void *), void *arg) 806 { 807 void *cookie; 808 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 809 810 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 811 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 812 813 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 814 return (cookie); 815 } 816 817 static int 818 schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 819 { 820 #if 0 821 struct schizo_pbm *pbm = pa->pa_pc->cookie; 822 struct schizo_softc *sc = pbm->sp_sc; 823 u_int bus; 824 u_int dev; 825 u_int pin; 826 #endif 827 828 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 829 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 830 (int)PCITAG_DEV(pa->pa_tag), 831 (int)PCITAG_FUN(pa->pa_tag))); 832 DPRINTF(SDB_INTMAP, 833 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 834 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 835 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 836 PCITAG_NODE(pa->pa_intrtag), 837 (int)PCITAG_BUS(pa->pa_intrtag), 838 (int)PCITAG_DEV(pa->pa_intrtag), 839 (int)PCITAG_FUN(pa->pa_intrtag))); 840 841 #if 0 842 bus = (pp->pp_id == PSYCHO_PBM_B); 843 /* 844 * If we are on a ppb, use the devno on the underlying bus when forming 845 * the ivec. 846 */ 847 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 848 dev = PCITAG_DEV(pa->pa_intrtag); 849 else 850 dev = pa->pa_device; 851 dev--; 852 853 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 854 pp->pp_id == PSYCHO_PBM_B) 855 dev--; 856 857 pin = pa->pa_intrpin - 1; 858 DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 859 sc->sc_mode, pp->pp_id, dev, pin)); 860 861 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 862 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 863 #endif 864 865 return (0); 866 } 867
Indexes created Tue Sep 30 20:09:53 GMT 2025