schizo.c revision 1.18
1 /* $NetBSD: schizo.c,v 1.18 2011/03/20 20:43:34 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/errno.h> 35 #include <sys/extent.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 #include <sys/reboot.h> 40 41 #define _SPARC_BUS_DMA_PRIVATE 42 #include <machine/bus.h> 43 #include <machine/autoconf.h> 44 #include <machine/psl.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <sparc64/dev/iommureg.h> 50 #include <sparc64/dev/iommuvar.h> 51 #include <sparc64/dev/schizoreg.h> 52 #include <sparc64/dev/schizovar.h> 53 #include <sparc64/sparc64/cache.h> 54 55 #ifdef DEBUG 56 #define SDB_PROM 0x01 57 #define SDB_BUSMAP 0x02 58 #define SDB_INTR 0x04 59 #define SDB_INTMAP 0x08 60 #define SDB_CONF 0x10 61 int schizo_debug = 0x0; 62 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 63 #else 64 #define DPRINTF(l, s) 65 #endif 66 67 extern struct sparc_pci_chipset _sparc_pci_chipset; 68 69 static int schizo_match(struct device *, struct cfdata *, void *); 70 static void schizo_attach(struct device *, struct device *, void *); 71 static int schizo_print(void *aux, const char *p); 72 73 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 74 schizo_match, schizo_attach, NULL, NULL); 75 76 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 77 78 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 79 int (*handler)(void *), void *, int, const char *); 80 int schizo_ue(void *); 81 int schizo_ce(void *); 82 int schizo_safari_error(void *); 83 int schizo_pci_error(void *); 84 85 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 86 pci_chipset_tag_t); 87 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 91 int); 92 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 93 94 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 97 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 98 int flags, vaddr_t unused, bus_space_handle_t *hp); 99 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 100 off_t off, int prot, int flags); 101 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 102 void *, void(*)(void)); 103 static int schizo_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 104 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 105 int, int (*)(void *), void *); 106 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 107 bus_size_t, int, bus_dmamap_t *); 108 109 int 110 schizo_match(struct device *parent, struct cfdata *match, void *aux) 111 { 112 struct mainbus_attach_args *ma = aux; 113 char *str; 114 115 if (strcmp(ma->ma_name, "pci") != 0) 116 return (0); 117 118 str = prom_getpropstring(ma->ma_node, "model"); 119 if (strcmp(str, "schizo") == 0) 120 return (1); 121 122 str = prom_getpropstring(ma->ma_node, "compatible"); 123 if (strcmp(str, "pci108e,8001") == 0) 124 return (1); 125 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 126 return (1); 127 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 128 return (1); 129 130 return (0); 131 } 132 133 void 134 schizo_attach(struct device *parent, struct device *self, void *aux) 135 { 136 struct schizo_softc *sc = (struct schizo_softc *)self; 137 struct mainbus_attach_args *ma = aux; 138 struct schizo_pbm *pbm; 139 struct iommu_state *is; 140 struct pcibus_attach_args pba; 141 uint64_t reg, eccctrl; 142 int *busranges = NULL, nranges; 143 char *str; 144 bool no_sc; 145 146 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 147 str = prom_getpropstring(ma->ma_node, "compatible"); 148 if (strcmp(str, "pci108e,a801") == 0) 149 sc->sc_tomatillo = 1; 150 151 sc->sc_node = ma->ma_node; 152 sc->sc_dmat = ma->ma_dmatag; 153 sc->sc_bustag = ma->ma_bustag; 154 155 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 156 sizeof(struct schizo_regs), 0, 157 &sc->sc_ctrlh)) { 158 aprint_error(": failed to map registers\n"); 159 return; 160 } 161 162 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 163 164 /* enable schizo ecc error interrupts */ 165 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 166 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 167 SCZ_ECCCTRL_UE_INTEN | 168 SCZ_ECCCTRL_CE_INTEN; 169 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 170 171 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 172 if (pbm == NULL) 173 panic("schizo: can't alloc schizo pbm"); 174 175 pbm->sp_sc = sc; 176 pbm->sp_regt = sc->sc_bustag; 177 178 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 179 pbm->sp_bus_a = 1; 180 else 181 pbm->sp_bus_a = 0; 182 183 /* 184 * Map interrupt registers 185 */ 186 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 187 ma->ma_reg[0].ur_len, 188 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 189 aprint_error(": failed to interrupt map registers\n"); 190 return; 191 } 192 193 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 194 &pbm->sp_nrange, (void **)&pbm->sp_range)) 195 panic("schizo: can't get ranges"); 196 197 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 198 (void **)&busranges)) 199 panic("schizo: can't get bus-range"); 200 201 aprint_normal(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 202 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 203 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 204 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 205 aprint_naive("\n"); 206 207 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 208 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 209 offsetof(struct schizo_regs, pbm_b), 210 sizeof(struct schizo_pbm_regs), 211 &pbm->sp_regh)) { 212 panic("schizo: unable to create PBM handle"); 213 } 214 215 is = &pbm->sp_is; 216 pbm->sp_sb.sb_is = is; 217 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 218 if (no_sc) 219 aprint_debug("%s: no streaming buffers\n", sc->sc_dv.dv_xname); 220 else { 221 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 222 223 /* 224 * Initialize the strbuf_ctl. 225 * 226 * The flush sync buffer must be 64-byte aligned. 227 */ 228 is->is_sb[0] = &pbm->sp_sb; 229 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 230 231 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 232 offsetof(struct schizo_pbm_regs, strbuf), 233 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 234 } 235 236 aprint_normal("%s: ", sc->sc_dv.dv_xname); 237 schizo_init_iommu(sc, pbm); 238 239 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 240 pbm->sp_iot = schizo_alloc_io_tag(pbm); 241 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 242 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 243 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 244 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 245 246 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 247 panic("schizo: could not map config space"); 248 249 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 250 &_sparc_pci_chipset); 251 pbm->sp_pc->spc_busmax = busranges[1]; 252 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 253 M_DEVBUF, M_NOWAIT | M_ZERO); 254 if (pbm->sp_pc->spc_busnode == NULL) 255 panic("schizo: malloc busnode"); 256 257 pba.pba_bus = busranges[0]; 258 pba.pba_bridgetag = NULL; 259 pba.pba_pc = pbm->sp_pc; 260 pba.pba_flags = pbm->sp_flags; 261 pba.pba_dmat = pbm->sp_dmat; 262 pba.pba_dmat64 = NULL; /* XXX */ 263 pba.pba_memt = pbm->sp_memt; 264 pba.pba_iot = pbm->sp_iot; 265 266 free(busranges, M_DEVBUF); 267 268 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 269 270 /* clear out the bus errors */ 271 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 272 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 273 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 274 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 275 276 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 277 /* enable/disable error interrupts and arbiter */ 278 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 279 reg &= ~SCZ_PCICTRL_SBH_INT; 280 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 281 282 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 283 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 284 SCZ_PCIDIAG_D_INTSYNC); 285 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 286 287 if (pbm->sp_bus_a) 288 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 289 pbm, SCZ_PCIERR_A_INO, "pci_a"); 290 else 291 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 292 pbm, SCZ_PCIERR_B_INO, "pci_b"); 293 294 /* double mapped */ 295 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 296 "ue"); 297 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 298 "ce"); 299 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 300 SCZ_SERR_INO, "safari"); 301 302 if (sc->sc_tomatillo) { 303 /* 304 * Enable the IOCACHE. 305 */ 306 uint64_t iocache_csr; 307 308 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 309 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 310 TOM_IOCACHE_CSR_PEN_RDM | 311 TOM_IOCACHE_CSR_PEN_ONE | 312 TOM_IOCACHE_CSR_PEN_LINE; 313 314 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 315 } 316 317 config_found(&sc->sc_dv, &pba, schizo_print); 318 } 319 320 int 321 schizo_ue(void *vsc) 322 { 323 struct schizo_softc *sc = vsc; 324 325 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 326 return (1); 327 } 328 329 int 330 schizo_ce(void *vsc) 331 { 332 struct schizo_softc *sc = vsc; 333 334 panic("%s: correctable error", sc->sc_dv.dv_xname); 335 return (1); 336 } 337 338 int 339 schizo_pci_error(void *vpbm) 340 { 341 struct schizo_pbm *sp = vpbm; 342 struct schizo_softc *sc = sp->sp_sc; 343 u_int64_t afsr, afar, ctrl, tfar; 344 u_int32_t csr; 345 char bits[128]; 346 347 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 348 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 349 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 350 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 351 352 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 353 sp->sp_bus_a ? 'A' : 'B'); 354 355 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 356 printf("PCIAFSR=%s\n", bits); 357 printf("PCIAFAR=%" PRIx64 "\n", afar); 358 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 359 printf("PCICTRL=%s\n", bits); 360 #ifdef PCI_COMMAND_STATUS_BITS 361 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 362 printf("PCICSR=%s\n", bits); 363 #endif 364 365 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 366 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 367 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 368 369 if ((ctrl & TOM_IOMMU_ERR) == 0) 370 goto clear_error; 371 372 if (sc->sc_tomatillo) { 373 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 374 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 375 } 376 377 /* These are non-fatal if target abort was signalled. */ 378 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 379 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 380 ctrl & TOM_IOMMU_BADVA_ERR) { 381 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 382 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 383 goto clear_error; 384 } 385 } 386 } 387 388 panic("%s: fatal", sc->sc_dv.dv_xname); 389 390 clear_error: 391 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 392 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 393 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 394 return (1); 395 } 396 397 int 398 schizo_safari_error(void *vsc) 399 { 400 struct schizo_softc *sc = vsc; 401 402 printf("%s: safari error\n", sc->sc_dv.dv_xname); 403 404 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 405 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 406 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 407 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 408 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 409 410 panic("%s: fatal", sc->sc_dv.dv_xname); 411 return (1); 412 } 413 414 void 415 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 416 { 417 struct iommu_state *is = &pbm->sp_is; 418 int *vdma = NULL, nitem, tsbsize = 7; 419 u_int32_t iobase = -1; 420 char *name; 421 422 /* punch in our copies */ 423 is->is_bustag = pbm->sp_regt; 424 bus_space_subregion(is->is_bustag, pbm->sp_regh, 425 offsetof(struct schizo_pbm_regs, iommu), 426 sizeof(struct iommureg2), 427 &is->is_iommu); 428 429 /* 430 * Separate the men from the boys. If the `virtual-dma' 431 * property exists, use it. 432 */ 433 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 434 (void **)&vdma)) { 435 /* Damn. Gotta use these values. */ 436 iobase = vdma[0]; 437 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 438 switch (vdma[1]) { 439 TSBCASE(1); TSBCASE(2); TSBCASE(3); 440 TSBCASE(4); TSBCASE(5); TSBCASE(6); 441 default: 442 printf("bogus tsb size %x, using 7\n", vdma[1]); 443 TSBCASE(7); 444 } 445 #undef TSBCASE 446 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 447 free(vdma, M_DEVBUF); 448 } else { 449 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 450 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 451 } 452 453 /* give us a nice name.. */ 454 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 455 if (name == NULL) 456 panic("couldn't malloc iommu name"); 457 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 458 459 iommu_init(name, is, tsbsize, iobase); 460 } 461 462 int 463 schizo_print(void *aux, const char *p) 464 { 465 466 if (p == NULL) 467 return (UNCONF); 468 return (QUIET); 469 } 470 471 pcireg_t 472 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 473 { 474 struct schizo_pbm *sp = pc->cookie; 475 pcireg_t val = (pcireg_t)~0; 476 477 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 478 if (PCITAG_NODE(tag) != -1) 479 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 480 PCITAG_OFFSET(tag) + reg); 481 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 482 return (val); 483 } 484 485 void 486 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 487 { 488 struct schizo_pbm *sp = pc->cookie; 489 490 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 491 (long)tag, reg, (int)data)); 492 493 /* If we don't know it, just punt it. */ 494 if (PCITAG_NODE(tag) == -1) { 495 DPRINTF(SDB_CONF, (" .. bad addr\n")); 496 return; 497 } 498 499 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 500 PCITAG_OFFSET(tag) + reg, data); 501 DPRINTF(SDB_CONF, (" .. done\n")); 502 } 503 504 void 505 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 506 int (*handler)(void *), void *arg, int ino, const char *what) 507 { 508 struct intrhand *ih; 509 u_int64_t mapoff, clroff; 510 uintptr_t intrregs; 511 512 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 513 ino, sc->sc_ign, handler, arg)); 514 515 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 516 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 517 ino |= sc->sc_ign; 518 519 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 520 mapoff, clroff)); 521 522 ih = (struct intrhand *) 523 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 524 if (ih == NULL) 525 return; 526 ih->ih_arg = arg; 527 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 528 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 529 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 530 ih->ih_fun = handler; 531 ih->ih_pil = (1<<ipl); 532 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 533 intr_establish(ipl, ipl != IPL_VM, ih); 534 535 schizo_pbm_write(pbm, mapoff, 536 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 537 } 538 539 bus_space_tag_t 540 schizo_alloc_mem_tag(struct schizo_pbm *sp) 541 { 542 return (schizo_alloc_bus_tag(sp, "mem", 543 PCI_MEMORY_BUS_SPACE)); 544 } 545 546 bus_space_tag_t 547 schizo_alloc_io_tag(struct schizo_pbm *sp) 548 { 549 return (schizo_alloc_bus_tag(sp, "io", 550 PCI_IO_BUS_SPACE)); 551 } 552 553 bus_space_tag_t 554 schizo_alloc_config_tag(struct schizo_pbm *sp) 555 { 556 return (schizo_alloc_bus_tag(sp, "cfg", 557 PCI_CONFIG_BUS_SPACE)); 558 } 559 560 bus_space_tag_t 561 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 562 { 563 struct schizo_softc *sc = pbm->sp_sc; 564 bus_space_tag_t bt; 565 566 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 567 M_DEVBUF, M_NOWAIT | M_ZERO); 568 if (bt == NULL) 569 panic("schizo: could not allocate bus tag"); 570 571 bt->cookie = pbm; 572 bt->parent = sc->sc_bustag; 573 bt->type = type; 574 bt->sparc_bus_map = schizo_bus_map; 575 bt->sparc_bus_mmap = schizo_bus_mmap; 576 bt->sparc_intr_establish = schizo_intr_establish; 577 return (bt); 578 } 579 580 bus_dma_tag_t 581 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 582 { 583 struct schizo_softc *sc = pbm->sp_sc; 584 bus_dma_tag_t dt, pdt = sc->sc_dmat; 585 586 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 587 if (dt == NULL) 588 panic("schizo: could not alloc dma tag"); 589 590 dt->_cookie = pbm; 591 dt->_parent = pdt; 592 #define PCOPY(x) dt->x = pdt->x 593 dt->_dmamap_create = schizo_dmamap_create; 594 PCOPY(_dmamap_destroy); 595 dt->_dmamap_load = iommu_dvmamap_load; 596 PCOPY(_dmamap_load_mbuf); 597 PCOPY(_dmamap_load_uio); 598 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 599 dt->_dmamap_unload = iommu_dvmamap_unload; 600 dt->_dmamap_sync = iommu_dvmamap_sync; 601 dt->_dmamem_alloc = iommu_dvmamem_alloc; 602 dt->_dmamem_free = iommu_dvmamem_free; 603 dt->_dmamem_map = iommu_dvmamem_map; 604 dt->_dmamem_unmap = iommu_dvmamem_unmap; 605 PCOPY(_dmamem_mmap); 606 #undef PCOPY 607 return (dt); 608 } 609 610 pci_chipset_tag_t 611 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 612 { 613 pci_chipset_tag_t npc; 614 615 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 616 if (npc == NULL) 617 panic("schizo: could not allocate pci_chipset_tag_t"); 618 memcpy(npc, pc, sizeof *pc); 619 npc->cookie = pbm; 620 npc->rootnode = node; 621 npc->spc_conf_read = schizo_conf_read; 622 npc->spc_conf_write = schizo_conf_write; 623 npc->spc_intr_map = schizo_pci_intr_map; 624 npc->spc_intr_establish = schizo_pci_intr_establish; 625 npc->spc_find_ino = NULL; 626 return (npc); 627 } 628 629 int 630 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 631 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 632 bus_dmamap_t *dmamp) 633 { 634 struct schizo_pbm *pbm = t->_cookie; 635 int error; 636 637 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 638 boundary, flags, dmamp); 639 if (error == 0) 640 (*dmamp)->_dm_cookie = &pbm->sp_sb; 641 return error; 642 } 643 644 static struct schizo_range * 645 get_schizorange(struct schizo_pbm *pbm, int ss) 646 { 647 int i; 648 649 for (i = 0; i < pbm->sp_nrange; i++) { 650 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 651 return (&pbm->sp_range[i]); 652 } 653 /* not found */ 654 return (NULL); 655 } 656 657 int 658 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 659 int flags, vaddr_t unused, bus_space_handle_t *hp) 660 { 661 bus_addr_t paddr; 662 struct schizo_pbm *pbm = t->cookie; 663 struct schizo_softc *sc = pbm->sp_sc; 664 struct schizo_range *sr; 665 int ss; 666 667 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 668 t->type, 669 (unsigned long long)offset, 670 (unsigned long long)size, 671 flags)); 672 673 ss = sparc_pci_childspace(t->type); 674 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 675 676 sr = get_schizorange(pbm, ss); 677 if (sr != NULL) { 678 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 679 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 680 "space %lx offset %lx paddr %qx\n", 681 __func__, (long)ss, (long)offset, 682 (unsigned long long)paddr)); 683 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 684 flags, 0, hp)); 685 } 686 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 687 return (EINVAL); 688 } 689 690 static paddr_t 691 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 692 int flags) 693 { 694 bus_addr_t offset = paddr; 695 struct schizo_pbm *pbm = t->cookie; 696 struct schizo_softc *sc = pbm->sp_sc; 697 struct schizo_range *sr; 698 int ss; 699 700 ss = sparc_pci_childspace(t->type); 701 702 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 703 prot, flags, (unsigned long long)paddr)); 704 705 sr = get_schizorange(pbm, ss); 706 if (sr != NULL) { 707 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 708 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 709 "space %lx offset %lx paddr %qx\n", 710 __func__, (long)ss, (long)offset, 711 (unsigned long long)paddr)); 712 return (bus_space_mmap(sc->sc_bustag, paddr, off, 713 prot, flags)); 714 } 715 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 716 return (-1); 717 } 718 719 /* 720 * Set the IGN for this schizo into the handle. 721 */ 722 int 723 schizo_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 724 { 725 struct schizo_pbm *pbm = pa->pa_pc->cookie; 726 struct schizo_softc *sc = pbm->sp_sc; 727 728 *ihp |= sc->sc_ign; 729 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 730 return (0); 731 } 732 733 static void * 734 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 735 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 736 { 737 struct schizo_pbm *pbm = t->cookie; 738 struct intrhand *ih = NULL; 739 uint64_t mapoff, clroff; 740 uintptr_t intrregs; 741 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 742 int ino; 743 long vec; 744 745 vec = INTVEC(ihandle); 746 ino = INTINO(vec); 747 748 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 749 if (ih == NULL) 750 return (NULL); 751 752 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 753 ihandle, level, handler, arg)); 754 755 if (level == IPL_NONE) 756 level = INTLEV(vec); 757 if (level == IPL_NONE) { 758 printf(": no IPL, setting IPL 2.\n"); 759 level = 2; 760 } 761 762 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 763 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 764 765 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 766 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 767 768 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 769 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 770 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 771 772 if (INTIGN(vec) == 0) 773 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 774 else 775 ino |= vec & INTMAP_IGN; 776 777 /* Register the map and clear intr registers */ 778 ih->ih_map = intrmapptr; 779 ih->ih_clr = intrclrptr; 780 781 ih->ih_fun = handler; 782 ih->ih_arg = arg; 783 ih->ih_pil = level; 784 ih->ih_number = ino; 785 786 DPRINTF(SDB_INTR, ( 787 "; installing handler %p arg %p with inr %x pil %u\n", 788 handler, arg, ino, (u_int)ih->ih_pil)); 789 790 intr_establish(ih->ih_pil, level != IPL_VM, ih); 791 792 /* 793 * Enable the interrupt now we have the handler installed. 794 * Read the current value as we can't change it besides the 795 * valid bit so so make sure only this bit is changed. 796 */ 797 if (intrmapptr) { 798 u_int64_t imap; 799 800 imap = schizo_pbm_readintr(pbm, mapoff); 801 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 802 (unsigned long long)imap)); 803 imap |= INTMAP_V; 804 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 805 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 806 (unsigned long long)imap)); 807 schizo_pbm_writeintr(pbm, mapoff, imap); 808 imap = schizo_pbm_readintr(pbm, mapoff); 809 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 810 (unsigned long long)imap)); 811 ih->ih_number |= imap & INTMAP_INR; 812 } 813 if (intrclrptr) { 814 /* set state to IDLE */ 815 schizo_pbm_writeintr(pbm, clroff, 0); 816 } 817 818 return (ih); 819 } 820 821 static void * 822 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 823 int (*func)(void *), void *arg) 824 { 825 void *cookie; 826 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 827 828 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 829 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 830 831 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 832 return (cookie); 833 } 834
Indexes created Tue Sep 30 20:09:53 GMT 2025