schizo.c revision 1.19
1 /* $NetBSD: schizo.c,v 1.19 2011/04/04 20:37:54 dyoung Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/errno.h> 35 #include <sys/extent.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 #include <sys/reboot.h> 40 41 #define _SPARC_BUS_DMA_PRIVATE 42 #include <machine/bus.h> 43 #include <machine/autoconf.h> 44 #include <machine/psl.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <sparc64/dev/iommureg.h> 50 #include <sparc64/dev/iommuvar.h> 51 #include <sparc64/dev/schizoreg.h> 52 #include <sparc64/dev/schizovar.h> 53 #include <sparc64/sparc64/cache.h> 54 55 #ifdef DEBUG 56 #define SDB_PROM 0x01 57 #define SDB_BUSMAP 0x02 58 #define SDB_INTR 0x04 59 #define SDB_INTMAP 0x08 60 #define SDB_CONF 0x10 61 int schizo_debug = 0x0; 62 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 63 #else 64 #define DPRINTF(l, s) 65 #endif 66 67 extern struct sparc_pci_chipset _sparc_pci_chipset; 68 69 static int schizo_match(struct device *, struct cfdata *, void *); 70 static void schizo_attach(struct device *, struct device *, void *); 71 static int schizo_print(void *aux, const char *p); 72 73 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 74 schizo_match, schizo_attach, NULL, NULL); 75 76 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 77 78 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 79 int (*handler)(void *), void *, int, const char *); 80 int schizo_ue(void *); 81 int schizo_ce(void *); 82 int schizo_safari_error(void *); 83 int schizo_pci_error(void *); 84 85 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 86 pci_chipset_tag_t); 87 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 91 int); 92 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 93 94 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 97 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 98 int flags, vaddr_t unused, bus_space_handle_t *hp); 99 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 100 off_t off, int prot, int flags); 101 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 102 void *, void(*)(void)); 103 static int schizo_pci_intr_map(const struct pci_attach_args *, 104 pci_intr_handle_t *); 105 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 106 int, int (*)(void *), void *); 107 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 108 bus_size_t, int, bus_dmamap_t *); 109 110 int 111 schizo_match(struct device *parent, struct cfdata *match, void *aux) 112 { 113 struct mainbus_attach_args *ma = aux; 114 char *str; 115 116 if (strcmp(ma->ma_name, "pci") != 0) 117 return (0); 118 119 str = prom_getpropstring(ma->ma_node, "model"); 120 if (strcmp(str, "schizo") == 0) 121 return (1); 122 123 str = prom_getpropstring(ma->ma_node, "compatible"); 124 if (strcmp(str, "pci108e,8001") == 0) 125 return (1); 126 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 127 return (1); 128 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 129 return (1); 130 131 return (0); 132 } 133 134 void 135 schizo_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct schizo_softc *sc = (struct schizo_softc *)self; 138 struct mainbus_attach_args *ma = aux; 139 struct schizo_pbm *pbm; 140 struct iommu_state *is; 141 struct pcibus_attach_args pba; 142 uint64_t reg, eccctrl; 143 int *busranges = NULL, nranges; 144 char *str; 145 bool no_sc; 146 147 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 148 str = prom_getpropstring(ma->ma_node, "compatible"); 149 if (strcmp(str, "pci108e,a801") == 0) 150 sc->sc_tomatillo = 1; 151 152 sc->sc_node = ma->ma_node; 153 sc->sc_dmat = ma->ma_dmatag; 154 sc->sc_bustag = ma->ma_bustag; 155 156 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 157 sizeof(struct schizo_regs), 0, 158 &sc->sc_ctrlh)) { 159 aprint_error(": failed to map registers\n"); 160 return; 161 } 162 163 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 164 165 /* enable schizo ecc error interrupts */ 166 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 167 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 168 SCZ_ECCCTRL_UE_INTEN | 169 SCZ_ECCCTRL_CE_INTEN; 170 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 171 172 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 173 if (pbm == NULL) 174 panic("schizo: can't alloc schizo pbm"); 175 176 pbm->sp_sc = sc; 177 pbm->sp_regt = sc->sc_bustag; 178 179 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 180 pbm->sp_bus_a = 1; 181 else 182 pbm->sp_bus_a = 0; 183 184 /* 185 * Map interrupt registers 186 */ 187 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 188 ma->ma_reg[0].ur_len, 189 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 190 aprint_error(": failed to interrupt map registers\n"); 191 return; 192 } 193 194 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 195 &pbm->sp_nrange, (void **)&pbm->sp_range)) 196 panic("schizo: can't get ranges"); 197 198 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 199 (void **)&busranges)) 200 panic("schizo: can't get bus-range"); 201 202 aprint_normal(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 203 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 204 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 205 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 206 aprint_naive("\n"); 207 208 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 209 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 210 offsetof(struct schizo_regs, pbm_b), 211 sizeof(struct schizo_pbm_regs), 212 &pbm->sp_regh)) { 213 panic("schizo: unable to create PBM handle"); 214 } 215 216 is = &pbm->sp_is; 217 pbm->sp_sb.sb_is = is; 218 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 219 if (no_sc) 220 aprint_debug("%s: no streaming buffers\n", sc->sc_dv.dv_xname); 221 else { 222 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 223 224 /* 225 * Initialize the strbuf_ctl. 226 * 227 * The flush sync buffer must be 64-byte aligned. 228 */ 229 is->is_sb[0] = &pbm->sp_sb; 230 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 231 232 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 233 offsetof(struct schizo_pbm_regs, strbuf), 234 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 235 } 236 237 aprint_normal("%s: ", sc->sc_dv.dv_xname); 238 schizo_init_iommu(sc, pbm); 239 240 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 241 pbm->sp_iot = schizo_alloc_io_tag(pbm); 242 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 243 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 244 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 245 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 246 247 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 248 panic("schizo: could not map config space"); 249 250 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 251 &_sparc_pci_chipset); 252 pbm->sp_pc->spc_busmax = busranges[1]; 253 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 254 M_DEVBUF, M_NOWAIT | M_ZERO); 255 if (pbm->sp_pc->spc_busnode == NULL) 256 panic("schizo: malloc busnode"); 257 258 pba.pba_bus = busranges[0]; 259 pba.pba_bridgetag = NULL; 260 pba.pba_pc = pbm->sp_pc; 261 pba.pba_flags = pbm->sp_flags; 262 pba.pba_dmat = pbm->sp_dmat; 263 pba.pba_dmat64 = NULL; /* XXX */ 264 pba.pba_memt = pbm->sp_memt; 265 pba.pba_iot = pbm->sp_iot; 266 267 free(busranges, M_DEVBUF); 268 269 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 270 271 /* clear out the bus errors */ 272 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 273 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 274 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 275 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 276 277 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 278 /* enable/disable error interrupts and arbiter */ 279 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 280 reg &= ~SCZ_PCICTRL_SBH_INT; 281 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 282 283 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 284 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 285 SCZ_PCIDIAG_D_INTSYNC); 286 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 287 288 if (pbm->sp_bus_a) 289 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 290 pbm, SCZ_PCIERR_A_INO, "pci_a"); 291 else 292 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 293 pbm, SCZ_PCIERR_B_INO, "pci_b"); 294 295 /* double mapped */ 296 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 297 "ue"); 298 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 299 "ce"); 300 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 301 SCZ_SERR_INO, "safari"); 302 303 if (sc->sc_tomatillo) { 304 /* 305 * Enable the IOCACHE. 306 */ 307 uint64_t iocache_csr; 308 309 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 310 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 311 TOM_IOCACHE_CSR_PEN_RDM | 312 TOM_IOCACHE_CSR_PEN_ONE | 313 TOM_IOCACHE_CSR_PEN_LINE; 314 315 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 316 } 317 318 config_found(&sc->sc_dv, &pba, schizo_print); 319 } 320 321 int 322 schizo_ue(void *vsc) 323 { 324 struct schizo_softc *sc = vsc; 325 326 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 327 return (1); 328 } 329 330 int 331 schizo_ce(void *vsc) 332 { 333 struct schizo_softc *sc = vsc; 334 335 panic("%s: correctable error", sc->sc_dv.dv_xname); 336 return (1); 337 } 338 339 int 340 schizo_pci_error(void *vpbm) 341 { 342 struct schizo_pbm *sp = vpbm; 343 struct schizo_softc *sc = sp->sp_sc; 344 u_int64_t afsr, afar, ctrl, tfar; 345 u_int32_t csr; 346 char bits[128]; 347 348 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 349 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 350 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 351 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 352 353 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 354 sp->sp_bus_a ? 'A' : 'B'); 355 356 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 357 printf("PCIAFSR=%s\n", bits); 358 printf("PCIAFAR=%" PRIx64 "\n", afar); 359 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 360 printf("PCICTRL=%s\n", bits); 361 #ifdef PCI_COMMAND_STATUS_BITS 362 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 363 printf("PCICSR=%s\n", bits); 364 #endif 365 366 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 367 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 368 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 369 370 if ((ctrl & TOM_IOMMU_ERR) == 0) 371 goto clear_error; 372 373 if (sc->sc_tomatillo) { 374 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 375 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 376 } 377 378 /* These are non-fatal if target abort was signalled. */ 379 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 380 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 381 ctrl & TOM_IOMMU_BADVA_ERR) { 382 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 383 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 384 goto clear_error; 385 } 386 } 387 } 388 389 panic("%s: fatal", sc->sc_dv.dv_xname); 390 391 clear_error: 392 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 393 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 394 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 395 return (1); 396 } 397 398 int 399 schizo_safari_error(void *vsc) 400 { 401 struct schizo_softc *sc = vsc; 402 403 printf("%s: safari error\n", sc->sc_dv.dv_xname); 404 405 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 406 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 407 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 408 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 409 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 410 411 panic("%s: fatal", sc->sc_dv.dv_xname); 412 return (1); 413 } 414 415 void 416 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 417 { 418 struct iommu_state *is = &pbm->sp_is; 419 int *vdma = NULL, nitem, tsbsize = 7; 420 u_int32_t iobase = -1; 421 char *name; 422 423 /* punch in our copies */ 424 is->is_bustag = pbm->sp_regt; 425 bus_space_subregion(is->is_bustag, pbm->sp_regh, 426 offsetof(struct schizo_pbm_regs, iommu), 427 sizeof(struct iommureg2), 428 &is->is_iommu); 429 430 /* 431 * Separate the men from the boys. If the `virtual-dma' 432 * property exists, use it. 433 */ 434 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 435 (void **)&vdma)) { 436 /* Damn. Gotta use these values. */ 437 iobase = vdma[0]; 438 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 439 switch (vdma[1]) { 440 TSBCASE(1); TSBCASE(2); TSBCASE(3); 441 TSBCASE(4); TSBCASE(5); TSBCASE(6); 442 default: 443 printf("bogus tsb size %x, using 7\n", vdma[1]); 444 TSBCASE(7); 445 } 446 #undef TSBCASE 447 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 448 free(vdma, M_DEVBUF); 449 } else { 450 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 451 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 452 } 453 454 /* give us a nice name.. */ 455 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 456 if (name == NULL) 457 panic("couldn't malloc iommu name"); 458 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 459 460 iommu_init(name, is, tsbsize, iobase); 461 } 462 463 int 464 schizo_print(void *aux, const char *p) 465 { 466 467 if (p == NULL) 468 return (UNCONF); 469 return (QUIET); 470 } 471 472 pcireg_t 473 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 474 { 475 struct schizo_pbm *sp = pc->cookie; 476 pcireg_t val = (pcireg_t)~0; 477 478 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 479 if (PCITAG_NODE(tag) != -1) 480 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 481 PCITAG_OFFSET(tag) + reg); 482 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 483 return (val); 484 } 485 486 void 487 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 488 { 489 struct schizo_pbm *sp = pc->cookie; 490 491 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 492 (long)tag, reg, (int)data)); 493 494 /* If we don't know it, just punt it. */ 495 if (PCITAG_NODE(tag) == -1) { 496 DPRINTF(SDB_CONF, (" .. bad addr\n")); 497 return; 498 } 499 500 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 501 PCITAG_OFFSET(tag) + reg, data); 502 DPRINTF(SDB_CONF, (" .. done\n")); 503 } 504 505 void 506 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 507 int (*handler)(void *), void *arg, int ino, const char *what) 508 { 509 struct intrhand *ih; 510 u_int64_t mapoff, clroff; 511 uintptr_t intrregs; 512 513 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 514 ino, sc->sc_ign, handler, arg)); 515 516 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 517 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 518 ino |= sc->sc_ign; 519 520 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 521 mapoff, clroff)); 522 523 ih = (struct intrhand *) 524 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 525 if (ih == NULL) 526 return; 527 ih->ih_arg = arg; 528 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 529 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 530 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 531 ih->ih_fun = handler; 532 ih->ih_pil = (1<<ipl); 533 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 534 intr_establish(ipl, ipl != IPL_VM, ih); 535 536 schizo_pbm_write(pbm, mapoff, 537 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 538 } 539 540 bus_space_tag_t 541 schizo_alloc_mem_tag(struct schizo_pbm *sp) 542 { 543 return (schizo_alloc_bus_tag(sp, "mem", 544 PCI_MEMORY_BUS_SPACE)); 545 } 546 547 bus_space_tag_t 548 schizo_alloc_io_tag(struct schizo_pbm *sp) 549 { 550 return (schizo_alloc_bus_tag(sp, "io", 551 PCI_IO_BUS_SPACE)); 552 } 553 554 bus_space_tag_t 555 schizo_alloc_config_tag(struct schizo_pbm *sp) 556 { 557 return (schizo_alloc_bus_tag(sp, "cfg", 558 PCI_CONFIG_BUS_SPACE)); 559 } 560 561 bus_space_tag_t 562 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 563 { 564 struct schizo_softc *sc = pbm->sp_sc; 565 bus_space_tag_t bt; 566 567 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 568 M_DEVBUF, M_NOWAIT | M_ZERO); 569 if (bt == NULL) 570 panic("schizo: could not allocate bus tag"); 571 572 bt->cookie = pbm; 573 bt->parent = sc->sc_bustag; 574 bt->type = type; 575 bt->sparc_bus_map = schizo_bus_map; 576 bt->sparc_bus_mmap = schizo_bus_mmap; 577 bt->sparc_intr_establish = schizo_intr_establish; 578 return (bt); 579 } 580 581 bus_dma_tag_t 582 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 583 { 584 struct schizo_softc *sc = pbm->sp_sc; 585 bus_dma_tag_t dt, pdt = sc->sc_dmat; 586 587 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 588 if (dt == NULL) 589 panic("schizo: could not alloc dma tag"); 590 591 dt->_cookie = pbm; 592 dt->_parent = pdt; 593 #define PCOPY(x) dt->x = pdt->x 594 dt->_dmamap_create = schizo_dmamap_create; 595 PCOPY(_dmamap_destroy); 596 dt->_dmamap_load = iommu_dvmamap_load; 597 PCOPY(_dmamap_load_mbuf); 598 PCOPY(_dmamap_load_uio); 599 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 600 dt->_dmamap_unload = iommu_dvmamap_unload; 601 dt->_dmamap_sync = iommu_dvmamap_sync; 602 dt->_dmamem_alloc = iommu_dvmamem_alloc; 603 dt->_dmamem_free = iommu_dvmamem_free; 604 dt->_dmamem_map = iommu_dvmamem_map; 605 dt->_dmamem_unmap = iommu_dvmamem_unmap; 606 PCOPY(_dmamem_mmap); 607 #undef PCOPY 608 return (dt); 609 } 610 611 pci_chipset_tag_t 612 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 613 { 614 pci_chipset_tag_t npc; 615 616 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 617 if (npc == NULL) 618 panic("schizo: could not allocate pci_chipset_tag_t"); 619 memcpy(npc, pc, sizeof *pc); 620 npc->cookie = pbm; 621 npc->rootnode = node; 622 npc->spc_conf_read = schizo_conf_read; 623 npc->spc_conf_write = schizo_conf_write; 624 npc->spc_intr_map = schizo_pci_intr_map; 625 npc->spc_intr_establish = schizo_pci_intr_establish; 626 npc->spc_find_ino = NULL; 627 return (npc); 628 } 629 630 int 631 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 632 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 633 bus_dmamap_t *dmamp) 634 { 635 struct schizo_pbm *pbm = t->_cookie; 636 int error; 637 638 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 639 boundary, flags, dmamp); 640 if (error == 0) 641 (*dmamp)->_dm_cookie = &pbm->sp_sb; 642 return error; 643 } 644 645 static struct schizo_range * 646 get_schizorange(struct schizo_pbm *pbm, int ss) 647 { 648 int i; 649 650 for (i = 0; i < pbm->sp_nrange; i++) { 651 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 652 return (&pbm->sp_range[i]); 653 } 654 /* not found */ 655 return (NULL); 656 } 657 658 int 659 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 660 int flags, vaddr_t unused, bus_space_handle_t *hp) 661 { 662 bus_addr_t paddr; 663 struct schizo_pbm *pbm = t->cookie; 664 struct schizo_softc *sc = pbm->sp_sc; 665 struct schizo_range *sr; 666 int ss; 667 668 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 669 t->type, 670 (unsigned long long)offset, 671 (unsigned long long)size, 672 flags)); 673 674 ss = sparc_pci_childspace(t->type); 675 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 676 677 sr = get_schizorange(pbm, ss); 678 if (sr != NULL) { 679 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 680 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 681 "space %lx offset %lx paddr %qx\n", 682 __func__, (long)ss, (long)offset, 683 (unsigned long long)paddr)); 684 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 685 flags, 0, hp)); 686 } 687 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 688 return (EINVAL); 689 } 690 691 static paddr_t 692 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 693 int flags) 694 { 695 bus_addr_t offset = paddr; 696 struct schizo_pbm *pbm = t->cookie; 697 struct schizo_softc *sc = pbm->sp_sc; 698 struct schizo_range *sr; 699 int ss; 700 701 ss = sparc_pci_childspace(t->type); 702 703 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 704 prot, flags, (unsigned long long)paddr)); 705 706 sr = get_schizorange(pbm, ss); 707 if (sr != NULL) { 708 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 709 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 710 "space %lx offset %lx paddr %qx\n", 711 __func__, (long)ss, (long)offset, 712 (unsigned long long)paddr)); 713 return (bus_space_mmap(sc->sc_bustag, paddr, off, 714 prot, flags)); 715 } 716 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 717 return (-1); 718 } 719 720 /* 721 * Set the IGN for this schizo into the handle. 722 */ 723 int 724 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 725 { 726 struct schizo_pbm *pbm = pa->pa_pc->cookie; 727 struct schizo_softc *sc = pbm->sp_sc; 728 729 *ihp |= sc->sc_ign; 730 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 731 return (0); 732 } 733 734 static void * 735 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 736 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 737 { 738 struct schizo_pbm *pbm = t->cookie; 739 struct intrhand *ih = NULL; 740 uint64_t mapoff, clroff; 741 uintptr_t intrregs; 742 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 743 int ino; 744 long vec; 745 746 vec = INTVEC(ihandle); 747 ino = INTINO(vec); 748 749 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 750 if (ih == NULL) 751 return (NULL); 752 753 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 754 ihandle, level, handler, arg)); 755 756 if (level == IPL_NONE) 757 level = INTLEV(vec); 758 if (level == IPL_NONE) { 759 printf(": no IPL, setting IPL 2.\n"); 760 level = 2; 761 } 762 763 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 764 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 765 766 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 767 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 768 769 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 770 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 771 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 772 773 if (INTIGN(vec) == 0) 774 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 775 else 776 ino |= vec & INTMAP_IGN; 777 778 /* Register the map and clear intr registers */ 779 ih->ih_map = intrmapptr; 780 ih->ih_clr = intrclrptr; 781 782 ih->ih_fun = handler; 783 ih->ih_arg = arg; 784 ih->ih_pil = level; 785 ih->ih_number = ino; 786 787 DPRINTF(SDB_INTR, ( 788 "; installing handler %p arg %p with inr %x pil %u\n", 789 handler, arg, ino, (u_int)ih->ih_pil)); 790 791 intr_establish(ih->ih_pil, level != IPL_VM, ih); 792 793 /* 794 * Enable the interrupt now we have the handler installed. 795 * Read the current value as we can't change it besides the 796 * valid bit so so make sure only this bit is changed. 797 */ 798 if (intrmapptr) { 799 u_int64_t imap; 800 801 imap = schizo_pbm_readintr(pbm, mapoff); 802 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 803 (unsigned long long)imap)); 804 imap |= INTMAP_V; 805 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 806 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 807 (unsigned long long)imap)); 808 schizo_pbm_writeintr(pbm, mapoff, imap); 809 imap = schizo_pbm_readintr(pbm, mapoff); 810 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 811 (unsigned long long)imap)); 812 ih->ih_number |= imap & INTMAP_INR; 813 } 814 if (intrclrptr) { 815 /* set state to IDLE */ 816 schizo_pbm_writeintr(pbm, clroff, 0); 817 } 818 819 return (ih); 820 } 821 822 static void * 823 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 824 int (*func)(void *), void *arg) 825 { 826 void *cookie; 827 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 828 829 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 830 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 831 832 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 833 return (cookie); 834 } 835
Indexes created Tue Sep 30 20:09:53 GMT 2025