schizo.c revision 1.2
1 /* $NetBSD: schizo.c,v 1.2 2008/12/10 05:56:22 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/extent.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/time.h> 38 #include <sys/reboot.h> 39 40 #define _SPARC_BUS_DMA_PRIVATE 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/psl.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <sparc64/dev/iommureg.h> 49 #include <sparc64/dev/iommuvar.h> 50 #include <sparc64/dev/schizoreg.h> 51 #include <sparc64/dev/schizovar.h> 52 #include <sparc64/sparc64/cache.h> 53 54 #ifdef DEBUG 55 #define SDB_PROM 0x01 56 #define SDB_BUSMAP 0x02 57 #define SDB_INTR 0x04 58 #define SDB_INTMAP 0x08 59 #define SDB_CONF 0x10 60 int schizo_debug = 0x0f; 61 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 62 #else 63 #define DPRINTF(l, s) 64 #endif 65 66 extern struct sparc_pci_chipset _sparc_pci_chipset; 67 68 static int schizo_match(struct device *, struct cfdata *, void *); 69 static void schizo_attach(struct device *, struct device *, void *); 70 static int schizo_print(void *aux, const char *p); 71 72 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 73 schizo_match, schizo_attach, NULL, NULL); 74 75 void schizo_init(struct schizo_softc *, int, struct mainbus_attach_args *); 76 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 77 78 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 79 int (*handler)(void *), void *, int, const char *); 80 int schizo_ue(void *); 81 int schizo_ce(void *); 82 int schizo_safari_error(void *); 83 int schizo_pci_error(void *); 84 85 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 86 pci_chipset_tag_t); 87 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 91 int); 92 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 93 94 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 97 int schizo_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 98 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 99 int flags, vaddr_t unused, bus_space_handle_t *hp); 100 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 101 off_t off, int prot, int flags); 102 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 103 void *, void(*)(void)); 104 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 105 int, int (*)(void *), void *); 106 static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 107 108 int 109 schizo_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct mainbus_attach_args *ma = aux; 112 char *str; 113 114 if (strcmp(ma->ma_name, "pci") != 0) 115 return (0); 116 117 str = prom_getpropstring(ma->ma_node, "model"); 118 if (strcmp(str, "schizo") == 0) 119 return (1); 120 121 str = prom_getpropstring(ma->ma_node, "compatible"); 122 if (strcmp(str, "pci108e,8001") == 0) 123 return (1); 124 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 125 return (1); 126 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 127 return (1); 128 129 return (0); 130 } 131 132 void 133 schizo_attach(struct device *parent, struct device *self, void *aux) 134 { 135 struct schizo_softc *sc = (struct schizo_softc *)self; 136 struct mainbus_attach_args *ma = aux; 137 uint64_t eccctrl; 138 int busa; 139 char *str; 140 141 printf(": addr %lx ", ma->ma_reg[0].ur_paddr); 142 str = prom_getpropstring(ma->ma_node, "compatible"); 143 if (strcmp(str, "pci108e,a801") == 0) 144 sc->sc_tomatillo = 1; 145 146 sc->sc_node = ma->ma_node; 147 sc->sc_dmat = ma->ma_dmatag; 148 sc->sc_bustag = ma->ma_bustag; 149 sc->sc_ctrl = ma->ma_reg[1].ur_paddr - 0x10000UL; 150 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 151 152 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 153 busa = 1; 154 else 155 busa = 0; 156 157 printf("bustag->type = %d\n", sc->sc_bustag->type); 158 if (bus_space_map(sc->sc_bustag, sc->sc_ctrl, 159 sizeof(struct schizo_regs), 0, 160 &sc->sc_ctrlh)) { 161 printf(": failed to map registers\n"); 162 return; 163 } 164 printf("mapped regs len %zx, sc_ctrl = %lx sc_ctrlh._ptr = %lx ._asi = %x ._sasi = %x\n", sizeof(struct schizo_regs), (uint64_t)sc->sc_ctrl, sc->sc_ctrlh._ptr, sc->sc_ctrlh._asi, sc->sc_ctrlh._sasi); 165 166 /* enable schizo ecc error interrupts */ 167 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 168 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 169 SCZ_ECCCTRL_UE_INTEN | 170 SCZ_ECCCTRL_CE_INTEN; 171 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 172 173 schizo_init(sc, busa, ma); 174 } 175 176 void 177 schizo_init(struct schizo_softc *sc, int busa, struct mainbus_attach_args *ma) 178 { 179 struct schizo_pbm *pbm; 180 struct pcibus_attach_args pba; 181 int *busranges = NULL, nranges; 182 u_int64_t /*match,*/ reg; 183 184 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 185 if (pbm == NULL) 186 panic("schizo: can't alloc schizo pbm"); 187 188 pbm->sp_sc = sc; 189 pbm->sp_bus_a = busa; 190 pbm->sp_regt = sc->sc_bustag; 191 192 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 193 &pbm->sp_nrange, (void **)&pbm->sp_range)) 194 panic("schizo: can't get ranges"); 195 196 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 197 (void **)&busranges)) 198 panic("schizo: can't get bus-range"); 199 200 printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 201 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 202 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 203 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 204 205 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 206 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 207 offsetof(struct schizo_regs, pbm_b), 208 sizeof(struct schizo_pbm_regs), 209 &pbm->sp_regh)) { 210 panic("schizo: unable to create PBM handle"); 211 } 212 printf("mapped regs, sp_regh._ptr = %lx ._asi = %x ._sasi = %x\n", pbm->sp_regh._ptr, pbm->sp_regh._asi, pbm->sp_regh._sasi); 213 214 printf("%s: ", sc->sc_dv.dv_xname); 215 schizo_init_iommu(sc, pbm); 216 217 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 218 pbm->sp_iot = schizo_alloc_io_tag(pbm); 219 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 220 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 221 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 222 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 223 224 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 225 panic("schizo: could not map config space"); 226 printf("mapped regs, sp_cfgh._ptr = %lx ._asi = %x ._sasi = %x\n", pbm->sp_cfgh._ptr, pbm->sp_cfgh._asi, pbm->sp_cfgh._sasi); 227 228 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 229 &_sparc_pci_chipset); 230 231 pba.pba_bus = busranges[0]; 232 pba.pba_bridgetag = NULL; 233 pba.pba_pc = pbm->sp_pc; 234 pba.pba_flags = pbm->sp_flags; 235 pba.pba_dmat = pbm->sp_dmat; 236 pba.pba_dmat64 = NULL; /* XXX */ 237 pba.pba_memt = pbm->sp_memt; 238 pba.pba_iot = pbm->sp_iot; 239 #if 0 240 pba.pba_pc->intr_map = schizo_intr_map; 241 #endif 242 243 free(busranges, M_DEVBUF); 244 245 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 246 247 /* clear out the bus errors */ 248 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 249 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 250 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 251 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 252 253 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 254 /* enable/disable error interrupts and arbiter */ 255 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 256 reg &= ~SCZ_PCICTRL_SBH_INT; 257 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 258 259 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 260 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 261 SCZ_PCIDIAG_D_INTSYNC); 262 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 263 264 if (pbm->sp_bus_a) 265 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 266 pbm, SCZ_PCIERR_A_INO, "pci_a"); 267 else 268 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 269 pbm, SCZ_PCIERR_B_INO, "pci_b"); 270 271 /* double mapped */ 272 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 273 "ue"); 274 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 275 "ce"); 276 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 277 SCZ_SERR_INO, "safari"); 278 279 config_found(&sc->sc_dv, &pba, schizo_print); 280 } 281 282 int 283 schizo_ue(void *vsc) 284 { 285 struct schizo_softc *sc = vsc; 286 287 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 288 return (1); 289 } 290 291 int 292 schizo_ce(void *vsc) 293 { 294 struct schizo_softc *sc = vsc; 295 296 panic("%s: correctable error", sc->sc_dv.dv_xname); 297 return (1); 298 } 299 300 int 301 schizo_pci_error(void *vpbm) 302 { 303 struct schizo_pbm *sp = vpbm; 304 struct schizo_softc *sc = sp->sp_sc; 305 u_int64_t afsr, afar, ctrl, tfar; 306 u_int32_t csr; 307 char bits[128]; 308 309 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 310 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 311 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 312 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 313 314 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 315 sp->sp_bus_a ? 'A' : 'B'); 316 317 printf("PCIAFSR=%s\n", bitmask_snprintf(afsr, SCZ_PCIAFSR_BITS, 318 bits, sizeof(bits))); 319 printf("PCIAFAR=%lx\n", afar); 320 printf("PCICTRL=%s\n", bitmask_snprintf(ctrl, SCZ_PCICTRL_BITS, 321 bits, sizeof(bits))); 322 #ifdef PCI_COMMAND_STATUS_BITS 323 printf("PCICSR=%s\n", bitmask_snprintf(csr, PCI_COMMAND_STATUS_BITS, 324 bits, sizeof(bits))); 325 #endif 326 327 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 328 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 329 printf("IOMMUCTRL=%lx\n", ctrl); 330 331 if ((ctrl & TOM_IOMMU_ERR) == 0) 332 goto clear_error; 333 334 if (sc->sc_tomatillo) { 335 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 336 printf("IOMMUTFAR=%lx\n", tfar); 337 } 338 339 /* These are non-fatal if target abort was signalled. */ 340 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 341 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 342 ctrl & TOM_IOMMU_BADVA_ERR) { 343 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 344 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 345 goto clear_error; 346 } 347 } 348 } 349 350 panic("%s: fatal", sc->sc_dv.dv_xname); 351 352 clear_error: 353 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 354 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 355 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 356 return (1); 357 } 358 359 int 360 schizo_safari_error(void *vsc) 361 { 362 struct schizo_softc *sc = vsc; 363 364 printf("%s: safari error\n", sc->sc_dv.dv_xname); 365 366 printf("ERRLOG=%lx\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 367 printf("UE_AFSR=%lx\n", schizo_read(sc, SCZ_UE_AFSR)); 368 printf("UE_AFAR=%lx\n", schizo_read(sc, SCZ_UE_AFAR)); 369 printf("CE_AFSR=%lx\n", schizo_read(sc, SCZ_CE_AFSR)); 370 printf("CE_AFAR=%lx\n", schizo_read(sc, SCZ_CE_AFAR)); 371 372 panic("%s: fatal", sc->sc_dv.dv_xname); 373 return (1); 374 } 375 376 void 377 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 378 { 379 struct iommu_state *is = &pbm->sp_is; 380 int *vdma = NULL, nitem, tsbsize = 7; 381 u_int32_t iobase = -1; 382 vaddr_t va; 383 char *name; 384 385 va = (vaddr_t)pbm->sp_flush[0x40]; 386 387 is->is_bustag = pbm->sp_regt; 388 389 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 390 offsetof(struct schizo_pbm_regs, iommu), 391 sizeof(struct iommureg), &is->is_iommu)) { 392 panic("schizo: unable to create iommu handle"); 393 } 394 395 is->is_sb[0] = &pbm->sp_sb; 396 // XXXSCHIZO? 397 //is->is_sb[0]->sb_bustag = is->is_bustag; 398 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 399 400 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 401 offsetof(struct schizo_pbm_regs, strbuf), 402 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb)) { 403 panic("schizo: unable to create streaming buffer handle"); 404 is->is_sb[0]->sb_flush = NULL; 405 } 406 407 #if 1 408 /* XXX disable the streaming buffers for now */ 409 bus_space_write_8(is->is_bustag, is->is_sb[0]->sb_sb, 410 STRBUFREG(strbuf_ctl), 411 bus_space_read_8(is->is_bustag, is->is_sb[0]->sb_sb, 412 STRBUFREG(strbuf_ctl)) & ~STRBUF_EN); 413 is->is_sb[0]->sb_flush = NULL; 414 #endif 415 416 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 417 if (name == NULL) 418 panic("couldn't malloc iommu name"); 419 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 420 421 /* 422 * Separate the men from the boys. If the `virtual-dma' 423 * property exists, use it. 424 */ 425 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 426 (void **)&vdma)) { 427 /* Damn. Gotta use these values. */ 428 iobase = vdma[0]; 429 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 430 switch (vdma[1]) { 431 TSBCASE(1); TSBCASE(2); TSBCASE(3); 432 TSBCASE(4); TSBCASE(5); TSBCASE(6); 433 default: 434 printf("bogus tsb size %x, using 7\n", vdma[1]); 435 TSBCASE(7); 436 } 437 #undef TSBCASE 438 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 439 free(vdma, M_DEVBUF); 440 } else { 441 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 442 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 443 } 444 445 iommu_init(name, is, tsbsize, iobase); 446 } 447 448 int 449 schizo_print(void *aux, const char *p) 450 { 451 452 if (p == NULL) 453 return (UNCONF); 454 return (QUIET); 455 } 456 457 pcireg_t 458 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 459 { 460 struct schizo_pbm *sp = pc->cookie; 461 pcireg_t val; 462 463 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 464 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 465 PCITAG_OFFSET(tag) + reg); 466 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 467 return (val); 468 } 469 470 void 471 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 472 { 473 struct schizo_pbm *sp = pc->cookie; 474 475 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 476 (long)tag, reg, (int)data)); 477 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 478 PCITAG_OFFSET(tag) + reg, data); 479 DPRINTF(SDB_CONF, (" .. done\n")); 480 } 481 482 #if 0 483 /* 484 * Bus-specific interrupt mapping 485 */ 486 int 487 schizo_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 488 { 489 struct schizo_pbm *sp = pa->pa_pc->cookie; 490 struct schizo_softc *sc = sp->sp_sc; 491 u_int dev; 492 493 if (*ihp != (pci_intr_handle_t)-1) { 494 *ihp |= sc->sc_ign; 495 return (0); 496 } 497 498 /* 499 * We didn't find a PROM mapping for this interrupt. Try to 500 * construct one ourselves based on the swizzled interrupt pin 501 * and the interrupt mapping for PCI slots documented in the 502 * UltraSPARC-IIi User's Manual. 503 */ 504 505 if (pa->pa_intrpin == 0) 506 return (-1); 507 508 /* 509 * This deserves some documentation. Should anyone 510 * have anything official looking, please speak up. 511 */ 512 dev = pa->pa_device - 1; 513 514 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 515 *ihp |= (dev << 2) & INTMAP_PCISLOT; 516 *ihp |= sc->sc_ign; 517 518 return (0); 519 } 520 #endif 521 522 void 523 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 524 int (*handler)(void *), void *arg, int ino, const char *what) 525 { 526 struct intrhand *ih; 527 //volatile u_int64_t *map, *clr; 528 //struct schizo_pbm_regs *pbmreg; 529 u_int64_t mapoff, clroff; 530 531 //pbmreg = bus_space_vaddr(pbm->sp_regt, pbm->sp_regh); 532 //map = &pbmreg->imap[ino]; 533 //clr = &pbmreg->iclr[ino]; 534 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 535 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 536 ino |= sc->sc_ign; 537 538 ih = (struct intrhand *) 539 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 540 if (ih == NULL) 541 return; 542 ih->ih_arg = arg; 543 //ih->ih_map = map; 544 //ih->ih_clr = clr; 545 ih->ih_map = (uint64_t *)mapoff; // XXX FIXME 546 ih->ih_clr = (uint64_t *)clroff; // XXX FIXME 547 ih->ih_fun = handler; 548 ih->ih_pil = (1<<ipl); 549 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 550 intr_establish(ipl, ipl != IPL_VM, ih); 551 552 schizo_pbm_write(pbm, mapoff, 553 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 554 555 } 556 557 bus_space_tag_t 558 schizo_alloc_mem_tag(struct schizo_pbm *sp) 559 { 560 return (schizo_alloc_bus_tag(sp, "mem", 561 PCI_MEMORY_BUS_SPACE)); 562 } 563 564 bus_space_tag_t 565 schizo_alloc_io_tag(struct schizo_pbm *sp) 566 { 567 return (schizo_alloc_bus_tag(sp, "io", 568 PCI_IO_BUS_SPACE)); 569 } 570 571 bus_space_tag_t 572 schizo_alloc_config_tag(struct schizo_pbm *sp) 573 { 574 return (schizo_alloc_bus_tag(sp, "cfg", 575 PCI_CONFIG_BUS_SPACE)); 576 } 577 578 bus_space_tag_t 579 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 580 { 581 struct schizo_softc *sc = pbm->sp_sc; 582 bus_space_tag_t bt; 583 584 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 585 M_DEVBUF, M_NOWAIT | M_ZERO); 586 if (bt == NULL) 587 panic("schizo: could not allocate bus tag"); 588 589 bt->cookie = pbm; 590 bt->parent = sc->sc_bustag; 591 bt->type = type; 592 bt->sparc_bus_map = schizo_bus_map; 593 bt->sparc_bus_mmap = schizo_bus_mmap; 594 bt->sparc_intr_establish = schizo_intr_establish; 595 return (bt); 596 } 597 598 bus_dma_tag_t 599 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 600 { 601 struct schizo_softc *sc = pbm->sp_sc; 602 bus_dma_tag_t dt, pdt = sc->sc_dmat; 603 604 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 605 if (dt == NULL) 606 panic("schizo: could not alloc dma tag"); 607 608 dt->_cookie = pbm; 609 dt->_parent = pdt; 610 #define PCOPY(x) dt->x = pdt->x 611 PCOPY(_dmamap_create); 612 PCOPY(_dmamap_destroy); 613 dt->_dmamap_load = iommu_dvmamap_load; 614 PCOPY(_dmamap_load_mbuf); 615 PCOPY(_dmamap_load_uio); 616 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 617 dt->_dmamap_unload = iommu_dvmamap_unload; 618 dt->_dmamap_sync = iommu_dvmamap_sync; 619 dt->_dmamem_alloc = iommu_dvmamem_alloc; 620 dt->_dmamem_free = iommu_dvmamem_free; 621 dt->_dmamem_map = iommu_dvmamem_map; 622 dt->_dmamem_unmap = iommu_dvmamem_unmap; 623 PCOPY(_dmamem_mmap); 624 #undef PCOPY 625 return (dt); 626 } 627 628 pci_chipset_tag_t 629 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 630 { 631 pci_chipset_tag_t npc; 632 633 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 634 if (npc == NULL) 635 panic("schizo: could not allocate pci_chipset_tag_t"); 636 memcpy(npc, pc, sizeof *pc); 637 npc->cookie = pbm; 638 npc->rootnode = node; 639 npc->spc_conf_read = schizo_conf_read; 640 npc->spc_conf_write = schizo_conf_write; 641 npc->spc_intr_establish = schizo_pci_intr_establish; 642 npc->spc_find_ino = schizo_pci_find_ino; 643 return (npc); 644 } 645 646 #if 0 647 int 648 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 649 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 650 bus_dmamap_t *dmamp) 651 { 652 struct schizo_pbm *pbm = t->_cookie; 653 654 return (iommu_dvmamap_create(t, &pbm->sp_sb, size, nsegments, 655 maxsegsz, boundary, flags, dmamp)); 656 } 657 #endif 658 659 static struct schizo_range * 660 get_schizorange(struct schizo_pbm *pbm, int ss) 661 { 662 int i; 663 664 for (i = 0; i < pbm->sp_nrange; i++) { 665 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 666 return (&pbm->sp_range[i]); 667 } 668 /* not found */ 669 return (NULL); 670 } 671 672 int 673 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 674 int flags, vaddr_t unused, bus_space_handle_t *hp) 675 { 676 bus_addr_t paddr; 677 struct schizo_pbm *pbm = t->cookie; 678 struct schizo_softc *sc = pbm->sp_sc; 679 struct schizo_range *sr; 680 int ss; 681 682 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 683 t->type, 684 (unsigned long long)offset, 685 (unsigned long long)size, 686 flags)); 687 688 ss = sparc_pci_childspace(t->type); 689 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 690 691 sr = get_schizorange(pbm, ss); 692 if (sr != NULL) { 693 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 694 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 695 "space %lx offset %lx paddr %qx\n", 696 __func__, (long)ss, (long)offset, 697 (unsigned long long)paddr)); 698 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 699 flags, 0, hp)); 700 } 701 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 702 return (EINVAL); 703 } 704 705 static paddr_t 706 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 707 int flags) 708 { 709 bus_addr_t offset = paddr; 710 struct schizo_pbm *pbm = t->cookie; 711 struct schizo_softc *sc = pbm->sp_sc; 712 struct schizo_range *sr; 713 int ss; 714 715 ss = sparc_pci_childspace(t->type); 716 717 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 718 prot, flags, (unsigned long long)paddr)); 719 720 sr = get_schizorange(pbm, ss); 721 if (sr != NULL) { 722 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 723 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 724 "space %lx offset %lx paddr %qx\n", 725 __func__, (long)ss, (long)offset, 726 (unsigned long long)paddr)); 727 return (bus_space_mmap(sc->sc_bustag, paddr, off, 728 prot, flags)); 729 } 730 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 731 return (-1); 732 } 733 734 static void * 735 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 736 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 737 { 738 struct schizo_pbm *pbm = t->cookie; 739 struct intrhand *ih = NULL; 740 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 741 int ino; 742 long vec = INTVEC(ihandle); 743 744 vec = INTVEC(ihandle); 745 ino = INTINO(vec); 746 747 DPRINTF(SDB_INTR, ("%s: ihandle %d level %d fn %p arg %p\n", __func__, 748 ihandle, level, handler, arg)); 749 750 if (level == IPL_NONE) 751 level = INTLEV(vec); 752 if (level == IPL_NONE) { 753 printf(": no IPL, setting IPL 2.\n"); 754 level = 2; 755 } 756 757 #if 0 758 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 759 struct schizo_pbm_regs *pbmreg; 760 761 pbmreg = bus_space_vaddr(pbm->sp_regt, pbm->sp_regh); 762 intrmapptr = &pbmreg->imap[ino]; 763 intrclrptr = &pbmreg->iclr[ino]; 764 if (INTIGN(vec) == 0) 765 ino |= (*intrmapptr) & INTMAP_IGN; 766 else 767 ino |= vec & INTMAP_IGN; 768 } 769 770 ih = bus_intr_allocate(t, handler, arg, ino, level, intrmapptr, 771 intrclrptr, what); 772 #endif 773 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 774 if (ih == NULL) 775 return (NULL); 776 777 ih->ih_map = intrmapptr; 778 ih->ih_clr = intrclrptr; 779 780 ih->ih_fun = handler; 781 ih->ih_arg = arg; 782 ih->ih_pil = level; 783 ih->ih_number = ino | pbm->sp_sc->sc_ign; 784 785 intr_establish(ih->ih_pil, level != IPL_VM, ih); 786 787 if (intrmapptr != NULL) { 788 u_int64_t imap; 789 790 imap = *intrmapptr; 791 imap |= INTMAP_V; 792 *intrmapptr = imap; 793 imap = *intrmapptr; 794 ih->ih_number |= imap & INTMAP_INR; 795 } 796 797 return (ih); 798 } 799 800 static void * 801 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 802 int (*func)(void *), void *arg) 803 { 804 void *cookie; 805 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 806 807 DPRINTF(SDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 808 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 809 810 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 811 return (cookie); 812 } 813 814 static int 815 schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 816 { 817 #if 0 818 struct schizo_pbm *pbm = pa->pa_pc->cookie; 819 struct schizo_softc *sc = pbm->sp_sc; 820 u_int bus; 821 u_int dev; 822 u_int pin; 823 #endif 824 825 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 826 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 827 (int)PCITAG_DEV(pa->pa_tag), 828 (int)PCITAG_FUN(pa->pa_tag))); 829 DPRINTF(SDB_INTMAP, 830 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 831 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 832 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 833 PCITAG_NODE(pa->pa_intrtag), 834 (int)PCITAG_BUS(pa->pa_intrtag), 835 (int)PCITAG_DEV(pa->pa_intrtag), 836 (int)PCITAG_FUN(pa->pa_intrtag))); 837 838 #if 0 839 bus = (pp->pp_id == PSYCHO_PBM_B); 840 /* 841 * If we are on a ppb, use the devno on the underlying bus when forming 842 * the ivec. 843 */ 844 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 845 dev = PCITAG_DEV(pa->pa_intrtag); 846 else 847 dev = pa->pa_device; 848 dev--; 849 850 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 851 pp->pp_id == PSYCHO_PBM_B) 852 dev--; 853 854 pin = pa->pa_intrpin - 1; 855 DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 856 sc->sc_mode, pp->pp_id, dev, pin)); 857 858 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 859 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 860 #endif 861 862 return (0); 863 } 864
Indexes created Tue Sep 30 20:09:53 GMT 2025