schizo.c revision 1.26
1 /* $NetBSD: schizo.c,v 1.26 2011/08/12 06:41:16 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/errno.h> 35 #include <sys/extent.h> 36 #include <sys/kmem.h> 37 #include <sys/malloc.h> 38 #include <sys/systm.h> 39 #include <sys/time.h> 40 #include <sys/reboot.h> 41 42 #define _SPARC_BUS_DMA_PRIVATE 43 #include <sys/bus.h> 44 #include <machine/autoconf.h> 45 #include <machine/psl.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include <sparc64/dev/iommureg.h> 51 #include <sparc64/dev/iommuvar.h> 52 #include <sparc64/dev/schizoreg.h> 53 #include <sparc64/dev/schizovar.h> 54 #include <sparc64/sparc64/cache.h> 55 56 #ifdef DEBUG 57 #define SDB_PROM 0x01 58 #define SDB_BUSMAP 0x02 59 #define SDB_INTR 0x04 60 #define SDB_INTMAP 0x08 61 #define SDB_CONF 0x10 62 int schizo_debug = 0x0; 63 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 64 #else 65 #define DPRINTF(l, s) 66 #endif 67 68 extern struct sparc_pci_chipset _sparc_pci_chipset; 69 70 static int schizo_match(device_t, cfdata_t, void *); 71 static void schizo_attach(device_t, device_t, void *); 72 static int schizo_print(void *aux, const char *p); 73 74 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc), 75 schizo_match, schizo_attach, NULL, NULL); 76 77 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 78 79 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 80 int (*handler)(void *), void *, int, const char *); 81 int schizo_ue(void *); 82 int schizo_ce(void *); 83 int schizo_safari_error(void *); 84 int schizo_pci_error(void *); 85 86 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 87 pci_chipset_tag_t); 88 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 91 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 92 int); 93 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 94 95 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 96 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 97 98 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 99 int flags, vaddr_t unused, bus_space_handle_t *hp); 100 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 101 off_t off, int prot, int flags); 102 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 103 void *, void(*)(void)); 104 static int schizo_pci_intr_map(const struct pci_attach_args *, 105 pci_intr_handle_t *); 106 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 107 int, int (*)(void *), void *); 108 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 109 bus_size_t, int, bus_dmamap_t *); 110 111 int 112 schizo_match(struct device *parent, cfdata_t match, void *aux) 113 { 114 struct mainbus_attach_args *ma = aux; 115 char *str; 116 117 if (strcmp(ma->ma_name, "pci") != 0) 118 return (0); 119 120 str = prom_getpropstring(ma->ma_node, "model"); 121 if (strcmp(str, "schizo") == 0) 122 return (1); 123 124 str = prom_getpropstring(ma->ma_node, "compatible"); 125 if (strcmp(str, "pci108e,8001") == 0) 126 return (1); 127 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 128 return (1); 129 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 130 return (1); 131 132 return (0); 133 } 134 135 void 136 schizo_attach(struct device *parent, struct device *self, void *aux) 137 { 138 struct schizo_softc *sc = device_private(self); 139 struct mainbus_attach_args *ma = aux; 140 struct schizo_pbm *pbm; 141 struct iommu_state *is; 142 struct pcibus_attach_args pba; 143 uint64_t reg, eccctrl; 144 int *busranges = NULL, nranges; 145 char *str; 146 bool no_sc; 147 148 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 149 str = prom_getpropstring(ma->ma_node, "compatible"); 150 if (strcmp(str, "pci108e,a801") == 0) 151 sc->sc_tomatillo = 1; 152 sc->sc_dev = self; 153 sc->sc_node = ma->ma_node; 154 sc->sc_dmat = ma->ma_dmatag; 155 sc->sc_bustag = ma->ma_bustag; 156 157 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 158 sizeof(struct schizo_regs), 0, 159 &sc->sc_ctrlh)) { 160 aprint_error(": failed to map registers\n"); 161 return; 162 } 163 164 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 165 166 /* enable schizo ecc error interrupts */ 167 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 168 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 169 SCZ_ECCCTRL_UE_INTEN | 170 SCZ_ECCCTRL_CE_INTEN; 171 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 172 173 pbm = kmem_zalloc(sizeof(*pbm), KM_NOSLEEP); 174 if (pbm == NULL) 175 panic("schizo: can't alloc schizo pbm"); 176 177 pbm->sp_sc = sc; 178 pbm->sp_regt = sc->sc_bustag; 179 180 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 181 pbm->sp_bus_a = 1; 182 else 183 pbm->sp_bus_a = 0; 184 185 /* 186 * Map interrupt registers 187 */ 188 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 189 ma->ma_reg[0].ur_len, 190 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 191 aprint_error(": failed to interrupt map registers\n"); 192 return; 193 } 194 195 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 196 &pbm->sp_nrange, (void **)&pbm->sp_range)) 197 panic("schizo: can't get ranges"); 198 199 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 200 (void **)&busranges)) 201 panic("schizo: can't get bus-range"); 202 203 aprint_normal(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 204 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 205 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 206 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 207 aprint_naive("\n"); 208 209 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 210 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 211 offsetof(struct schizo_regs, pbm_b), 212 sizeof(struct schizo_pbm_regs), 213 &pbm->sp_regh)) { 214 panic("schizo: unable to create PBM handle"); 215 } 216 217 is = &pbm->sp_is; 218 pbm->sp_sb.sb_is = is; 219 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 220 if (no_sc) 221 aprint_debug_dev(sc->sc_dev, "no streaming buffers\n"); 222 else { 223 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 224 225 /* 226 * Initialize the strbuf_ctl. 227 * 228 * The flush sync buffer must be 64-byte aligned. 229 */ 230 is->is_sb[0] = &pbm->sp_sb; 231 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 232 233 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 234 offsetof(struct schizo_pbm_regs, strbuf), 235 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 236 } 237 238 aprint_normal_dev(sc->sc_dev, " "); 239 schizo_init_iommu(sc, pbm); 240 241 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 242 pbm->sp_iot = schizo_alloc_io_tag(pbm); 243 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 244 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 245 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 246 (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0); 247 248 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 249 panic("schizo: could not map config space"); 250 251 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 252 &_sparc_pci_chipset); 253 pbm->sp_pc->spc_busmax = busranges[1]; 254 pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode), 255 KM_NOSLEEP); 256 if (pbm->sp_pc->spc_busnode == NULL) 257 panic("schizo: kmem_alloc busnode"); 258 259 pba.pba_bus = busranges[0]; 260 pba.pba_bridgetag = NULL; 261 pba.pba_pc = pbm->sp_pc; 262 pba.pba_flags = pbm->sp_flags; 263 pba.pba_dmat = pbm->sp_dmat; 264 pba.pba_dmat64 = NULL; /* XXX */ 265 pba.pba_memt = pbm->sp_memt; 266 pba.pba_iot = pbm->sp_iot; 267 268 free(busranges, M_DEVBUF); 269 270 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 271 272 /* clear out the bus errors */ 273 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 274 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 275 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 276 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 277 278 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 279 /* enable/disable error interrupts and arbiter */ 280 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 281 reg &= ~SCZ_PCICTRL_SBH_INT; 282 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 283 284 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 285 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 286 SCZ_PCIDIAG_D_INTSYNC); 287 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 288 289 if (pbm->sp_bus_a) 290 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 291 pbm, SCZ_PCIERR_A_INO, "pci_a"); 292 else 293 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 294 pbm, SCZ_PCIERR_B_INO, "pci_b"); 295 296 /* double mapped */ 297 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 298 "ue"); 299 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 300 "ce"); 301 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 302 SCZ_SERR_INO, "safari"); 303 304 if (sc->sc_tomatillo) { 305 /* 306 * Enable the IOCACHE. 307 */ 308 uint64_t iocache_csr; 309 310 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 311 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 312 TOM_IOCACHE_CSR_PEN_RDM | 313 TOM_IOCACHE_CSR_PEN_ONE | 314 TOM_IOCACHE_CSR_PEN_LINE; 315 316 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 317 } 318 319 config_found(sc->sc_dev, &pba, schizo_print); 320 } 321 322 int 323 schizo_ue(void *vsc) 324 { 325 struct schizo_softc *sc = vsc; 326 327 panic("%s: uncorrectable error", device_xname(sc->sc_dev)); 328 return (1); 329 } 330 331 int 332 schizo_ce(void *vsc) 333 { 334 struct schizo_softc *sc = vsc; 335 336 panic("%s: correctable error", device_xname(sc->sc_dev)); 337 return (1); 338 } 339 340 int 341 schizo_pci_error(void *vpbm) 342 { 343 struct schizo_pbm *sp = vpbm; 344 struct schizo_softc *sc = sp->sp_sc; 345 u_int64_t afsr, afar, ctrl, tfar; 346 u_int32_t csr; 347 char bits[128]; 348 349 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 350 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 351 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 352 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 353 354 printf("%s: pci bus %c error\n", device_xname(sc->sc_dev), 355 sp->sp_bus_a ? 'A' : 'B'); 356 357 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 358 printf("PCIAFSR=%s\n", bits); 359 printf("PCIAFAR=%" PRIx64 "\n", afar); 360 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 361 printf("PCICTRL=%s\n", bits); 362 #ifdef PCI_COMMAND_STATUS_BITS 363 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 364 printf("PCICSR=%s\n", bits); 365 #endif 366 367 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 368 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 369 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 370 371 if ((ctrl & TOM_IOMMU_ERR) == 0) 372 goto clear_error; 373 374 if (sc->sc_tomatillo) { 375 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 376 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 377 } 378 379 /* These are non-fatal if target abort was signalled. */ 380 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 381 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 382 ctrl & TOM_IOMMU_BADVA_ERR) { 383 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 384 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 385 goto clear_error; 386 } 387 } 388 } 389 390 panic("%s: fatal", device_xname(sc->sc_dev)); 391 392 clear_error: 393 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 394 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 395 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 396 return (1); 397 } 398 399 int 400 schizo_safari_error(void *vsc) 401 { 402 struct schizo_softc *sc = vsc; 403 404 printf("%s: safari error\n", device_xname(sc->sc_dev)); 405 406 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 407 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 408 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 409 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 410 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 411 412 panic("%s: fatal", device_xname(sc->sc_dev)); 413 return (1); 414 } 415 416 void 417 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 418 { 419 struct iommu_state *is = &pbm->sp_is; 420 int *vdma = NULL, nitem, tsbsize = 7; 421 u_int32_t iobase = -1; 422 char *name; 423 424 /* punch in our copies */ 425 is->is_bustag = pbm->sp_regt; 426 bus_space_subregion(is->is_bustag, pbm->sp_regh, 427 offsetof(struct schizo_pbm_regs, iommu), 428 sizeof(struct iommureg2), 429 &is->is_iommu); 430 431 /* 432 * Separate the men from the boys. If the `virtual-dma' 433 * property exists, use it. 434 */ 435 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 436 (void **)&vdma)) { 437 /* Damn. Gotta use these values. */ 438 iobase = vdma[0]; 439 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 440 switch (vdma[1]) { 441 TSBCASE(1); TSBCASE(2); TSBCASE(3); 442 TSBCASE(4); TSBCASE(5); TSBCASE(6); 443 default: 444 printf("bogus tsb size %x, using 7\n", vdma[1]); 445 TSBCASE(7); 446 } 447 #undef TSBCASE 448 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 449 free(vdma, M_DEVBUF); 450 } else { 451 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 452 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 453 } 454 455 /* give us a nice name.. */ 456 name = (char *)kmem_alloc(32, KM_NOSLEEP); 457 if (name == NULL) 458 459 panic("couldn't kmem_alloc iommu name"); 460 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 461 462 iommu_init(name, is, tsbsize, iobase); 463 } 464 465 int 466 schizo_print(void *aux, const char *p) 467 { 468 469 if (p == NULL) 470 return (UNCONF); 471 return (QUIET); 472 } 473 474 pcireg_t 475 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 476 { 477 struct schizo_pbm *sp = pc->cookie; 478 pcireg_t val = (pcireg_t)~0; 479 480 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 481 if (PCITAG_NODE(tag) != -1) 482 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 483 PCITAG_OFFSET(tag) + reg); 484 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 485 return (val); 486 } 487 488 void 489 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 490 { 491 struct schizo_pbm *sp = pc->cookie; 492 493 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 494 (long)tag, reg, (int)data)); 495 496 /* If we don't know it, just punt it. */ 497 if (PCITAG_NODE(tag) == -1) { 498 DPRINTF(SDB_CONF, (" .. bad addr\n")); 499 return; 500 } 501 502 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 503 PCITAG_OFFSET(tag) + reg, data); 504 DPRINTF(SDB_CONF, (" .. done\n")); 505 } 506 507 void 508 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 509 int (*handler)(void *), void *arg, int ino, const char *what) 510 { 511 struct intrhand *ih; 512 u_int64_t mapoff, clroff; 513 uintptr_t intrregs; 514 515 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 516 ino, sc->sc_ign, handler, arg)); 517 518 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 519 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 520 ino |= sc->sc_ign; 521 522 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 523 mapoff, clroff)); 524 525 ih = (struct intrhand *) 526 kmem_alloc(sizeof(struct intrhand), KM_NOSLEEP); 527 if (ih == NULL) 528 return; 529 ih->ih_arg = arg; 530 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 531 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 532 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 533 ih->ih_fun = handler; 534 ih->ih_pil = (1<<ipl); 535 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 536 ih->ih_pending = 0; 537 538 intr_establish(ipl, ipl != IPL_VM, ih); 539 540 schizo_pbm_write(pbm, mapoff, 541 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 542 } 543 544 bus_space_tag_t 545 schizo_alloc_mem_tag(struct schizo_pbm *sp) 546 { 547 return (schizo_alloc_bus_tag(sp, "mem", 548 PCI_MEMORY_BUS_SPACE)); 549 } 550 551 bus_space_tag_t 552 schizo_alloc_io_tag(struct schizo_pbm *sp) 553 { 554 return (schizo_alloc_bus_tag(sp, "io", 555 PCI_IO_BUS_SPACE)); 556 } 557 558 bus_space_tag_t 559 schizo_alloc_config_tag(struct schizo_pbm *sp) 560 { 561 return (schizo_alloc_bus_tag(sp, "cfg", 562 PCI_CONFIG_BUS_SPACE)); 563 } 564 565 bus_space_tag_t 566 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 567 { 568 struct schizo_softc *sc = pbm->sp_sc; 569 bus_space_tag_t bt; 570 571 bt = (bus_space_tag_t) kmem_zalloc(sizeof(struct sparc_bus_space_tag), 572 KM_NOSLEEP); 573 if (bt == NULL) 574 panic("schizo: could not allocate bus tag"); 575 576 bt->cookie = pbm; 577 bt->parent = sc->sc_bustag; 578 bt->type = type; 579 bt->sparc_bus_map = schizo_bus_map; 580 bt->sparc_bus_mmap = schizo_bus_mmap; 581 bt->sparc_intr_establish = schizo_intr_establish; 582 return (bt); 583 } 584 585 bus_dma_tag_t 586 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 587 { 588 struct schizo_softc *sc = pbm->sp_sc; 589 bus_dma_tag_t dt, pdt = sc->sc_dmat; 590 591 dt = kmem_zalloc(sizeof(*dt), KM_NOSLEEP); 592 if (dt == NULL) 593 panic("schizo: could not alloc dma tag"); 594 595 dt->_cookie = pbm; 596 dt->_parent = pdt; 597 #define PCOPY(x) dt->x = pdt->x 598 dt->_dmamap_create = schizo_dmamap_create; 599 PCOPY(_dmamap_destroy); 600 dt->_dmamap_load = iommu_dvmamap_load; 601 PCOPY(_dmamap_load_mbuf); 602 PCOPY(_dmamap_load_uio); 603 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 604 dt->_dmamap_unload = iommu_dvmamap_unload; 605 dt->_dmamap_sync = iommu_dvmamap_sync; 606 dt->_dmamem_alloc = iommu_dvmamem_alloc; 607 dt->_dmamem_free = iommu_dvmamem_free; 608 dt->_dmamem_map = iommu_dvmamem_map; 609 dt->_dmamem_unmap = iommu_dvmamem_unmap; 610 PCOPY(_dmamem_mmap); 611 #undef PCOPY 612 return (dt); 613 } 614 615 pci_chipset_tag_t 616 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 617 { 618 pci_chipset_tag_t npc; 619 620 npc = kmem_alloc(sizeof *npc, KM_NOSLEEP); 621 if (npc == NULL) 622 panic("schizo: could not allocate pci_chipset_tag_t"); 623 memcpy(npc, pc, sizeof *pc); 624 npc->cookie = pbm; 625 npc->rootnode = node; 626 npc->spc_conf_read = schizo_conf_read; 627 npc->spc_conf_write = schizo_conf_write; 628 npc->spc_intr_map = schizo_pci_intr_map; 629 npc->spc_intr_establish = schizo_pci_intr_establish; 630 npc->spc_find_ino = NULL; 631 return (npc); 632 } 633 634 int 635 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 636 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 637 bus_dmamap_t *dmamp) 638 { 639 struct schizo_pbm *pbm = t->_cookie; 640 int error; 641 642 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 643 boundary, flags, dmamp); 644 if (error == 0) 645 (*dmamp)->_dm_cookie = &pbm->sp_sb; 646 return error; 647 } 648 649 static struct schizo_range * 650 get_schizorange(struct schizo_pbm *pbm, int ss) 651 { 652 int i; 653 654 for (i = 0; i < pbm->sp_nrange; i++) { 655 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 656 return (&pbm->sp_range[i]); 657 } 658 /* not found */ 659 return (NULL); 660 } 661 662 int 663 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 664 int flags, vaddr_t unused, bus_space_handle_t *hp) 665 { 666 bus_addr_t paddr; 667 struct schizo_pbm *pbm = t->cookie; 668 struct schizo_softc *sc = pbm->sp_sc; 669 struct schizo_range *sr; 670 int ss; 671 672 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 673 t->type, 674 (unsigned long long)offset, 675 (unsigned long long)size, 676 flags)); 677 678 ss = sparc_pci_childspace(t->type); 679 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 680 681 sr = get_schizorange(pbm, ss); 682 if (sr != NULL) { 683 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 684 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 685 "space %lx offset %lx paddr %qx\n", 686 __func__, (long)ss, (long)offset, 687 (unsigned long long)paddr)); 688 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 689 flags, 0, hp)); 690 } 691 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 692 return (EINVAL); 693 } 694 695 static paddr_t 696 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 697 int flags) 698 { 699 bus_addr_t offset = paddr; 700 struct schizo_pbm *pbm = t->cookie; 701 struct schizo_softc *sc = pbm->sp_sc; 702 struct schizo_range *sr; 703 int ss; 704 705 ss = sparc_pci_childspace(t->type); 706 707 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 708 prot, flags, (unsigned long long)paddr)); 709 710 sr = get_schizorange(pbm, ss); 711 if (sr != NULL) { 712 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 713 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 714 "space %lx offset %lx paddr %qx\n", 715 __func__, (long)ss, (long)offset, 716 (unsigned long long)paddr)); 717 return (bus_space_mmap(sc->sc_bustag, paddr, off, 718 prot, flags)); 719 } 720 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 721 return (-1); 722 } 723 724 /* 725 * Set the IGN for this schizo into the handle. 726 */ 727 int 728 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 729 { 730 struct schizo_pbm *pbm = pa->pa_pc->cookie; 731 struct schizo_softc *sc = pbm->sp_sc; 732 733 *ihp |= sc->sc_ign; 734 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 735 return (0); 736 } 737 738 static void * 739 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 740 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 741 { 742 struct schizo_pbm *pbm = t->cookie; 743 struct intrhand *ih = NULL; 744 uint64_t mapoff, clroff; 745 uintptr_t intrregs; 746 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 747 int ino; 748 long vec; 749 750 vec = INTVEC(ihandle); 751 ino = INTINO(vec); 752 753 ih = kmem_alloc(sizeof *ih, KM_NOSLEEP); 754 if (ih == NULL) 755 return (NULL); 756 757 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 758 ihandle, level, handler, arg)); 759 760 if (level == IPL_NONE) 761 level = INTLEV(vec); 762 if (level == IPL_NONE) { 763 printf(": no IPL, setting IPL 2.\n"); 764 level = 2; 765 } 766 767 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 768 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 769 770 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 771 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 772 773 ih->ih_ivec = ihandle; 774 775 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 776 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 777 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 778 779 if (INTIGN(vec) == 0) 780 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 781 else 782 ino |= vec & INTMAP_IGN; 783 784 /* Register the map and clear intr registers */ 785 ih->ih_map = intrmapptr; 786 ih->ih_clr = intrclrptr; 787 788 ih->ih_fun = handler; 789 ih->ih_arg = arg; 790 ih->ih_pil = level; 791 ih->ih_number = ino; 792 ih->ih_pending = 0; 793 794 DPRINTF(SDB_INTR, ( 795 "; installing handler %p arg %p with inr %x pil %u\n", 796 handler, arg, ino, (u_int)ih->ih_pil)); 797 798 intr_establish(ih->ih_pil, level != IPL_VM, ih); 799 800 /* 801 * Enable the interrupt now we have the handler installed. 802 * Read the current value as we can't change it besides the 803 * valid bit so so make sure only this bit is changed. 804 */ 805 if (intrmapptr) { 806 u_int64_t imap; 807 808 imap = schizo_pbm_readintr(pbm, mapoff); 809 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 810 (unsigned long long)imap)); 811 imap |= INTMAP_V; 812 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 813 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 814 (unsigned long long)imap)); 815 schizo_pbm_writeintr(pbm, mapoff, imap); 816 imap = schizo_pbm_readintr(pbm, mapoff); 817 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 818 (unsigned long long)imap)); 819 ih->ih_number |= imap & INTMAP_INR; 820 } 821 if (intrclrptr) { 822 /* set state to IDLE */ 823 schizo_pbm_writeintr(pbm, clroff, 0); 824 } 825 826 return (ih); 827 } 828 829 static void * 830 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 831 int (*func)(void *), void *arg) 832 { 833 void *cookie; 834 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 835 836 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 837 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 838 839 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 840 return (cookie); 841 } 842
Indexes created Tue Sep 30 20:09:53 GMT 2025