schizo.c revision 1.28
1 /* $NetBSD: schizo.c,v 1.28 2012/03/18 05:26:58 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.28 2012/03/18 05:26:58 mrg Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/kmem.h> 40 #include <sys/malloc.h> 41 #include <sys/systm.h> 42 #include <sys/time.h> 43 #include <sys/reboot.h> 44 45 #define _SPARC_BUS_DMA_PRIVATE 46 #include <sys/bus.h> 47 #include <machine/autoconf.h> 48 #include <machine/psl.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/dev/iommuvar.h> 55 #include <sparc64/dev/schizoreg.h> 56 #include <sparc64/dev/schizovar.h> 57 #include <sparc64/sparc64/cache.h> 58 59 #ifdef DEBUG 60 #define SDB_PROM 0x01 61 #define SDB_BUSMAP 0x02 62 #define SDB_INTR 0x04 63 #define SDB_INTMAP 0x08 64 #define SDB_CONF 0x10 65 int schizo_debug = 0x0; 66 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 67 #else 68 #define DPRINTF(l, s) 69 #endif 70 71 extern struct sparc_pci_chipset _sparc_pci_chipset; 72 73 static int schizo_match(device_t, cfdata_t, void *); 74 static void schizo_attach(device_t, device_t, void *); 75 static int schizo_print(void *aux, const char *p); 76 77 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc), 78 schizo_match, schizo_attach, NULL, NULL); 79 80 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 81 82 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 83 int (*handler)(void *), void *, int, const char *); 84 int schizo_ue(void *); 85 int schizo_ce(void *); 86 int schizo_safari_error(void *); 87 int schizo_pci_error(void *); 88 89 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 90 pci_chipset_tag_t); 91 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 92 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 93 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 94 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 95 int); 96 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 97 98 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 99 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 100 101 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 102 int flags, vaddr_t unused, bus_space_handle_t *hp); 103 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 104 off_t off, int prot, int flags); 105 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 106 void *, void(*)(void)); 107 static int schizo_pci_intr_map(const struct pci_attach_args *, 108 pci_intr_handle_t *); 109 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 110 int, int (*)(void *), void *); 111 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 112 bus_size_t, int, bus_dmamap_t *); 113 114 int 115 schizo_match(struct device *parent, cfdata_t match, void *aux) 116 { 117 struct mainbus_attach_args *ma = aux; 118 char *str; 119 120 if (strcmp(ma->ma_name, "pci") != 0) 121 return (0); 122 123 str = prom_getpropstring(ma->ma_node, "model"); 124 if (strcmp(str, "schizo") == 0) 125 return (1); 126 127 str = prom_getpropstring(ma->ma_node, "compatible"); 128 if (strcmp(str, "pci108e,8001") == 0) 129 return (1); 130 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 131 return (1); 132 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 133 return (1); 134 135 return (0); 136 } 137 138 void 139 schizo_attach(struct device *parent, struct device *self, void *aux) 140 { 141 struct schizo_softc *sc = device_private(self); 142 struct mainbus_attach_args *ma = aux; 143 struct schizo_pbm *pbm; 144 struct iommu_state *is; 145 struct pcibus_attach_args pba; 146 uint64_t reg, eccctrl; 147 int *busranges = NULL, nranges; 148 char *str; 149 bool no_sc; 150 151 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 152 str = prom_getpropstring(ma->ma_node, "compatible"); 153 if (strcmp(str, "pci108e,a801") == 0) 154 sc->sc_tomatillo = 1; 155 sc->sc_dev = self; 156 sc->sc_node = ma->ma_node; 157 sc->sc_dmat = ma->ma_dmatag; 158 sc->sc_bustag = ma->ma_bustag; 159 160 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 161 sizeof(struct schizo_regs), 0, 162 &sc->sc_ctrlh)) { 163 aprint_error(": failed to map registers\n"); 164 return; 165 } 166 167 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 168 169 /* enable schizo ecc error interrupts */ 170 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 171 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 172 SCZ_ECCCTRL_UE_INTEN | 173 SCZ_ECCCTRL_CE_INTEN; 174 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 175 176 pbm = kmem_zalloc(sizeof(*pbm), KM_NOSLEEP); 177 if (pbm == NULL) 178 panic("schizo: can't alloc schizo pbm"); 179 180 pbm->sp_sc = sc; 181 pbm->sp_regt = sc->sc_bustag; 182 183 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 184 pbm->sp_bus_a = 1; 185 else 186 pbm->sp_bus_a = 0; 187 188 /* 189 * Map interrupt registers 190 */ 191 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 192 ma->ma_reg[0].ur_len, 193 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 194 aprint_error(": failed to interrupt map registers\n"); 195 return; 196 } 197 198 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 199 &pbm->sp_nrange, (void **)&pbm->sp_range)) 200 panic("schizo: can't get ranges"); 201 202 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 203 (void **)&busranges)) 204 panic("schizo: can't get bus-range"); 205 206 aprint_normal(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 207 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 208 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 209 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 210 aprint_naive("\n"); 211 212 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 213 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 214 offsetof(struct schizo_regs, pbm_b), 215 sizeof(struct schizo_pbm_regs), 216 &pbm->sp_regh)) { 217 panic("schizo: unable to create PBM handle"); 218 } 219 220 is = &pbm->sp_is; 221 pbm->sp_sb.sb_is = is; 222 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 223 if (no_sc) 224 aprint_debug_dev(sc->sc_dev, "no streaming buffers\n"); 225 else { 226 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 227 228 /* 229 * Initialize the strbuf_ctl. 230 * 231 * The flush sync buffer must be 64-byte aligned. 232 */ 233 is->is_sb[0] = &pbm->sp_sb; 234 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 235 236 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 237 offsetof(struct schizo_pbm_regs, strbuf), 238 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 239 } 240 241 aprint_normal_dev(sc->sc_dev, " "); 242 schizo_init_iommu(sc, pbm); 243 244 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 245 pbm->sp_iot = schizo_alloc_io_tag(pbm); 246 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 247 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 248 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 249 (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0); 250 251 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 252 panic("schizo: could not map config space"); 253 254 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 255 &_sparc_pci_chipset); 256 pbm->sp_pc->spc_busmax = busranges[1]; 257 pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode), 258 KM_NOSLEEP); 259 if (pbm->sp_pc->spc_busnode == NULL) 260 panic("schizo: kmem_alloc busnode"); 261 262 pba.pba_bus = busranges[0]; 263 pba.pba_bridgetag = NULL; 264 pba.pba_pc = pbm->sp_pc; 265 pba.pba_flags = pbm->sp_flags; 266 pba.pba_dmat = pbm->sp_dmat; 267 pba.pba_dmat64 = NULL; /* XXX */ 268 pba.pba_memt = pbm->sp_memt; 269 pba.pba_iot = pbm->sp_iot; 270 271 free(busranges, M_DEVBUF); 272 273 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 274 275 /* clear out the bus errors */ 276 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 277 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 278 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 279 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 280 281 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 282 /* enable/disable error interrupts and arbiter */ 283 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 284 reg &= ~SCZ_PCICTRL_SBH_INT; 285 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 286 287 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 288 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 289 SCZ_PCIDIAG_D_INTSYNC); 290 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 291 292 if (pbm->sp_bus_a) 293 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 294 pbm, SCZ_PCIERR_A_INO, "pci_a"); 295 else 296 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 297 pbm, SCZ_PCIERR_B_INO, "pci_b"); 298 299 /* double mapped */ 300 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 301 "ue"); 302 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 303 "ce"); 304 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 305 SCZ_SERR_INO, "safari"); 306 307 if (sc->sc_tomatillo) { 308 /* 309 * Enable the IOCACHE. 310 */ 311 uint64_t iocache_csr; 312 313 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 314 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 315 TOM_IOCACHE_CSR_PEN_RDM | 316 TOM_IOCACHE_CSR_PEN_ONE | 317 TOM_IOCACHE_CSR_PEN_LINE; 318 319 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 320 } 321 322 config_found(sc->sc_dev, &pba, schizo_print); 323 } 324 325 int 326 schizo_ue(void *vsc) 327 { 328 struct schizo_softc *sc = vsc; 329 330 panic("%s: uncorrectable error", device_xname(sc->sc_dev)); 331 return (1); 332 } 333 334 int 335 schizo_ce(void *vsc) 336 { 337 struct schizo_softc *sc = vsc; 338 339 panic("%s: correctable error", device_xname(sc->sc_dev)); 340 return (1); 341 } 342 343 int 344 schizo_pci_error(void *vpbm) 345 { 346 struct schizo_pbm *sp = vpbm; 347 struct schizo_softc *sc = sp->sp_sc; 348 u_int64_t afsr, afar, ctrl, tfar; 349 u_int32_t csr; 350 char bits[128]; 351 352 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 353 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 354 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 355 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 356 357 printf("%s: pci bus %c error\n", device_xname(sc->sc_dev), 358 sp->sp_bus_a ? 'A' : 'B'); 359 360 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 361 printf("PCIAFSR=%s\n", bits); 362 printf("PCIAFAR=%" PRIx64 "\n", afar); 363 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 364 printf("PCICTRL=%s\n", bits); 365 #ifdef PCI_COMMAND_STATUS_BITS 366 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 367 printf("PCICSR=%s\n", bits); 368 #endif 369 370 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 371 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 372 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 373 374 if ((ctrl & TOM_IOMMU_ERR) == 0) 375 goto clear_error; 376 377 if (sc->sc_tomatillo) { 378 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 379 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 380 } 381 382 /* These are non-fatal if target abort was signalled. */ 383 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 384 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 385 ctrl & TOM_IOMMU_BADVA_ERR) { 386 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 387 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 388 goto clear_error; 389 } 390 } 391 } 392 393 panic("%s: fatal", device_xname(sc->sc_dev)); 394 395 clear_error: 396 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 397 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 398 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 399 return (1); 400 } 401 402 int 403 schizo_safari_error(void *vsc) 404 { 405 struct schizo_softc *sc = vsc; 406 407 printf("%s: safari error\n", device_xname(sc->sc_dev)); 408 409 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 410 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 411 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 412 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 413 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 414 415 panic("%s: fatal", device_xname(sc->sc_dev)); 416 return (1); 417 } 418 419 void 420 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 421 { 422 struct iommu_state *is = &pbm->sp_is; 423 int *vdma = NULL, nitem, tsbsize = 7; 424 u_int32_t iobase = -1; 425 char *name; 426 427 /* punch in our copies */ 428 is->is_bustag = pbm->sp_regt; 429 bus_space_subregion(is->is_bustag, pbm->sp_regh, 430 offsetof(struct schizo_pbm_regs, iommu), 431 sizeof(struct iommureg2), 432 &is->is_iommu); 433 434 /* 435 * Separate the men from the boys. If the `virtual-dma' 436 * property exists, use it. 437 */ 438 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 439 (void **)&vdma)) { 440 /* Damn. Gotta use these values. */ 441 iobase = vdma[0]; 442 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 443 switch (vdma[1]) { 444 TSBCASE(1); TSBCASE(2); TSBCASE(3); 445 TSBCASE(4); TSBCASE(5); TSBCASE(6); 446 default: 447 printf("bogus tsb size %x, using 7\n", vdma[1]); 448 TSBCASE(7); 449 } 450 #undef TSBCASE 451 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 452 free(vdma, M_DEVBUF); 453 } else { 454 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 455 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 456 } 457 458 /* give us a nice name.. */ 459 name = (char *)kmem_alloc(32, KM_NOSLEEP); 460 if (name == NULL) 461 462 panic("couldn't kmem_alloc iommu name"); 463 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 464 465 iommu_init(name, is, tsbsize, iobase); 466 } 467 468 int 469 schizo_print(void *aux, const char *p) 470 { 471 472 if (p == NULL) 473 return (UNCONF); 474 return (QUIET); 475 } 476 477 pcireg_t 478 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 479 { 480 struct schizo_pbm *sp = pc->cookie; 481 pcireg_t val = (pcireg_t)~0; 482 483 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 484 if (PCITAG_NODE(tag) != -1) 485 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 486 PCITAG_OFFSET(tag) + reg); 487 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 488 return (val); 489 } 490 491 void 492 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 493 { 494 struct schizo_pbm *sp = pc->cookie; 495 496 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 497 (long)tag, reg, (int)data)); 498 499 /* If we don't know it, just punt it. */ 500 if (PCITAG_NODE(tag) == -1) { 501 DPRINTF(SDB_CONF, (" .. bad addr\n")); 502 return; 503 } 504 505 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 506 PCITAG_OFFSET(tag) + reg, data); 507 DPRINTF(SDB_CONF, (" .. done\n")); 508 } 509 510 void 511 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 512 int (*handler)(void *), void *arg, int ino, const char *what) 513 { 514 struct intrhand *ih; 515 u_int64_t mapoff, clroff; 516 uintptr_t intrregs; 517 518 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 519 ino, sc->sc_ign, handler, arg)); 520 521 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 522 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 523 ino |= sc->sc_ign; 524 525 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 526 mapoff, clroff)); 527 528 ih = (struct intrhand *) 529 kmem_alloc(sizeof(struct intrhand), KM_NOSLEEP); 530 if (ih == NULL) 531 return; 532 ih->ih_arg = arg; 533 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 534 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 535 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 536 ih->ih_fun = handler; 537 ih->ih_pil = ipl; 538 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 539 ih->ih_pending = 0; 540 541 intr_establish(ipl, ipl != IPL_VM, ih); 542 543 schizo_pbm_write(pbm, mapoff, 544 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 545 } 546 547 bus_space_tag_t 548 schizo_alloc_mem_tag(struct schizo_pbm *sp) 549 { 550 return (schizo_alloc_bus_tag(sp, "mem", 551 PCI_MEMORY_BUS_SPACE)); 552 } 553 554 bus_space_tag_t 555 schizo_alloc_io_tag(struct schizo_pbm *sp) 556 { 557 return (schizo_alloc_bus_tag(sp, "io", 558 PCI_IO_BUS_SPACE)); 559 } 560 561 bus_space_tag_t 562 schizo_alloc_config_tag(struct schizo_pbm *sp) 563 { 564 return (schizo_alloc_bus_tag(sp, "cfg", 565 PCI_CONFIG_BUS_SPACE)); 566 } 567 568 bus_space_tag_t 569 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 570 { 571 struct schizo_softc *sc = pbm->sp_sc; 572 bus_space_tag_t bt; 573 574 bt = (bus_space_tag_t) kmem_zalloc(sizeof(struct sparc_bus_space_tag), 575 KM_NOSLEEP); 576 if (bt == NULL) 577 panic("schizo: could not allocate bus tag"); 578 579 bt->cookie = pbm; 580 bt->parent = sc->sc_bustag; 581 bt->type = type; 582 bt->sparc_bus_map = schizo_bus_map; 583 bt->sparc_bus_mmap = schizo_bus_mmap; 584 bt->sparc_intr_establish = schizo_intr_establish; 585 return (bt); 586 } 587 588 bus_dma_tag_t 589 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 590 { 591 struct schizo_softc *sc = pbm->sp_sc; 592 bus_dma_tag_t dt, pdt = sc->sc_dmat; 593 594 dt = kmem_zalloc(sizeof(*dt), KM_NOSLEEP); 595 if (dt == NULL) 596 panic("schizo: could not alloc dma tag"); 597 598 dt->_cookie = pbm; 599 dt->_parent = pdt; 600 #define PCOPY(x) dt->x = pdt->x 601 dt->_dmamap_create = schizo_dmamap_create; 602 PCOPY(_dmamap_destroy); 603 dt->_dmamap_load = iommu_dvmamap_load; 604 PCOPY(_dmamap_load_mbuf); 605 PCOPY(_dmamap_load_uio); 606 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 607 dt->_dmamap_unload = iommu_dvmamap_unload; 608 dt->_dmamap_sync = iommu_dvmamap_sync; 609 dt->_dmamem_alloc = iommu_dvmamem_alloc; 610 dt->_dmamem_free = iommu_dvmamem_free; 611 dt->_dmamem_map = iommu_dvmamem_map; 612 dt->_dmamem_unmap = iommu_dvmamem_unmap; 613 PCOPY(_dmamem_mmap); 614 #undef PCOPY 615 return (dt); 616 } 617 618 pci_chipset_tag_t 619 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 620 { 621 pci_chipset_tag_t npc; 622 623 npc = kmem_alloc(sizeof *npc, KM_NOSLEEP); 624 if (npc == NULL) 625 panic("schizo: could not allocate pci_chipset_tag_t"); 626 memcpy(npc, pc, sizeof *pc); 627 npc->cookie = pbm; 628 npc->rootnode = node; 629 npc->spc_conf_read = schizo_conf_read; 630 npc->spc_conf_write = schizo_conf_write; 631 npc->spc_intr_map = schizo_pci_intr_map; 632 npc->spc_intr_establish = schizo_pci_intr_establish; 633 npc->spc_find_ino = NULL; 634 return (npc); 635 } 636 637 int 638 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 639 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 640 bus_dmamap_t *dmamp) 641 { 642 struct schizo_pbm *pbm = t->_cookie; 643 int error; 644 645 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 646 boundary, flags, dmamp); 647 if (error == 0) 648 (*dmamp)->_dm_cookie = &pbm->sp_sb; 649 return error; 650 } 651 652 static struct schizo_range * 653 get_schizorange(struct schizo_pbm *pbm, int ss) 654 { 655 int i; 656 657 for (i = 0; i < pbm->sp_nrange; i++) { 658 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 659 return (&pbm->sp_range[i]); 660 } 661 /* not found */ 662 return (NULL); 663 } 664 665 int 666 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 667 int flags, vaddr_t unused, bus_space_handle_t *hp) 668 { 669 bus_addr_t paddr; 670 struct schizo_pbm *pbm = t->cookie; 671 struct schizo_softc *sc = pbm->sp_sc; 672 struct schizo_range *sr; 673 int ss; 674 675 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 676 t->type, 677 (unsigned long long)offset, 678 (unsigned long long)size, 679 flags)); 680 681 ss = sparc_pci_childspace(t->type); 682 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 683 684 sr = get_schizorange(pbm, ss); 685 if (sr != NULL) { 686 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 687 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 688 "space %lx offset %lx paddr %qx\n", 689 __func__, (long)ss, (long)offset, 690 (unsigned long long)paddr)); 691 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 692 flags, 0, hp)); 693 } 694 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 695 return (EINVAL); 696 } 697 698 static paddr_t 699 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 700 int flags) 701 { 702 bus_addr_t offset = paddr; 703 struct schizo_pbm *pbm = t->cookie; 704 struct schizo_softc *sc = pbm->sp_sc; 705 struct schizo_range *sr; 706 int ss; 707 708 ss = sparc_pci_childspace(t->type); 709 710 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 711 prot, flags, (unsigned long long)paddr)); 712 713 sr = get_schizorange(pbm, ss); 714 if (sr != NULL) { 715 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 716 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 717 "space %lx offset %lx paddr %qx\n", 718 __func__, (long)ss, (long)offset, 719 (unsigned long long)paddr)); 720 return (bus_space_mmap(sc->sc_bustag, paddr, off, 721 prot, flags)); 722 } 723 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 724 return (-1); 725 } 726 727 /* 728 * Set the IGN for this schizo into the handle. 729 */ 730 int 731 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 732 { 733 struct schizo_pbm *pbm = pa->pa_pc->cookie; 734 struct schizo_softc *sc = pbm->sp_sc; 735 736 *ihp |= sc->sc_ign; 737 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 738 return (0); 739 } 740 741 static void * 742 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 743 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 744 { 745 struct schizo_pbm *pbm = t->cookie; 746 struct intrhand *ih = NULL; 747 uint64_t mapoff, clroff; 748 uintptr_t intrregs; 749 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 750 int ino; 751 long vec; 752 753 vec = INTVEC(ihandle); 754 ino = INTINO(vec); 755 756 ih = kmem_alloc(sizeof *ih, KM_NOSLEEP); 757 if (ih == NULL) 758 return (NULL); 759 760 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 761 ihandle, level, handler, arg)); 762 763 if (level == IPL_NONE) 764 level = INTLEV(vec); 765 if (level == IPL_NONE) { 766 printf(": no IPL, setting IPL 2.\n"); 767 level = 2; 768 } 769 770 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 771 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 772 773 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 774 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 775 776 ih->ih_ivec = ihandle; 777 778 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 779 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 780 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 781 782 if (INTIGN(vec) == 0) 783 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 784 else 785 ino |= vec & INTMAP_IGN; 786 787 /* Register the map and clear intr registers */ 788 ih->ih_map = intrmapptr; 789 ih->ih_clr = intrclrptr; 790 791 ih->ih_fun = handler; 792 ih->ih_arg = arg; 793 ih->ih_pil = level; 794 ih->ih_number = ino; 795 ih->ih_pending = 0; 796 797 DPRINTF(SDB_INTR, ( 798 "; installing handler %p arg %p with inr %x pil %u\n", 799 handler, arg, ino, (u_int)ih->ih_pil)); 800 801 intr_establish(ih->ih_pil, level != IPL_VM, ih); 802 803 /* 804 * Enable the interrupt now we have the handler installed. 805 * Read the current value as we can't change it besides the 806 * valid bit so so make sure only this bit is changed. 807 */ 808 if (intrmapptr) { 809 u_int64_t imap; 810 811 imap = schizo_pbm_readintr(pbm, mapoff); 812 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 813 (unsigned long long)imap)); 814 imap |= INTMAP_V; 815 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 816 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 817 (unsigned long long)imap)); 818 schizo_pbm_writeintr(pbm, mapoff, imap); 819 imap = schizo_pbm_readintr(pbm, mapoff); 820 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 821 (unsigned long long)imap)); 822 ih->ih_number |= imap & INTMAP_INR; 823 } 824 if (intrclrptr) { 825 /* set state to IDLE */ 826 schizo_pbm_writeintr(pbm, clroff, 0); 827 } 828 829 return (ih); 830 } 831 832 static void * 833 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 834 int (*func)(void *), void *arg) 835 { 836 void *cookie; 837 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 838 839 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 840 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 841 842 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 843 return (cookie); 844 } 845
Indexes created Tue Sep 30 20:09:53 GMT 2025