schizo.c revision 1.3
1 /* $NetBSD: schizo.c,v 1.3 2008/12/10 12:17:02 nakayama Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/extent.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/time.h> 38 #include <sys/reboot.h> 39 40 #define _SPARC_BUS_DMA_PRIVATE 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/psl.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <sparc64/dev/iommureg.h> 49 #include <sparc64/dev/iommuvar.h> 50 #include <sparc64/dev/schizoreg.h> 51 #include <sparc64/dev/schizovar.h> 52 #include <sparc64/sparc64/cache.h> 53 54 #ifdef DEBUG 55 #define SDB_PROM 0x01 56 #define SDB_BUSMAP 0x02 57 #define SDB_INTR 0x04 58 #define SDB_INTMAP 0x08 59 #define SDB_CONF 0x10 60 int schizo_debug = 0x0f; 61 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 62 #else 63 #define DPRINTF(l, s) 64 #endif 65 66 extern struct sparc_pci_chipset _sparc_pci_chipset; 67 68 static int schizo_match(struct device *, struct cfdata *, void *); 69 static void schizo_attach(struct device *, struct device *, void *); 70 static int schizo_print(void *aux, const char *p); 71 72 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 73 schizo_match, schizo_attach, NULL, NULL); 74 75 void schizo_init(struct schizo_softc *, int, struct mainbus_attach_args *); 76 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 77 78 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 79 int (*handler)(void *), void *, int, const char *); 80 int schizo_ue(void *); 81 int schizo_ce(void *); 82 int schizo_safari_error(void *); 83 int schizo_pci_error(void *); 84 85 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 86 pci_chipset_tag_t); 87 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 91 int); 92 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 93 94 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 97 int schizo_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 98 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 99 int flags, vaddr_t unused, bus_space_handle_t *hp); 100 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 101 off_t off, int prot, int flags); 102 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 103 void *, void(*)(void)); 104 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 105 int, int (*)(void *), void *); 106 static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 107 108 int 109 schizo_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct mainbus_attach_args *ma = aux; 112 char *str; 113 114 if (strcmp(ma->ma_name, "pci") != 0) 115 return (0); 116 117 str = prom_getpropstring(ma->ma_node, "model"); 118 if (strcmp(str, "schizo") == 0) 119 return (1); 120 121 str = prom_getpropstring(ma->ma_node, "compatible"); 122 if (strcmp(str, "pci108e,8001") == 0) 123 return (1); 124 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 125 return (1); 126 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 127 return (1); 128 129 return (0); 130 } 131 132 void 133 schizo_attach(struct device *parent, struct device *self, void *aux) 134 { 135 struct schizo_softc *sc = (struct schizo_softc *)self; 136 struct mainbus_attach_args *ma = aux; 137 uint64_t eccctrl; 138 int busa; 139 char *str; 140 141 printf(": addr %lx ", ma->ma_reg[0].ur_paddr); 142 str = prom_getpropstring(ma->ma_node, "compatible"); 143 if (strcmp(str, "pci108e,a801") == 0) 144 sc->sc_tomatillo = 1; 145 146 sc->sc_node = ma->ma_node; 147 sc->sc_dmat = ma->ma_dmatag; 148 sc->sc_bustag = ma->ma_bustag; 149 sc->sc_ctrl = ma->ma_reg[1].ur_paddr - 0x10000UL; 150 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 151 152 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 153 busa = 1; 154 else 155 busa = 0; 156 157 printf("bustag->type = %d\n", sc->sc_bustag->type); 158 if (bus_space_map(sc->sc_bustag, sc->sc_ctrl, 159 sizeof(struct schizo_regs), 0, 160 &sc->sc_ctrlh)) { 161 printf(": failed to map registers\n"); 162 return; 163 } 164 printf("mapped regs len %zx, sc_ctrl = %lx sc_ctrlh._ptr = %lx ._asi = %x ._sasi = %x\n", sizeof(struct schizo_regs), (uint64_t)sc->sc_ctrl, sc->sc_ctrlh._ptr, sc->sc_ctrlh._asi, sc->sc_ctrlh._sasi); 165 166 /* enable schizo ecc error interrupts */ 167 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 168 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 169 SCZ_ECCCTRL_UE_INTEN | 170 SCZ_ECCCTRL_CE_INTEN; 171 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 172 173 schizo_init(sc, busa, ma); 174 } 175 176 void 177 schizo_init(struct schizo_softc *sc, int busa, struct mainbus_attach_args *ma) 178 { 179 struct schizo_pbm *pbm; 180 struct pcibus_attach_args pba; 181 int *busranges = NULL, nranges; 182 u_int64_t /*match,*/ reg; 183 184 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 185 if (pbm == NULL) 186 panic("schizo: can't alloc schizo pbm"); 187 188 pbm->sp_sc = sc; 189 pbm->sp_bus_a = busa; 190 pbm->sp_regt = sc->sc_bustag; 191 192 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 193 &pbm->sp_nrange, (void **)&pbm->sp_range)) 194 panic("schizo: can't get ranges"); 195 196 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 197 (void **)&busranges)) 198 panic("schizo: can't get bus-range"); 199 200 printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 201 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 202 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 203 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 204 205 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 206 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 207 offsetof(struct schizo_regs, pbm_b), 208 sizeof(struct schizo_pbm_regs), 209 &pbm->sp_regh)) { 210 panic("schizo: unable to create PBM handle"); 211 } 212 printf("mapped regs, sp_regh._ptr = %lx ._asi = %x ._sasi = %x\n", pbm->sp_regh._ptr, pbm->sp_regh._asi, pbm->sp_regh._sasi); 213 214 printf("%s: ", sc->sc_dv.dv_xname); 215 schizo_init_iommu(sc, pbm); 216 217 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 218 pbm->sp_iot = schizo_alloc_io_tag(pbm); 219 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 220 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 221 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 222 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 223 224 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 225 panic("schizo: could not map config space"); 226 printf("mapped regs, sp_cfgh._ptr = %lx ._asi = %x ._sasi = %x\n", pbm->sp_cfgh._ptr, pbm->sp_cfgh._asi, pbm->sp_cfgh._sasi); 227 228 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 229 &_sparc_pci_chipset); 230 pbm->sp_pc->spc_busmax = busranges[1]; 231 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 232 M_DEVBUF, M_NOWAIT | M_ZERO); 233 if (pbm->sp_pc->spc_busnode == NULL) 234 panic("schizo: malloc busnode"); 235 236 pba.pba_bus = busranges[0]; 237 pba.pba_bridgetag = NULL; 238 pba.pba_pc = pbm->sp_pc; 239 pba.pba_flags = pbm->sp_flags; 240 pba.pba_dmat = pbm->sp_dmat; 241 pba.pba_dmat64 = NULL; /* XXX */ 242 pba.pba_memt = pbm->sp_memt; 243 pba.pba_iot = pbm->sp_iot; 244 #if 0 245 pba.pba_pc->intr_map = schizo_intr_map; 246 #endif 247 248 free(busranges, M_DEVBUF); 249 250 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 251 252 /* clear out the bus errors */ 253 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 254 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 255 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 256 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 257 258 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 259 /* enable/disable error interrupts and arbiter */ 260 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 261 reg &= ~SCZ_PCICTRL_SBH_INT; 262 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 263 264 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 265 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 266 SCZ_PCIDIAG_D_INTSYNC); 267 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 268 269 if (pbm->sp_bus_a) 270 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 271 pbm, SCZ_PCIERR_A_INO, "pci_a"); 272 else 273 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 274 pbm, SCZ_PCIERR_B_INO, "pci_b"); 275 276 /* double mapped */ 277 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 278 "ue"); 279 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 280 "ce"); 281 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 282 SCZ_SERR_INO, "safari"); 283 284 config_found(&sc->sc_dv, &pba, schizo_print); 285 } 286 287 int 288 schizo_ue(void *vsc) 289 { 290 struct schizo_softc *sc = vsc; 291 292 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 293 return (1); 294 } 295 296 int 297 schizo_ce(void *vsc) 298 { 299 struct schizo_softc *sc = vsc; 300 301 panic("%s: correctable error", sc->sc_dv.dv_xname); 302 return (1); 303 } 304 305 int 306 schizo_pci_error(void *vpbm) 307 { 308 struct schizo_pbm *sp = vpbm; 309 struct schizo_softc *sc = sp->sp_sc; 310 u_int64_t afsr, afar, ctrl, tfar; 311 u_int32_t csr; 312 char bits[128]; 313 314 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 315 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 316 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 317 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 318 319 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 320 sp->sp_bus_a ? 'A' : 'B'); 321 322 printf("PCIAFSR=%s\n", bitmask_snprintf(afsr, SCZ_PCIAFSR_BITS, 323 bits, sizeof(bits))); 324 printf("PCIAFAR=%lx\n", afar); 325 printf("PCICTRL=%s\n", bitmask_snprintf(ctrl, SCZ_PCICTRL_BITS, 326 bits, sizeof(bits))); 327 #ifdef PCI_COMMAND_STATUS_BITS 328 printf("PCICSR=%s\n", bitmask_snprintf(csr, PCI_COMMAND_STATUS_BITS, 329 bits, sizeof(bits))); 330 #endif 331 332 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 333 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 334 printf("IOMMUCTRL=%lx\n", ctrl); 335 336 if ((ctrl & TOM_IOMMU_ERR) == 0) 337 goto clear_error; 338 339 if (sc->sc_tomatillo) { 340 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 341 printf("IOMMUTFAR=%lx\n", tfar); 342 } 343 344 /* These are non-fatal if target abort was signalled. */ 345 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 346 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 347 ctrl & TOM_IOMMU_BADVA_ERR) { 348 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 349 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 350 goto clear_error; 351 } 352 } 353 } 354 355 panic("%s: fatal", sc->sc_dv.dv_xname); 356 357 clear_error: 358 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 359 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 360 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 361 return (1); 362 } 363 364 int 365 schizo_safari_error(void *vsc) 366 { 367 struct schizo_softc *sc = vsc; 368 369 printf("%s: safari error\n", sc->sc_dv.dv_xname); 370 371 printf("ERRLOG=%lx\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 372 printf("UE_AFSR=%lx\n", schizo_read(sc, SCZ_UE_AFSR)); 373 printf("UE_AFAR=%lx\n", schizo_read(sc, SCZ_UE_AFAR)); 374 printf("CE_AFSR=%lx\n", schizo_read(sc, SCZ_CE_AFSR)); 375 printf("CE_AFAR=%lx\n", schizo_read(sc, SCZ_CE_AFAR)); 376 377 panic("%s: fatal", sc->sc_dv.dv_xname); 378 return (1); 379 } 380 381 void 382 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 383 { 384 struct iommu_state *is = &pbm->sp_is; 385 int *vdma = NULL, nitem, tsbsize = 7; 386 u_int32_t iobase = -1; 387 vaddr_t va; 388 char *name; 389 390 va = (vaddr_t)pbm->sp_flush[0x40]; 391 392 is->is_bustag = pbm->sp_regt; 393 394 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 395 offsetof(struct schizo_pbm_regs, iommu), 396 sizeof(struct iommureg), &is->is_iommu)) { 397 panic("schizo: unable to create iommu handle"); 398 } 399 400 is->is_sb[0] = &pbm->sp_sb; 401 // XXXSCHIZO? 402 //is->is_sb[0]->sb_bustag = is->is_bustag; 403 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 404 405 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 406 offsetof(struct schizo_pbm_regs, strbuf), 407 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb)) { 408 panic("schizo: unable to create streaming buffer handle"); 409 is->is_sb[0]->sb_flush = NULL; 410 } 411 412 #if 1 413 /* XXX disable the streaming buffers for now */ 414 bus_space_write_8(is->is_bustag, is->is_sb[0]->sb_sb, 415 STRBUFREG(strbuf_ctl), 416 bus_space_read_8(is->is_bustag, is->is_sb[0]->sb_sb, 417 STRBUFREG(strbuf_ctl)) & ~STRBUF_EN); 418 is->is_sb[0]->sb_flush = NULL; 419 #endif 420 421 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 422 if (name == NULL) 423 panic("couldn't malloc iommu name"); 424 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 425 426 /* 427 * Separate the men from the boys. If the `virtual-dma' 428 * property exists, use it. 429 */ 430 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 431 (void **)&vdma)) { 432 /* Damn. Gotta use these values. */ 433 iobase = vdma[0]; 434 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 435 switch (vdma[1]) { 436 TSBCASE(1); TSBCASE(2); TSBCASE(3); 437 TSBCASE(4); TSBCASE(5); TSBCASE(6); 438 default: 439 printf("bogus tsb size %x, using 7\n", vdma[1]); 440 TSBCASE(7); 441 } 442 #undef TSBCASE 443 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 444 free(vdma, M_DEVBUF); 445 } else { 446 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 447 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 448 } 449 450 iommu_init(name, is, tsbsize, iobase); 451 } 452 453 int 454 schizo_print(void *aux, const char *p) 455 { 456 457 if (p == NULL) 458 return (UNCONF); 459 return (QUIET); 460 } 461 462 pcireg_t 463 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 464 { 465 struct schizo_pbm *sp = pc->cookie; 466 pcireg_t val; 467 468 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 469 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 470 PCITAG_OFFSET(tag) + reg); 471 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 472 return (val); 473 } 474 475 void 476 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 477 { 478 struct schizo_pbm *sp = pc->cookie; 479 480 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 481 (long)tag, reg, (int)data)); 482 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 483 PCITAG_OFFSET(tag) + reg, data); 484 DPRINTF(SDB_CONF, (" .. done\n")); 485 } 486 487 #if 0 488 /* 489 * Bus-specific interrupt mapping 490 */ 491 int 492 schizo_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 493 { 494 struct schizo_pbm *sp = pa->pa_pc->cookie; 495 struct schizo_softc *sc = sp->sp_sc; 496 u_int dev; 497 498 if (*ihp != (pci_intr_handle_t)-1) { 499 *ihp |= sc->sc_ign; 500 return (0); 501 } 502 503 /* 504 * We didn't find a PROM mapping for this interrupt. Try to 505 * construct one ourselves based on the swizzled interrupt pin 506 * and the interrupt mapping for PCI slots documented in the 507 * UltraSPARC-IIi User's Manual. 508 */ 509 510 if (pa->pa_intrpin == 0) 511 return (-1); 512 513 /* 514 * This deserves some documentation. Should anyone 515 * have anything official looking, please speak up. 516 */ 517 dev = pa->pa_device - 1; 518 519 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 520 *ihp |= (dev << 2) & INTMAP_PCISLOT; 521 *ihp |= sc->sc_ign; 522 523 return (0); 524 } 525 #endif 526 527 void 528 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 529 int (*handler)(void *), void *arg, int ino, const char *what) 530 { 531 struct intrhand *ih; 532 //volatile u_int64_t *map, *clr; 533 //struct schizo_pbm_regs *pbmreg; 534 u_int64_t mapoff, clroff; 535 536 //pbmreg = bus_space_vaddr(pbm->sp_regt, pbm->sp_regh); 537 //map = &pbmreg->imap[ino]; 538 //clr = &pbmreg->iclr[ino]; 539 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 540 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 541 ino |= sc->sc_ign; 542 543 ih = (struct intrhand *) 544 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 545 if (ih == NULL) 546 return; 547 ih->ih_arg = arg; 548 //ih->ih_map = map; 549 //ih->ih_clr = clr; 550 ih->ih_map = (uint64_t *)mapoff; // XXX FIXME 551 ih->ih_clr = (uint64_t *)clroff; // XXX FIXME 552 ih->ih_fun = handler; 553 ih->ih_pil = (1<<ipl); 554 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 555 intr_establish(ipl, ipl != IPL_VM, ih); 556 557 schizo_pbm_write(pbm, mapoff, 558 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 559 560 } 561 562 bus_space_tag_t 563 schizo_alloc_mem_tag(struct schizo_pbm *sp) 564 { 565 return (schizo_alloc_bus_tag(sp, "mem", 566 PCI_MEMORY_BUS_SPACE)); 567 } 568 569 bus_space_tag_t 570 schizo_alloc_io_tag(struct schizo_pbm *sp) 571 { 572 return (schizo_alloc_bus_tag(sp, "io", 573 PCI_IO_BUS_SPACE)); 574 } 575 576 bus_space_tag_t 577 schizo_alloc_config_tag(struct schizo_pbm *sp) 578 { 579 return (schizo_alloc_bus_tag(sp, "cfg", 580 PCI_CONFIG_BUS_SPACE)); 581 } 582 583 bus_space_tag_t 584 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 585 { 586 struct schizo_softc *sc = pbm->sp_sc; 587 bus_space_tag_t bt; 588 589 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 590 M_DEVBUF, M_NOWAIT | M_ZERO); 591 if (bt == NULL) 592 panic("schizo: could not allocate bus tag"); 593 594 bt->cookie = pbm; 595 bt->parent = sc->sc_bustag; 596 bt->type = type; 597 bt->sparc_bus_map = schizo_bus_map; 598 bt->sparc_bus_mmap = schizo_bus_mmap; 599 bt->sparc_intr_establish = schizo_intr_establish; 600 return (bt); 601 } 602 603 bus_dma_tag_t 604 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 605 { 606 struct schizo_softc *sc = pbm->sp_sc; 607 bus_dma_tag_t dt, pdt = sc->sc_dmat; 608 609 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 610 if (dt == NULL) 611 panic("schizo: could not alloc dma tag"); 612 613 dt->_cookie = pbm; 614 dt->_parent = pdt; 615 #define PCOPY(x) dt->x = pdt->x 616 PCOPY(_dmamap_create); 617 PCOPY(_dmamap_destroy); 618 dt->_dmamap_load = iommu_dvmamap_load; 619 PCOPY(_dmamap_load_mbuf); 620 PCOPY(_dmamap_load_uio); 621 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 622 dt->_dmamap_unload = iommu_dvmamap_unload; 623 dt->_dmamap_sync = iommu_dvmamap_sync; 624 dt->_dmamem_alloc = iommu_dvmamem_alloc; 625 dt->_dmamem_free = iommu_dvmamem_free; 626 dt->_dmamem_map = iommu_dvmamem_map; 627 dt->_dmamem_unmap = iommu_dvmamem_unmap; 628 PCOPY(_dmamem_mmap); 629 #undef PCOPY 630 return (dt); 631 } 632 633 pci_chipset_tag_t 634 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 635 { 636 pci_chipset_tag_t npc; 637 638 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 639 if (npc == NULL) 640 panic("schizo: could not allocate pci_chipset_tag_t"); 641 memcpy(npc, pc, sizeof *pc); 642 npc->cookie = pbm; 643 npc->rootnode = node; 644 npc->spc_conf_read = schizo_conf_read; 645 npc->spc_conf_write = schizo_conf_write; 646 npc->spc_intr_establish = schizo_pci_intr_establish; 647 npc->spc_find_ino = schizo_pci_find_ino; 648 return (npc); 649 } 650 651 #if 0 652 int 653 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 654 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 655 bus_dmamap_t *dmamp) 656 { 657 struct schizo_pbm *pbm = t->_cookie; 658 659 return (iommu_dvmamap_create(t, &pbm->sp_sb, size, nsegments, 660 maxsegsz, boundary, flags, dmamp)); 661 } 662 #endif 663 664 static struct schizo_range * 665 get_schizorange(struct schizo_pbm *pbm, int ss) 666 { 667 int i; 668 669 for (i = 0; i < pbm->sp_nrange; i++) { 670 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 671 return (&pbm->sp_range[i]); 672 } 673 /* not found */ 674 return (NULL); 675 } 676 677 int 678 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 679 int flags, vaddr_t unused, bus_space_handle_t *hp) 680 { 681 bus_addr_t paddr; 682 struct schizo_pbm *pbm = t->cookie; 683 struct schizo_softc *sc = pbm->sp_sc; 684 struct schizo_range *sr; 685 int ss; 686 687 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 688 t->type, 689 (unsigned long long)offset, 690 (unsigned long long)size, 691 flags)); 692 693 ss = sparc_pci_childspace(t->type); 694 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 695 696 sr = get_schizorange(pbm, ss); 697 if (sr != NULL) { 698 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 699 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 700 "space %lx offset %lx paddr %qx\n", 701 __func__, (long)ss, (long)offset, 702 (unsigned long long)paddr)); 703 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 704 flags, 0, hp)); 705 } 706 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 707 return (EINVAL); 708 } 709 710 static paddr_t 711 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 712 int flags) 713 { 714 bus_addr_t offset = paddr; 715 struct schizo_pbm *pbm = t->cookie; 716 struct schizo_softc *sc = pbm->sp_sc; 717 struct schizo_range *sr; 718 int ss; 719 720 ss = sparc_pci_childspace(t->type); 721 722 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 723 prot, flags, (unsigned long long)paddr)); 724 725 sr = get_schizorange(pbm, ss); 726 if (sr != NULL) { 727 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 728 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 729 "space %lx offset %lx paddr %qx\n", 730 __func__, (long)ss, (long)offset, 731 (unsigned long long)paddr)); 732 return (bus_space_mmap(sc->sc_bustag, paddr, off, 733 prot, flags)); 734 } 735 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 736 return (-1); 737 } 738 739 static void * 740 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 741 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 742 { 743 struct schizo_pbm *pbm = t->cookie; 744 struct intrhand *ih = NULL; 745 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 746 int ino; 747 long vec = INTVEC(ihandle); 748 749 vec = INTVEC(ihandle); 750 ino = INTINO(vec); 751 752 DPRINTF(SDB_INTR, ("%s: ihandle %d level %d fn %p arg %p\n", __func__, 753 ihandle, level, handler, arg)); 754 755 if (level == IPL_NONE) 756 level = INTLEV(vec); 757 if (level == IPL_NONE) { 758 printf(": no IPL, setting IPL 2.\n"); 759 level = 2; 760 } 761 762 #if 0 763 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 764 struct schizo_pbm_regs *pbmreg; 765 766 pbmreg = bus_space_vaddr(pbm->sp_regt, pbm->sp_regh); 767 intrmapptr = &pbmreg->imap[ino]; 768 intrclrptr = &pbmreg->iclr[ino]; 769 if (INTIGN(vec) == 0) 770 ino |= (*intrmapptr) & INTMAP_IGN; 771 else 772 ino |= vec & INTMAP_IGN; 773 } 774 775 ih = bus_intr_allocate(t, handler, arg, ino, level, intrmapptr, 776 intrclrptr, what); 777 #endif 778 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 779 if (ih == NULL) 780 return (NULL); 781 782 ih->ih_map = intrmapptr; 783 ih->ih_clr = intrclrptr; 784 785 ih->ih_fun = handler; 786 ih->ih_arg = arg; 787 ih->ih_pil = level; 788 ih->ih_number = ino | pbm->sp_sc->sc_ign; 789 790 intr_establish(ih->ih_pil, level != IPL_VM, ih); 791 792 if (intrmapptr != NULL) { 793 u_int64_t imap; 794 795 imap = *intrmapptr; 796 imap |= INTMAP_V; 797 *intrmapptr = imap; 798 imap = *intrmapptr; 799 ih->ih_number |= imap & INTMAP_INR; 800 } 801 802 return (ih); 803 } 804 805 static void * 806 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 807 int (*func)(void *), void *arg) 808 { 809 void *cookie; 810 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 811 812 DPRINTF(SDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 813 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 814 815 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 816 return (cookie); 817 } 818 819 static int 820 schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 821 { 822 #if 0 823 struct schizo_pbm *pbm = pa->pa_pc->cookie; 824 struct schizo_softc *sc = pbm->sp_sc; 825 u_int bus; 826 u_int dev; 827 u_int pin; 828 #endif 829 830 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 831 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 832 (int)PCITAG_DEV(pa->pa_tag), 833 (int)PCITAG_FUN(pa->pa_tag))); 834 DPRINTF(SDB_INTMAP, 835 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 836 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 837 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 838 PCITAG_NODE(pa->pa_intrtag), 839 (int)PCITAG_BUS(pa->pa_intrtag), 840 (int)PCITAG_DEV(pa->pa_intrtag), 841 (int)PCITAG_FUN(pa->pa_intrtag))); 842 843 #if 0 844 bus = (pp->pp_id == PSYCHO_PBM_B); 845 /* 846 * If we are on a ppb, use the devno on the underlying bus when forming 847 * the ivec. 848 */ 849 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 850 dev = PCITAG_DEV(pa->pa_intrtag); 851 else 852 dev = pa->pa_device; 853 dev--; 854 855 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 856 pp->pp_id == PSYCHO_PBM_B) 857 dev--; 858 859 pin = pa->pa_intrpin - 1; 860 DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 861 sc->sc_mode, pp->pp_id, dev, pin)); 862 863 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 864 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 865 #endif 866 867 return (0); 868 } 869
Indexes created Tue Sep 30 20:09:53 GMT 2025