schizo.c revision 1.33
1 /* $NetBSD: schizo.c,v 1.33 2015/10/02 05:22:52 msaitoh Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010, 2012 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.33 2015/10/02 05:22:52 msaitoh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/kmem.h> 40 #include <sys/malloc.h> 41 #include <sys/systm.h> 42 #include <sys/time.h> 43 #include <sys/reboot.h> 44 45 #define _SPARC_BUS_DMA_PRIVATE 46 #include <sys/bus.h> 47 #include <machine/autoconf.h> 48 #include <machine/psl.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/dev/iommuvar.h> 55 #include <sparc64/dev/schizoreg.h> 56 #include <sparc64/dev/schizovar.h> 57 #include <sparc64/sparc64/cache.h> 58 59 #ifdef DEBUG 60 #define SDB_PROM 0x01 61 #define SDB_BUSMAP 0x02 62 #define SDB_INTR 0x04 63 #define SDB_INTMAP 0x08 64 #define SDB_CONF 0x10 65 int schizo_debug = 0x0; 66 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 67 #else 68 #define DPRINTF(l, s) 69 #endif 70 71 extern struct sparc_pci_chipset _sparc_pci_chipset; 72 73 static int schizo_match(device_t, cfdata_t, void *); 74 static void schizo_attach(device_t, device_t, void *); 75 static int schizo_print(void *aux, const char *p); 76 77 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc), 78 schizo_match, schizo_attach, NULL, NULL); 79 80 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 81 82 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 83 int (*handler)(void *), void *, int, const char *); 84 int schizo_ue(void *); 85 int schizo_ce(void *); 86 int schizo_safari_error(void *); 87 int schizo_pci_error(void *); 88 89 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 90 pci_chipset_tag_t); 91 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 92 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 93 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 94 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 95 int); 96 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 97 98 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 99 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 100 101 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 102 int flags, vaddr_t unused, bus_space_handle_t *hp); 103 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 104 off_t off, int prot, int flags); 105 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 106 void *, void(*)(void)); 107 static int schizo_pci_intr_map(const struct pci_attach_args *, 108 pci_intr_handle_t *); 109 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 110 int, int (*)(void *), void *); 111 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 112 bus_size_t, int, bus_dmamap_t *); 113 114 int 115 schizo_match(device_t parent, cfdata_t match, void *aux) 116 { 117 struct mainbus_attach_args *ma = aux; 118 char *str; 119 120 if (strcmp(ma->ma_name, "pci") != 0) 121 return (0); 122 123 str = prom_getpropstring(ma->ma_node, "model"); 124 if (strcmp(str, "schizo") == 0) 125 return (1); 126 127 str = prom_getpropstring(ma->ma_node, "compatible"); 128 if (strcmp(str, "pci108e,8001") == 0) 129 return (1); 130 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 131 return (1); 132 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 133 return (1); 134 135 return (0); 136 } 137 138 void 139 schizo_attach(device_t parent, device_t self, void *aux) 140 { 141 struct schizo_softc *sc = device_private(self); 142 struct mainbus_attach_args *ma = aux; 143 struct schizo_pbm *pbm; 144 struct iommu_state *is; 145 struct pcibus_attach_args pba; 146 uint64_t reg, eccctrl; 147 int *busranges = NULL, nranges; 148 char *str; 149 bool no_sc; 150 151 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 152 str = prom_getpropstring(ma->ma_node, "compatible"); 153 if (strcmp(str, "pci108e,a801") == 0) 154 sc->sc_tomatillo = 1; 155 156 sc->sc_ver = prom_getpropint(sc->sc_node, "version#", 0); 157 158 sc->sc_dev = self; 159 sc->sc_node = ma->ma_node; 160 sc->sc_dmat = ma->ma_dmatag; 161 sc->sc_bustag = ma->ma_bustag; 162 163 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 164 sizeof(struct schizo_regs), 0, 165 &sc->sc_ctrlh)) { 166 aprint_error(": failed to map registers\n"); 167 return; 168 } 169 170 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 171 172 /* enable schizo ecc error interrupts */ 173 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 174 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 175 SCZ_ECCCTRL_UE_INTEN | 176 SCZ_ECCCTRL_CE_INTEN; 177 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 178 179 pbm = kmem_zalloc(sizeof(*pbm), KM_NOSLEEP); 180 if (pbm == NULL) 181 panic("schizo: can't alloc schizo pbm"); 182 183 pbm->sp_sc = sc; 184 pbm->sp_regt = sc->sc_bustag; 185 186 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 187 pbm->sp_bus_a = 1; 188 else 189 pbm->sp_bus_a = 0; 190 191 /* 192 * Map interrupt registers 193 */ 194 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 195 ma->ma_reg[0].ur_len, 196 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 197 aprint_error(": failed to interrupt map registers\n"); 198 kmem_free(pbm, sizeof(*pbm)); 199 return; 200 } 201 202 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 203 &pbm->sp_nrange, (void **)&pbm->sp_range)) 204 panic("schizo: can't get ranges"); 205 206 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 207 (void **)&busranges)) 208 panic("schizo: can't get bus-range"); 209 210 aprint_normal(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 211 sc->sc_tomatillo ? "Tomatillo" : "Schizo", sc->sc_ver, 212 sc->sc_ign, pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 213 aprint_naive("\n"); 214 215 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 216 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 217 offsetof(struct schizo_regs, pbm_b), 218 sizeof(struct schizo_pbm_regs), 219 &pbm->sp_regh)) { 220 panic("schizo: unable to create PBM handle"); 221 } 222 223 is = &pbm->sp_is; 224 pbm->sp_sb.sb_is = is; 225 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 226 if (no_sc) 227 aprint_debug_dev(sc->sc_dev, "no streaming buffers\n"); 228 else { 229 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 230 231 /* 232 * Initialize the strbuf_ctl. 233 * 234 * The flush sync buffer must be 64-byte aligned. 235 */ 236 is->is_sb[0] = &pbm->sp_sb; 237 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 238 239 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 240 offsetof(struct schizo_pbm_regs, strbuf), 241 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 242 } 243 244 aprint_normal_dev(sc->sc_dev, " "); 245 schizo_init_iommu(sc, pbm); 246 247 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 248 pbm->sp_iot = schizo_alloc_io_tag(pbm); 249 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 250 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 251 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 252 (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0); 253 254 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 255 panic("schizo: could not map config space"); 256 257 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 258 &_sparc_pci_chipset); 259 pbm->sp_pc->spc_busmax = busranges[1]; 260 pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode), 261 KM_NOSLEEP); 262 if (pbm->sp_pc->spc_busnode == NULL) 263 panic("schizo: kmem_alloc busnode"); 264 265 pba.pba_bus = busranges[0]; 266 pba.pba_bridgetag = NULL; 267 pba.pba_pc = pbm->sp_pc; 268 pba.pba_flags = pbm->sp_flags; 269 pba.pba_dmat = pbm->sp_dmat; 270 pba.pba_dmat64 = NULL; /* XXX */ 271 pba.pba_memt = pbm->sp_memt; 272 pba.pba_iot = pbm->sp_iot; 273 274 free(busranges, M_DEVBUF); 275 276 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 277 278 /* clear out the bus errors */ 279 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 280 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 281 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 282 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 283 284 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 285 /* enable/disable error interrupts and arbiter */ 286 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT; 287 if (sc->sc_tomatillo) { 288 reg &= ~SCZ_PCICTRL_SBH_INT; 289 reg |= TOM_PCICTRL_ARB; 290 reg |= TOM_PCICTRL_PRM | TOM_PCICTRL_PRO | 291 TOM_PCICTRL_PRL; 292 if (sc->sc_ver <= 1) /* 2.0 */ 293 reg |= TOM_PCICTRL_DTO_INT; 294 else 295 reg |= SCZ_PCICTRL_PTO; 296 } else 297 reg |= SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_ARB; 298 if (OF_getproplen(sc->sc_node, "no-bus-parking") < 0) 299 reg |= SCZ_PCICTRL_PARK; 300 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 301 302 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 303 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 304 SCZ_PCIDIAG_D_INTSYNC); 305 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 306 307 if (pbm->sp_bus_a) 308 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 309 pbm, SCZ_PCIERR_A_INO, "pci_a"); 310 else 311 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 312 pbm, SCZ_PCIERR_B_INO, "pci_b"); 313 314 /* double mapped */ 315 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 316 "ue"); 317 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 318 "ce"); 319 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 320 SCZ_SERR_INO, "safari"); 321 322 if (sc->sc_tomatillo) { 323 /* 324 * Enable the IOCACHE. 325 */ 326 uint64_t iocache_csr; 327 328 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 329 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 330 TOM_IOCACHE_CSR_PEN_RDM | 331 TOM_IOCACHE_CSR_PEN_ONE | 332 TOM_IOCACHE_CSR_PEN_LINE; 333 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 334 } 335 336 config_found(sc->sc_dev, &pba, schizo_print); 337 } 338 339 int 340 schizo_ue(void *vsc) 341 { 342 struct schizo_softc *sc = vsc; 343 344 panic("%s: uncorrectable error", device_xname(sc->sc_dev)); 345 return (1); 346 } 347 348 int 349 schizo_ce(void *vsc) 350 { 351 struct schizo_softc *sc = vsc; 352 353 panic("%s: correctable error", device_xname(sc->sc_dev)); 354 return (1); 355 } 356 357 int 358 schizo_pci_error(void *vpbm) 359 { 360 struct schizo_pbm *sp = vpbm; 361 struct schizo_softc *sc = sp->sp_sc; 362 u_int64_t afsr, afar, ctrl, tfar; 363 u_int32_t csr; 364 char bits[128]; 365 366 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 367 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 368 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 369 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 370 371 printf("%s: pci bus %c error\n", device_xname(sc->sc_dev), 372 sp->sp_bus_a ? 'A' : 'B'); 373 374 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 375 printf("PCIAFSR=%s\n", bits); 376 printf("PCIAFAR=%" PRIx64 "\n", afar); 377 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 378 printf("PCICTRL=%s\n", bits); 379 #ifdef PCI_COMMAND_STATUS_BITS 380 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 381 printf("PCICSR=%s\n", bits); 382 #endif 383 384 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 385 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 386 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 387 388 if ((ctrl & TOM_IOMMU_ERR) == 0) 389 goto clear_error; 390 391 if (sc->sc_tomatillo) { 392 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 393 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 394 } 395 396 /* These are non-fatal if target abort was signalled. */ 397 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 398 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 399 ctrl & TOM_IOMMU_BADVA_ERR) { 400 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 401 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 402 goto clear_error; 403 } 404 } 405 } 406 407 panic("%s: fatal", device_xname(sc->sc_dev)); 408 409 clear_error: 410 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 411 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 412 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 413 return (1); 414 } 415 416 int 417 schizo_safari_error(void *vsc) 418 { 419 struct schizo_softc *sc = vsc; 420 421 printf("%s: safari error\n", device_xname(sc->sc_dev)); 422 423 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 424 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 425 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 426 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 427 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 428 429 panic("%s: fatal", device_xname(sc->sc_dev)); 430 return (1); 431 } 432 433 void 434 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 435 { 436 struct iommu_state *is = &pbm->sp_is; 437 int *vdma = NULL, nitem, tsbsize = 7; 438 u_int32_t iobase = -1; 439 char *name; 440 441 /* punch in our copies */ 442 is->is_bustag = pbm->sp_regt; 443 bus_space_subregion(is->is_bustag, pbm->sp_regh, 444 offsetof(struct schizo_pbm_regs, iommu), 445 sizeof(struct iommureg2), 446 &is->is_iommu); 447 448 /* 449 * Separate the men from the boys. If the `virtual-dma' 450 * property exists, use it. 451 */ 452 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 453 (void **)&vdma)) { 454 /* Damn. Gotta use these values. */ 455 iobase = vdma[0]; 456 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 457 switch (vdma[1]) { 458 TSBCASE(1); TSBCASE(2); TSBCASE(3); 459 TSBCASE(4); TSBCASE(5); TSBCASE(6); 460 default: 461 printf("bogus tsb size %x, using 7\n", vdma[1]); 462 TSBCASE(7); 463 } 464 #undef TSBCASE 465 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 466 free(vdma, M_DEVBUF); 467 } else { 468 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 469 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 470 } 471 472 /* give us a nice name.. */ 473 name = (char *)kmem_alloc(32, KM_NOSLEEP); 474 if (name == NULL) 475 476 panic("couldn't kmem_alloc iommu name"); 477 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 478 479 iommu_init(name, is, tsbsize, iobase); 480 } 481 482 int 483 schizo_print(void *aux, const char *p) 484 { 485 486 if (p == NULL) 487 return (UNCONF); 488 return (QUIET); 489 } 490 491 pcireg_t 492 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 493 { 494 struct schizo_pbm *sp = pc->cookie; 495 struct cpu_info *ci = curcpu(); 496 pcireg_t val = (pcireg_t)~0; 497 int s; 498 499 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 500 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 501 s = splhigh(); 502 ci->ci_pci_probe = true; 503 membar_Sync(); 504 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 505 PCITAG_OFFSET(tag) + reg); 506 membar_Sync(); 507 if (ci->ci_pci_fault) 508 val = (pcireg_t)~0; 509 ci->ci_pci_probe = ci->ci_pci_fault = false; 510 splx(s); 511 } 512 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 513 return (val); 514 } 515 516 void 517 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 518 { 519 struct schizo_pbm *sp = pc->cookie; 520 521 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 522 (long)tag, reg, (int)data)); 523 524 /* If we don't know it, just punt it. */ 525 if (PCITAG_NODE(tag) == -1) { 526 DPRINTF(SDB_CONF, (" .. bad addr\n")); 527 return; 528 } 529 530 if ((unsigned int)reg >= PCI_CONF_SIZE) 531 return; 532 533 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 534 PCITAG_OFFSET(tag) + reg, data); 535 DPRINTF(SDB_CONF, (" .. done\n")); 536 } 537 538 void 539 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 540 int (*handler)(void *), void *arg, int ino, const char *what) 541 { 542 struct intrhand *ih; 543 u_int64_t mapoff, clroff; 544 uintptr_t intrregs; 545 546 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 547 ino, sc->sc_ign, handler, arg)); 548 549 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 550 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 551 ino |= sc->sc_ign; 552 553 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 554 mapoff, clroff)); 555 556 ih = (struct intrhand *) 557 kmem_alloc(sizeof(struct intrhand), KM_NOSLEEP); 558 if (ih == NULL) 559 return; 560 ih->ih_arg = arg; 561 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 562 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 563 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 564 ih->ih_fun = handler; 565 ih->ih_pil = ipl; 566 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 567 ih->ih_pending = 0; 568 569 intr_establish(ipl, ipl != IPL_VM, ih); 570 571 schizo_pbm_write(pbm, mapoff, 572 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 573 } 574 575 bus_space_tag_t 576 schizo_alloc_mem_tag(struct schizo_pbm *sp) 577 { 578 return (schizo_alloc_bus_tag(sp, "mem", PCI_MEMORY_BUS_SPACE)); 579 } 580 581 bus_space_tag_t 582 schizo_alloc_io_tag(struct schizo_pbm *sp) 583 { 584 return (schizo_alloc_bus_tag(sp, "io", PCI_IO_BUS_SPACE)); 585 } 586 587 bus_space_tag_t 588 schizo_alloc_config_tag(struct schizo_pbm *sp) 589 { 590 return (schizo_alloc_bus_tag(sp, "cfg", PCI_CONFIG_BUS_SPACE)); 591 } 592 593 bus_space_tag_t 594 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 595 { 596 struct schizo_softc *sc = pbm->sp_sc; 597 bus_space_tag_t bt; 598 599 bt = (bus_space_tag_t) kmem_zalloc(sizeof(struct sparc_bus_space_tag), 600 KM_NOSLEEP); 601 if (bt == NULL) 602 panic("schizo: could not allocate bus tag"); 603 604 bt->cookie = pbm; 605 bt->parent = sc->sc_bustag; 606 bt->type = type; 607 bt->sparc_bus_map = schizo_bus_map; 608 bt->sparc_bus_mmap = schizo_bus_mmap; 609 bt->sparc_intr_establish = schizo_intr_establish; 610 return (bt); 611 } 612 613 bus_dma_tag_t 614 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 615 { 616 struct schizo_softc *sc = pbm->sp_sc; 617 bus_dma_tag_t dt, pdt = sc->sc_dmat; 618 619 dt = kmem_zalloc(sizeof(*dt), KM_NOSLEEP); 620 if (dt == NULL) 621 panic("schizo: could not alloc dma tag"); 622 623 dt->_cookie = pbm; 624 dt->_parent = pdt; 625 #define PCOPY(x) dt->x = pdt->x 626 dt->_dmamap_create = schizo_dmamap_create; 627 PCOPY(_dmamap_destroy); 628 dt->_dmamap_load = iommu_dvmamap_load; 629 PCOPY(_dmamap_load_mbuf); 630 PCOPY(_dmamap_load_uio); 631 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 632 dt->_dmamap_unload = iommu_dvmamap_unload; 633 dt->_dmamap_sync = iommu_dvmamap_sync; 634 dt->_dmamem_alloc = iommu_dvmamem_alloc; 635 dt->_dmamem_free = iommu_dvmamem_free; 636 dt->_dmamem_map = iommu_dvmamem_map; 637 dt->_dmamem_unmap = iommu_dvmamem_unmap; 638 PCOPY(_dmamem_mmap); 639 #undef PCOPY 640 return (dt); 641 } 642 643 pci_chipset_tag_t 644 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 645 { 646 pci_chipset_tag_t npc; 647 648 npc = kmem_alloc(sizeof *npc, KM_NOSLEEP); 649 if (npc == NULL) 650 panic("schizo: could not allocate pci_chipset_tag_t"); 651 memcpy(npc, pc, sizeof *pc); 652 npc->cookie = pbm; 653 npc->rootnode = node; 654 npc->spc_conf_read = schizo_conf_read; 655 npc->spc_conf_write = schizo_conf_write; 656 npc->spc_intr_map = schizo_pci_intr_map; 657 npc->spc_intr_establish = schizo_pci_intr_establish; 658 npc->spc_find_ino = NULL; 659 return (npc); 660 } 661 662 int 663 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 664 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 665 bus_dmamap_t *dmamp) 666 { 667 struct schizo_pbm *pbm = t->_cookie; 668 int error; 669 670 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 671 boundary, flags, dmamp); 672 if (error == 0) 673 (*dmamp)->_dm_cookie = &pbm->sp_sb; 674 return error; 675 } 676 677 static struct schizo_range * 678 get_schizorange(struct schizo_pbm *pbm, int ss) 679 { 680 int i; 681 682 for (i = 0; i < pbm->sp_nrange; i++) { 683 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 684 return (&pbm->sp_range[i]); 685 } 686 /* not found */ 687 return (NULL); 688 } 689 690 int 691 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 692 int flags, vaddr_t unused, bus_space_handle_t *hp) 693 { 694 bus_addr_t paddr; 695 struct schizo_pbm *pbm = t->cookie; 696 struct schizo_softc *sc = pbm->sp_sc; 697 struct schizo_range *sr; 698 int ss; 699 700 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 701 t->type, 702 (unsigned long long)offset, 703 (unsigned long long)size, 704 flags)); 705 706 ss = sparc_pci_childspace(t->type); 707 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 708 709 sr = get_schizorange(pbm, ss); 710 if (sr != NULL) { 711 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 712 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 713 "space %lx offset %lx paddr %qx\n", 714 __func__, (long)ss, (long)offset, 715 (unsigned long long)paddr)); 716 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 717 flags, 0, hp)); 718 } 719 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 720 return (EINVAL); 721 } 722 723 static paddr_t 724 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 725 int flags) 726 { 727 bus_addr_t offset = paddr; 728 struct schizo_pbm *pbm = t->cookie; 729 struct schizo_softc *sc = pbm->sp_sc; 730 struct schizo_range *sr; 731 int ss; 732 733 ss = sparc_pci_childspace(t->type); 734 735 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 736 prot, flags, (unsigned long long)paddr)); 737 738 sr = get_schizorange(pbm, ss); 739 if (sr != NULL) { 740 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 741 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 742 "space %lx offset %lx paddr %qx\n", 743 __func__, (long)ss, (long)offset, 744 (unsigned long long)paddr)); 745 return (bus_space_mmap(sc->sc_bustag, paddr, off, 746 prot, flags)); 747 } 748 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 749 return (-1); 750 } 751 752 /* 753 * Set the IGN for this schizo into the handle. 754 */ 755 int 756 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 757 { 758 struct schizo_pbm *pbm = pa->pa_pc->cookie; 759 struct schizo_softc *sc = pbm->sp_sc; 760 761 *ihp |= sc->sc_ign; 762 DPRINTF(SDB_INTMAP, ("returning IGN adjusted to %x\n", *ihp)); 763 return (0); 764 } 765 766 static void * 767 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 768 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 769 { 770 struct schizo_pbm *pbm = t->cookie; 771 struct intrhand *ih = NULL; 772 uint64_t mapoff, clroff; 773 uintptr_t intrregs; 774 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 775 int ino; 776 long vec; 777 778 vec = INTVEC(ihandle); 779 ino = INTINO(vec); 780 781 ih = kmem_alloc(sizeof *ih, KM_NOSLEEP); 782 if (ih == NULL) 783 return (NULL); 784 785 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 786 ihandle, level, handler, arg)); 787 788 if (level == IPL_NONE) 789 level = INTLEV(vec); 790 if (level == IPL_NONE) { 791 printf(": no IPL, setting IPL 2.\n"); 792 level = 2; 793 } 794 795 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 796 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 797 798 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 799 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 800 801 ih->ih_ivec = ihandle; 802 803 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 804 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 805 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 806 807 if (INTIGN(vec) == 0) 808 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 809 else 810 ino |= vec & INTMAP_IGN; 811 812 /* Register the map and clear intr registers */ 813 ih->ih_map = intrmapptr; 814 ih->ih_clr = intrclrptr; 815 816 ih->ih_fun = handler; 817 ih->ih_arg = arg; 818 ih->ih_pil = level; 819 ih->ih_number = ino; 820 ih->ih_pending = 0; 821 822 DPRINTF(SDB_INTR, ( 823 "; installing handler %p arg %p with inr %x pil %u\n", 824 handler, arg, ino, (u_int)ih->ih_pil)); 825 826 intr_establish(ih->ih_pil, level != IPL_VM, ih); 827 828 /* 829 * Enable the interrupt now we have the handler installed. 830 * Read the current value as we can't change it besides the 831 * valid bit so so make sure only this bit is changed. 832 */ 833 if (intrmapptr) { 834 u_int64_t imap; 835 836 imap = schizo_pbm_readintr(pbm, mapoff); 837 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 838 (unsigned long long)imap)); 839 imap |= INTMAP_V; 840 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 841 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 842 (unsigned long long)imap)); 843 schizo_pbm_writeintr(pbm, mapoff, imap); 844 imap = schizo_pbm_readintr(pbm, mapoff); 845 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 846 (unsigned long long)imap)); 847 ih->ih_number |= imap & INTMAP_INR; 848 } 849 if (intrclrptr) { 850 /* set state to IDLE */ 851 schizo_pbm_writeintr(pbm, clroff, 0); 852 } 853 854 return (ih); 855 } 856 857 static void * 858 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 859 int (*func)(void *), void *arg) 860 { 861 void *cookie; 862 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 863 864 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 865 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 866 867 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 868 return (cookie); 869 } 870
Indexes created Tue Sep 30 20:09:53 GMT 2025