schizo.c revision 1.36
1 /* $NetBSD: schizo.c,v 1.36 2016/05/10 19:23:59 palle Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010, 2012 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.36 2016/05/10 19:23:59 palle Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/kmem.h> 40 #include <sys/malloc.h> 41 #include <sys/systm.h> 42 #include <sys/time.h> 43 #include <sys/reboot.h> 44 45 #define _SPARC_BUS_DMA_PRIVATE 46 #include <sys/bus.h> 47 #include <machine/autoconf.h> 48 #include <machine/psl.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/dev/iommuvar.h> 55 #include <sparc64/dev/schizoreg.h> 56 #include <sparc64/dev/schizovar.h> 57 #include <sparc64/sparc64/cache.h> 58 59 #ifdef DEBUG 60 #define SDB_PROM 0x01 61 #define SDB_BUSMAP 0x02 62 #define SDB_INTR 0x04 63 #define SDB_INTMAP 0x08 64 #define SDB_CONF 0x10 65 int schizo_debug = 0x0; 66 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 67 #else 68 #define DPRINTF(l, s) 69 #endif 70 71 extern struct sparc_pci_chipset _sparc_pci_chipset; 72 73 static int schizo_match(device_t, cfdata_t, void *); 74 static void schizo_attach(device_t, device_t, void *); 75 static int schizo_print(void *aux, const char *p); 76 77 #ifdef DEBUG 78 void schizo_print_regs(int unit, int what); 79 #endif 80 81 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc), 82 schizo_match, schizo_attach, NULL, NULL); 83 84 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 85 86 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 87 int (*handler)(void *), void *, int, const char *); 88 int schizo_ue(void *); 89 int schizo_ce(void *); 90 int schizo_safari_error(void *); 91 int schizo_pci_error(void *); 92 93 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 94 pci_chipset_tag_t); 95 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 96 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 97 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 98 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 99 int); 100 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 101 102 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 103 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 104 105 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 106 int flags, vaddr_t unused, bus_space_handle_t *hp); 107 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 108 off_t off, int prot, int flags); 109 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 110 void *, void(*)(void)); 111 static int schizo_pci_intr_map(const struct pci_attach_args *, 112 pci_intr_handle_t *); 113 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 114 int, int (*)(void *), void *); 115 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 116 bus_size_t, int, bus_dmamap_t *); 117 118 int 119 schizo_match(device_t parent, cfdata_t match, void *aux) 120 { 121 struct mainbus_attach_args *ma = aux; 122 char *str; 123 124 if (strcmp(ma->ma_name, "pci") != 0) 125 return (0); 126 127 str = prom_getpropstring(ma->ma_node, "model"); 128 if (strcmp(str, "schizo") == 0) 129 return (1); 130 131 str = prom_getpropstring(ma->ma_node, "compatible"); 132 if (strcmp(str, "pci108e,8001") == 0) 133 return (1); 134 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 135 return (1); 136 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 137 return (1); 138 139 return (0); 140 } 141 142 void 143 schizo_attach(device_t parent, device_t self, void *aux) 144 { 145 struct schizo_softc *sc = device_private(self); 146 struct mainbus_attach_args *ma = aux; 147 struct schizo_pbm *pbm; 148 struct iommu_state *is; 149 struct pcibus_attach_args pba; 150 uint64_t reg, eccctrl, ino_bitmap; 151 int *busranges = NULL, nranges, *ino_bitmaps = NULL, nbitmaps; 152 char *str; 153 bool no_sc; 154 155 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 156 str = prom_getpropstring(ma->ma_node, "compatible"); 157 if (strcmp(str, "pci108e,a801") == 0) 158 sc->sc_tomatillo = 1; 159 160 sc->sc_ver = prom_getpropint(sc->sc_node, "version#", 0); 161 162 sc->sc_dev = self; 163 sc->sc_node = ma->ma_node; 164 sc->sc_dmat = ma->ma_dmatag; 165 sc->sc_bustag = ma->ma_bustag; 166 167 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 168 sizeof(struct schizo_regs), 0, 169 &sc->sc_ctrlh)) { 170 aprint_error(": failed to map registers\n"); 171 return; 172 } 173 174 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 175 176 /* enable schizo ecc error interrupts */ 177 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 178 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 179 SCZ_ECCCTRL_UE_INTEN | 180 SCZ_ECCCTRL_CE_INTEN; 181 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 182 183 pbm = kmem_zalloc(sizeof(*pbm), KM_NOSLEEP); 184 if (pbm == NULL) 185 panic("schizo: can't alloc schizo pbm"); 186 187 #ifdef DEBUG 188 sc->sc_pbm = pbm; 189 #endif 190 pbm->sp_sc = sc; 191 pbm->sp_regt = sc->sc_bustag; 192 193 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 194 pbm->sp_bus_a = 1; 195 else 196 pbm->sp_bus_a = 0; 197 198 /* 199 * Map interrupt registers 200 */ 201 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 202 ma->ma_reg[0].ur_len, 203 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 204 aprint_error(": failed to map interrupt registers\n"); 205 kmem_free(pbm, sizeof(*pbm)); 206 return; 207 } 208 209 #ifdef DEBUG 210 /* 211 * Map ichip registers 212 */ 213 if (sc->sc_tomatillo) 214 if (bus_space_map(sc->sc_bustag, ma->ma_reg[3].ur_paddr, 215 ma->ma_reg[3].ur_len, 216 BUS_SPACE_MAP_LINEAR, &pbm->sp_ichiph)) { 217 aprint_error(": failed to map ichip registers\n"); 218 kmem_free(pbm, sizeof(*pbm)); 219 return; 220 } 221 #endif 222 223 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 224 &pbm->sp_nrange, (void **)&pbm->sp_range)) 225 panic("schizo: can't get ranges"); 226 227 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 228 (void **)&busranges)) 229 panic("schizo: can't get bus-range"); 230 231 aprint_normal(": %s, version %d, ign %x, bus %c %d to %d\n", 232 sc->sc_tomatillo ? "Tomatillo" : "Schizo", sc->sc_ver, 233 sc->sc_ign, pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 234 aprint_naive("\n"); 235 236 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 237 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 238 offsetof(struct schizo_regs, pbm_b), 239 sizeof(struct schizo_pbm_regs), 240 &pbm->sp_regh)) { 241 panic("schizo: unable to create PBM handle"); 242 } 243 244 is = &pbm->sp_is; 245 pbm->sp_sb.sb_is = is; 246 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 247 if (no_sc) 248 aprint_debug_dev(sc->sc_dev, "no streaming buffers\n"); 249 else { 250 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 251 252 /* 253 * Initialize the strbuf_ctl. 254 * 255 * The flush sync buffer must be 64-byte aligned. 256 */ 257 is->is_sb[0] = &pbm->sp_sb; 258 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 259 260 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 261 offsetof(struct schizo_pbm_regs, strbuf), 262 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 263 } 264 265 aprint_normal_dev(sc->sc_dev, " "); 266 schizo_init_iommu(sc, pbm); 267 268 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 269 pbm->sp_iot = schizo_alloc_io_tag(pbm); 270 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 271 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 272 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 273 (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0); 274 275 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 276 panic("schizo: could not map config space"); 277 278 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 279 &_sparc_pci_chipset); 280 pbm->sp_pc->spc_busmax = busranges[1]; 281 pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode), 282 KM_NOSLEEP); 283 if (pbm->sp_pc->spc_busnode == NULL) 284 panic("schizo: kmem_alloc busnode"); 285 286 pba.pba_bus = busranges[0]; 287 pba.pba_bridgetag = NULL; 288 pba.pba_pc = pbm->sp_pc; 289 pba.pba_flags = pbm->sp_flags; 290 pba.pba_dmat = pbm->sp_dmat; 291 pba.pba_dmat64 = NULL; /* XXX */ 292 pba.pba_memt = pbm->sp_memt; 293 pba.pba_iot = pbm->sp_iot; 294 295 free(busranges, M_DEVBUF); 296 297 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 298 299 /* clear out the bus errors */ 300 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 301 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 302 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 303 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 304 305 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 306 /* enable/disable error interrupts and arbiter */ 307 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT; 308 if (sc->sc_tomatillo) { 309 reg &= ~SCZ_PCICTRL_SBH_INT; 310 reg |= TOM_PCICTRL_ARB; 311 reg |= TOM_PCICTRL_PRM | TOM_PCICTRL_PRO | 312 TOM_PCICTRL_PRL; 313 if (sc->sc_ver <= 1) /* 2.0 */ 314 reg |= TOM_PCICTRL_DTO_INT; 315 else 316 reg |= SCZ_PCICTRL_PTO; 317 } else 318 reg |= SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_ARB; 319 if (OF_getproplen(sc->sc_node, "no-bus-parking") < 0) 320 reg |= SCZ_PCICTRL_PARK; 321 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 322 323 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 324 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 325 SCZ_PCIDIAG_D_INTSYNC); 326 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 327 328 if (prom_getprop(sc->sc_node, "ino-bitmap", sizeof(int), &nbitmaps, 329 (void **)&ino_bitmaps)) { 330 /* No property - set defaults (double map UE, CE, SERR). */ 331 if (pbm->sp_bus_a) 332 ino_bitmap = __BIT(SCZ_PCIERR_A_INO); 333 else 334 ino_bitmap = __BIT(SCZ_PCIERR_B_INO); 335 ino_bitmap |= __BIT(SCZ_UE_INO) | __BIT(SCZ_CE_INO) | 336 __BIT(SCZ_SERR_INO); 337 } else 338 ino_bitmap = (uint64_t) ino_bitmaps[1] << 32 | ino_bitmaps[0]; 339 DPRINTF(SDB_INTR, ("ino_bitmap=0x%016" PRIx64 "\n", ino_bitmap)); 340 341 if (ino_bitmap & __BIT(SCZ_PCIERR_A_INO)) 342 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 343 pbm, SCZ_PCIERR_A_INO, "pci_a"); 344 if (ino_bitmap & __BIT(SCZ_PCIERR_B_INO)) 345 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 346 pbm, SCZ_PCIERR_B_INO, "pci_b"); 347 if (ino_bitmap & __BIT(SCZ_UE_INO)) 348 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 349 "ue"); 350 if (ino_bitmap & __BIT(SCZ_CE_INO)) 351 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 352 "ce"); 353 if (ino_bitmap & __BIT(SCZ_SERR_INO)) 354 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 355 SCZ_SERR_INO, "safari"); 356 357 if (sc->sc_tomatillo) { 358 /* 359 * Enable the IOCACHE. 360 */ 361 uint64_t iocache_csr; 362 363 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 364 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 365 TOM_IOCACHE_CSR_PEN_RDM | 366 TOM_IOCACHE_CSR_PEN_ONE | 367 TOM_IOCACHE_CSR_PEN_LINE; 368 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 369 } 370 371 config_found(sc->sc_dev, &pba, schizo_print); 372 } 373 374 int 375 schizo_ue(void *vsc) 376 { 377 struct schizo_softc *sc = vsc; 378 379 panic("%s: uncorrectable error", device_xname(sc->sc_dev)); 380 return (1); 381 } 382 383 int 384 schizo_ce(void *vsc) 385 { 386 struct schizo_softc *sc = vsc; 387 388 panic("%s: correctable error", device_xname(sc->sc_dev)); 389 return (1); 390 } 391 392 int 393 schizo_pci_error(void *vpbm) 394 { 395 struct schizo_pbm *sp = vpbm; 396 struct schizo_softc *sc = sp->sp_sc; 397 u_int64_t afsr, afar, ctrl, tfar; 398 u_int32_t csr; 399 char bits[128]; 400 401 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 402 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 403 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 404 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 405 406 printf("%s: pci bus %c error\n", device_xname(sc->sc_dev), 407 sp->sp_bus_a ? 'A' : 'B'); 408 409 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 410 printf("PCIAFSR=%s\n", bits); 411 printf("PCIAFAR=%" PRIx64 "\n", afar); 412 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 413 printf("PCICTRL=%s\n", bits); 414 #ifdef PCI_COMMAND_STATUS_BITS 415 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 416 printf("PCICSR=%s\n", bits); 417 #endif 418 419 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 420 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 421 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 422 423 if ((ctrl & TOM_IOMMU_ERR) == 0) 424 goto clear_error; 425 426 if (sc->sc_tomatillo) { 427 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 428 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 429 } 430 431 /* These are non-fatal if target abort was signalled. */ 432 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 433 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 434 ctrl & TOM_IOMMU_BADVA_ERR) { 435 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 436 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 437 goto clear_error; 438 } 439 } 440 } 441 442 panic("%s: fatal", device_xname(sc->sc_dev)); 443 444 clear_error: 445 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 446 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 447 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 448 return (1); 449 } 450 451 int 452 schizo_safari_error(void *vsc) 453 { 454 struct schizo_softc *sc = vsc; 455 456 printf("%s: safari error\n", device_xname(sc->sc_dev)); 457 458 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 459 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 460 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 461 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 462 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 463 464 panic("%s: fatal", device_xname(sc->sc_dev)); 465 return (1); 466 } 467 468 void 469 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 470 { 471 struct iommu_state *is = &pbm->sp_is; 472 int *vdma = NULL, nitem, tsbsize = 7; 473 u_int32_t iobase = -1; 474 char *name; 475 476 /* punch in our copies */ 477 is->is_bustag = pbm->sp_regt; 478 bus_space_subregion(is->is_bustag, pbm->sp_regh, 479 offsetof(struct schizo_pbm_regs, iommu), 480 sizeof(struct iommureg2), 481 &is->is_iommu); 482 483 /* 484 * Separate the men from the boys. If the `virtual-dma' 485 * property exists, use it. 486 */ 487 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 488 (void **)&vdma)) { 489 /* Damn. Gotta use these values. */ 490 iobase = vdma[0]; 491 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 492 switch (vdma[1]) { 493 TSBCASE(1); TSBCASE(2); TSBCASE(3); 494 TSBCASE(4); TSBCASE(5); TSBCASE(6); 495 default: 496 printf("bogus tsb size %x, using 7\n", vdma[1]); 497 TSBCASE(7); 498 } 499 #undef TSBCASE 500 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 501 free(vdma, M_DEVBUF); 502 } else { 503 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 504 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 505 } 506 507 /* give us a nice name.. */ 508 name = (char *)kmem_alloc(32, KM_NOSLEEP); 509 if (name == NULL) 510 511 panic("couldn't kmem_alloc iommu name"); 512 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 513 514 iommu_init(name, is, tsbsize, iobase); 515 } 516 517 int 518 schizo_print(void *aux, const char *p) 519 { 520 521 if (p == NULL) 522 return (UNCONF); 523 return (QUIET); 524 } 525 526 pcireg_t 527 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 528 { 529 struct schizo_pbm *sp = pc->cookie; 530 struct cpu_info *ci = curcpu(); 531 pcireg_t val = (pcireg_t)~0; 532 int s; 533 534 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 535 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 536 s = splhigh(); 537 ci->ci_pci_probe = true; 538 membar_Sync(); 539 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 540 PCITAG_OFFSET(tag) + reg); 541 membar_Sync(); 542 if (ci->ci_pci_fault) 543 val = (pcireg_t)~0; 544 ci->ci_pci_probe = ci->ci_pci_fault = false; 545 splx(s); 546 } 547 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 548 return (val); 549 } 550 551 void 552 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 553 { 554 struct schizo_pbm *sp = pc->cookie; 555 556 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 557 (long)tag, reg, (int)data)); 558 559 /* If we don't know it, just punt it. */ 560 if (PCITAG_NODE(tag) == -1) { 561 DPRINTF(SDB_CONF, (" .. bad addr\n")); 562 return; 563 } 564 565 if ((unsigned int)reg >= PCI_CONF_SIZE) 566 return; 567 568 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 569 PCITAG_OFFSET(tag) + reg, data); 570 DPRINTF(SDB_CONF, (" .. done\n")); 571 } 572 573 void 574 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 575 int (*handler)(void *), void *arg, int ino, const char *what) 576 { 577 struct intrhand *ih; 578 u_int64_t mapoff, clroff; 579 uintptr_t intrregs; 580 581 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 582 ino, sc->sc_ign, handler, arg)); 583 584 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 585 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 586 ino |= sc->sc_ign; 587 588 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 589 mapoff, clroff)); 590 591 ih = intrhand_alloc(); 592 593 ih->ih_arg = arg; 594 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 595 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 596 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 597 ih->ih_fun = handler; 598 ih->ih_pil = ipl; 599 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 600 ih->ih_pending = 0; 601 602 intr_establish(ipl, ipl != IPL_VM, ih); 603 604 schizo_pbm_write(pbm, mapoff, 605 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 606 schizo_pbm_write(pbm, clroff, 0); 607 } 608 609 bus_space_tag_t 610 schizo_alloc_mem_tag(struct schizo_pbm *sp) 611 { 612 return (schizo_alloc_bus_tag(sp, "mem", PCI_MEMORY_BUS_SPACE)); 613 } 614 615 bus_space_tag_t 616 schizo_alloc_io_tag(struct schizo_pbm *sp) 617 { 618 return (schizo_alloc_bus_tag(sp, "io", PCI_IO_BUS_SPACE)); 619 } 620 621 bus_space_tag_t 622 schizo_alloc_config_tag(struct schizo_pbm *sp) 623 { 624 return (schizo_alloc_bus_tag(sp, "cfg", PCI_CONFIG_BUS_SPACE)); 625 } 626 627 bus_space_tag_t 628 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 629 { 630 struct schizo_softc *sc = pbm->sp_sc; 631 bus_space_tag_t bt; 632 633 bt = (bus_space_tag_t) kmem_zalloc(sizeof(struct sparc_bus_space_tag), 634 KM_NOSLEEP); 635 if (bt == NULL) 636 panic("schizo: could not allocate bus tag"); 637 638 bt->cookie = pbm; 639 bt->parent = sc->sc_bustag; 640 bt->type = type; 641 bt->sparc_bus_map = schizo_bus_map; 642 bt->sparc_bus_mmap = schizo_bus_mmap; 643 bt->sparc_intr_establish = schizo_intr_establish; 644 return (bt); 645 } 646 647 bus_dma_tag_t 648 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 649 { 650 struct schizo_softc *sc = pbm->sp_sc; 651 bus_dma_tag_t dt, pdt = sc->sc_dmat; 652 653 dt = kmem_zalloc(sizeof(*dt), KM_NOSLEEP); 654 if (dt == NULL) 655 panic("schizo: could not alloc dma tag"); 656 657 dt->_cookie = pbm; 658 dt->_parent = pdt; 659 #define PCOPY(x) dt->x = pdt->x 660 dt->_dmamap_create = schizo_dmamap_create; 661 PCOPY(_dmamap_destroy); 662 dt->_dmamap_load = iommu_dvmamap_load; 663 PCOPY(_dmamap_load_mbuf); 664 PCOPY(_dmamap_load_uio); 665 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 666 dt->_dmamap_unload = iommu_dvmamap_unload; 667 dt->_dmamap_sync = iommu_dvmamap_sync; 668 dt->_dmamem_alloc = iommu_dvmamem_alloc; 669 dt->_dmamem_free = iommu_dvmamem_free; 670 dt->_dmamem_map = iommu_dvmamem_map; 671 dt->_dmamem_unmap = iommu_dvmamem_unmap; 672 PCOPY(_dmamem_mmap); 673 #undef PCOPY 674 return (dt); 675 } 676 677 pci_chipset_tag_t 678 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 679 { 680 pci_chipset_tag_t npc; 681 682 npc = kmem_alloc(sizeof *npc, KM_NOSLEEP); 683 if (npc == NULL) 684 panic("schizo: could not allocate pci_chipset_tag_t"); 685 memcpy(npc, pc, sizeof *pc); 686 npc->cookie = pbm; 687 npc->rootnode = node; 688 npc->spc_conf_read = schizo_conf_read; 689 npc->spc_conf_write = schizo_conf_write; 690 npc->spc_intr_map = schizo_pci_intr_map; 691 npc->spc_intr_establish = schizo_pci_intr_establish; 692 npc->spc_find_ino = NULL; 693 return (npc); 694 } 695 696 int 697 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 698 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 699 bus_dmamap_t *dmamp) 700 { 701 struct schizo_pbm *pbm = t->_cookie; 702 int error; 703 704 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 705 boundary, flags, dmamp); 706 if (error == 0) 707 (*dmamp)->_dm_cookie = &pbm->sp_sb; 708 return error; 709 } 710 711 static struct schizo_range * 712 get_schizorange(struct schizo_pbm *pbm, int ss) 713 { 714 int i; 715 716 for (i = 0; i < pbm->sp_nrange; i++) { 717 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 718 return (&pbm->sp_range[i]); 719 } 720 /* not found */ 721 return (NULL); 722 } 723 724 int 725 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 726 int flags, vaddr_t unused, bus_space_handle_t *hp) 727 { 728 bus_addr_t paddr; 729 struct schizo_pbm *pbm = t->cookie; 730 struct schizo_softc *sc = pbm->sp_sc; 731 struct schizo_range *sr; 732 int ss; 733 734 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 735 t->type, 736 (unsigned long long)offset, 737 (unsigned long long)size, 738 flags)); 739 740 ss = sparc_pci_childspace(t->type); 741 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 742 743 sr = get_schizorange(pbm, ss); 744 if (sr != NULL) { 745 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 746 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 747 "space %lx offset %lx paddr %qx\n", 748 __func__, (long)ss, (long)offset, 749 (unsigned long long)paddr)); 750 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 751 flags, 0, hp)); 752 } 753 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 754 return (EINVAL); 755 } 756 757 static paddr_t 758 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 759 int flags) 760 { 761 bus_addr_t offset = paddr; 762 struct schizo_pbm *pbm = t->cookie; 763 struct schizo_softc *sc = pbm->sp_sc; 764 struct schizo_range *sr; 765 int ss; 766 767 ss = sparc_pci_childspace(t->type); 768 769 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 770 prot, flags, (unsigned long long)paddr)); 771 772 sr = get_schizorange(pbm, ss); 773 if (sr != NULL) { 774 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 775 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 776 "space %lx offset %lx paddr %qx\n", 777 __func__, (long)ss, (long)offset, 778 (unsigned long long)paddr)); 779 return (bus_space_mmap(sc->sc_bustag, paddr, off, 780 prot, flags)); 781 } 782 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 783 return (-1); 784 } 785 786 /* 787 * Set the IGN for this schizo into the handle. 788 */ 789 int 790 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 791 { 792 struct schizo_pbm *pbm = pa->pa_pc->cookie; 793 struct schizo_softc *sc = pbm->sp_sc; 794 795 DPRINTF(SDB_INTMAP, ("IGN %x", *ihp)); 796 *ihp |= sc->sc_ign; 797 DPRINTF(SDB_INTMAP, (" adjusted to %x\n", *ihp)); 798 return (0); 799 } 800 801 static void * 802 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 803 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 804 { 805 struct schizo_pbm *pbm = t->cookie; 806 struct intrhand *ih = NULL; 807 uint64_t mapoff, clroff; 808 uintptr_t intrregs; 809 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 810 int ino; 811 long vec; 812 813 vec = INTVEC(ihandle); 814 ino = INTINO(vec); 815 816 ih = intrhand_alloc(); 817 818 DPRINTF(SDB_INTR, ("\n%s: ihandle %x level %d fn %p arg %p\n", __func__, 819 ihandle, level, handler, arg)); 820 821 if (level == IPL_NONE) 822 level = INTLEV(vec); 823 if (level == IPL_NONE) { 824 printf(": no IPL, setting IPL 2.\n"); 825 level = 2; 826 } 827 828 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 829 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 830 831 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 832 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 833 834 ih->ih_ivec = ihandle; 835 836 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 837 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 838 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 839 840 if (INTIGN(vec) == 0) 841 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 842 else 843 ino |= vec & INTMAP_IGN; 844 845 /* Register the map and clear intr registers */ 846 ih->ih_map = intrmapptr; 847 ih->ih_clr = intrclrptr; 848 849 ih->ih_fun = handler; 850 ih->ih_arg = arg; 851 ih->ih_pil = level; 852 ih->ih_number = ino; 853 ih->ih_pending = 0; 854 855 DPRINTF(SDB_INTR, ( 856 "; installing handler %p arg %p with inr %x pil %u\n", 857 handler, arg, ino, (u_int)ih->ih_pil)); 858 859 intr_establish(ih->ih_pil, level != IPL_VM, ih); 860 861 /* 862 * Enable the interrupt now we have the handler installed. 863 * Read the current value as we can't change it besides the 864 * valid bit so so make sure only this bit is changed. 865 */ 866 if (intrmapptr) { 867 u_int64_t imap; 868 869 imap = schizo_pbm_readintr(pbm, mapoff); 870 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 871 (unsigned long long)imap)); 872 imap |= INTMAP_V; 873 imap |= (CPU_UPAID << INTMAP_TID_SHIFT); 874 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 875 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 876 (unsigned long long)imap)); 877 schizo_pbm_writeintr(pbm, mapoff, imap); 878 imap = schizo_pbm_readintr(pbm, mapoff); 879 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 880 (unsigned long long)imap)); 881 ih->ih_number |= imap & INTMAP_INR; 882 } 883 if (intrclrptr) { 884 /* set state to IDLE */ 885 schizo_pbm_writeintr(pbm, clroff, 0); 886 } 887 888 return (ih); 889 } 890 891 static void * 892 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 893 int (*func)(void *), void *arg) 894 { 895 void *cookie; 896 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 897 898 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 899 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 900 901 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 902 return (cookie); 903 } 904 905 #ifdef DEBUG 906 void 907 schizo_print_regs(int unit, int what) 908 { 909 device_t dev; 910 struct schizo_softc *sc; 911 struct schizo_pbm *pbm; 912 const struct schizo_regname *r; 913 int i; 914 u_int64_t reg; 915 916 dev = device_find_by_driver_unit("schizo", unit); 917 if (dev == NULL) { 918 printf("Can't find device schizo%d\n", unit); 919 return; 920 } 921 922 if (!what) { 923 printf("0x01: Safari registers\n"); 924 printf("0x02: PCI registers\n"); 925 printf("0x04: Scratch pad registers (Tomatillo only)\n"); 926 printf("0x08: IOMMU registers\n"); 927 printf("0x10: Streaming cache registers (Schizo only)\n"); 928 printf("0x20: Interrupt registers\n"); 929 printf("0x40: I-chip registers (Tomatillo only)\n"); 930 return; 931 } 932 sc = device_private(dev); 933 pbm = sc->sc_pbm; 934 printf("%s (leaf %c) registers:\n", device_xname(sc->sc_dev), 935 pbm->sp_bus_a ? 'A' : 'B'); 936 937 printf(" Safari registers:\n"); 938 if (what & 0x01) { 939 for (r = schizo_regnames; r->size != 0; ++r) 940 for (i = 0; i <= r->n_reg; i += r->size) { 941 if ((!sc->sc_tomatillo && 942 !(r->type & REG_TYPE_SCHIZO)) || 943 (sc->sc_tomatillo && 944 !(r->type & REG_TYPE_TOMATILLO))) 945 continue; 946 switch (r->size) { 947 case 1: 948 reg = schizo_read_1(sc, r->offset + i); 949 break; 950 case 8: 951 /* fallthrough */ 952 default: 953 reg = schizo_read(sc, r->offset + i); 954 break; 955 } 956 printf("0x%06" PRIx64 " = 0x%016" PRIx64 " (%s", 957 r->offset + i, reg, r->name); 958 if (r->n_reg) 959 printf(" %d)\n", i / r->size); 960 else 961 printf(")\n"); 962 } 963 } 964 965 if (what & 0x02) { 966 printf(" PCI registers:\n"); 967 for (r = schizo_pbm_regnames; r->size != 0; ++r) 968 for (i = 0; i <= r->n_reg; i += r->size) { 969 if ((!sc->sc_tomatillo && 970 !(r->type & REG_TYPE_SCHIZO)) || 971 (sc->sc_tomatillo && 972 !(r->type & REG_TYPE_TOMATILLO))) 973 continue; 974 if ((pbm->sp_bus_a && 975 !(r->type & REG_TYPE_LEAF_A)) || 976 (!pbm->sp_bus_a && 977 !(r->type & REG_TYPE_LEAF_B))) 978 continue; 979 reg = schizo_pbm_read(pbm, r->offset + i); 980 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 981 " (%s", r->offset + i, reg, r->name); 982 if (r->n_reg) 983 printf(" %d)\n", i / r->size); 984 else 985 printf(")\n"); 986 } 987 } 988 989 if (what & 0x04 && sc->sc_tomatillo) { 990 printf(" Scratch pad registers:\n"); 991 for (r = tomatillo_scratch_regnames; r->size != 0; ++r) 992 for (i = 0; i <= r->n_reg; i += r->size) { 993 reg = schizo_pbm_read(pbm, r->offset + i); 994 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 995 " (%s", r->offset + i, reg, r->name); 996 if (r->n_reg) 997 printf(" %d)\n", i / r->size); 998 else 999 printf(")\n"); 1000 } 1001 } 1002 1003 if (what & 0x08) { 1004 printf(" IOMMU registers:\n"); 1005 for (r = schizo_iommu_regnames; r->size != 0; ++r) 1006 for (i = 0; i <= r->n_reg; i += r->size) { 1007 if ((!sc->sc_tomatillo && 1008 !(r->type & REG_TYPE_SCHIZO)) || 1009 (sc->sc_tomatillo && 1010 !(r->type & REG_TYPE_TOMATILLO))) 1011 continue; 1012 reg = schizo_pbm_read(pbm, r->offset + i); 1013 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1014 " (%s", r->offset + i, reg, r->name); 1015 if (r->n_reg) 1016 printf(" %d)\n", i / r->size); 1017 else 1018 printf(")\n"); 1019 } 1020 } 1021 1022 if (what & 0x10 && !sc->sc_tomatillo) { 1023 printf(" Streaming cache registers:\n"); 1024 for (r = schizo_stream_regnames; r->size != 0; ++r) 1025 for (i = 0; i <= r->n_reg; i += r->size) { 1026 reg = schizo_pbm_read(pbm, r->offset + i); 1027 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1028 " (%s", r->offset + i, reg, r->name); 1029 if (r->n_reg) 1030 printf(" %d)\n", i / r->size); 1031 else 1032 printf(")\n"); 1033 } 1034 } 1035 1036 if (what & 0x20) { 1037 printf(" Interrupt registers:\n"); 1038 for (r = schizo_intr_regnames; r->size != 0; ++r) 1039 for (i = 0; i <= r->n_reg; i += r->size) { 1040 if ((!sc->sc_tomatillo && 1041 !(r->type & REG_TYPE_SCHIZO)) || 1042 (sc->sc_tomatillo && 1043 !(r->type & REG_TYPE_TOMATILLO))) 1044 continue; 1045 reg = schizo_pbm_readintr(pbm, r->offset + i); 1046 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1047 " (%s", r->offset + i, reg, r->name); 1048 if (r->n_reg) 1049 printf(" %d)\n", i / r->size); 1050 else 1051 printf(")\n"); 1052 } 1053 } 1054 1055 if (what & 0x40 && sc->sc_tomatillo) { 1056 printf(" I-chip registers:\n"); 1057 for (r = tomatillo_ichip_regnames; r->size != 0; ++r) 1058 for (i = 0; i <= r->n_reg; i += r->size) { 1059 if ((sc->sc_tomatillo && 1060 !(r->type & REG_TYPE_TOMATILLO))) 1061 continue; 1062 reg = tomatillo_pbm_readichip(pbm, 1063 r->offset + i); 1064 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1065 " (%s", r->offset + i, reg, r->name); 1066 if (r->n_reg) 1067 printf(" %d)\n", i / r->size); 1068 else 1069 printf(")\n"); 1070 } 1071 } 1072 } 1073 #endif 1074
Indexes created Tue Sep 30 20:09:53 GMT 2025