schizo.c revision 1.41
1 /* $NetBSD: schizo.c,v 1.41 2019/02/09 11:27:05 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010, 2012 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.41 2019/02/09 11:27:05 mrg Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/kmem.h> 40 #include <sys/malloc.h> 41 #include <sys/systm.h> 42 #include <sys/time.h> 43 #include <sys/reboot.h> 44 45 #define _SPARC_BUS_DMA_PRIVATE 46 #include <sys/bus.h> 47 #include <machine/autoconf.h> 48 #include <machine/psl.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/dev/iommuvar.h> 55 #include <sparc64/dev/schizoreg.h> 56 #include <sparc64/dev/schizovar.h> 57 #include <sparc64/sparc64/cache.h> 58 59 #ifdef DEBUG 60 #define SDB_PROM 0x01 61 #define SDB_BUSMAP 0x02 62 #define SDB_INTR 0x04 63 #define SDB_INTMAP 0x08 64 #define SDB_CONF 0x10 65 int schizo_debug = 0x0; 66 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 67 #else 68 #define DPRINTF(l, s) 69 #endif 70 71 extern struct sparc_pci_chipset _sparc_pci_chipset; 72 73 static int schizo_match(device_t, cfdata_t, void *); 74 static void schizo_attach(device_t, device_t, void *); 75 static int schizo_print(void *aux, const char *p); 76 77 #ifdef DEBUG 78 void schizo_print_regs(int unit, int what); 79 #endif 80 81 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc), 82 schizo_match, schizo_attach, NULL, NULL); 83 84 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 85 86 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 87 int (*handler)(void *), void *, int, const char *); 88 int schizo_ue(void *); 89 int schizo_ce(void *); 90 int schizo_safari_error(void *); 91 int schizo_pci_error(void *); 92 93 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 94 pci_chipset_tag_t); 95 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 96 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 97 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 98 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 99 int); 100 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 101 102 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 103 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 104 105 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 106 int flags, vaddr_t unused, bus_space_handle_t *hp); 107 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 108 off_t off, int prot, int flags); 109 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 110 void *, void(*)(void)); 111 static int schizo_pci_intr_map(const struct pci_attach_args *, 112 pci_intr_handle_t *); 113 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 114 int, int (*)(void *), void *); 115 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 116 bus_size_t, int, bus_dmamap_t *); 117 118 int 119 schizo_match(device_t parent, cfdata_t match, void *aux) 120 { 121 struct mainbus_attach_args *ma = aux; 122 char *str; 123 124 if (strcmp(ma->ma_name, "pci") != 0) 125 return (0); 126 127 str = prom_getpropstring(ma->ma_node, "model"); 128 if (strcmp(str, "schizo") == 0) 129 return (1); 130 131 str = prom_getpropstring(ma->ma_node, "compatible"); 132 if (strcmp(str, "pci108e,8001") == 0) 133 return (1); 134 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 135 return (1); 136 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 137 return (1); 138 139 return (0); 140 } 141 142 void 143 schizo_attach(device_t parent, device_t self, void *aux) 144 { 145 struct schizo_softc *sc = device_private(self); 146 struct mainbus_attach_args *ma = aux; 147 struct schizo_pbm *pbm; 148 struct iommu_state *is; 149 struct pcibus_attach_args pba; 150 uint64_t reg, eccctrl, ino_bitmap; 151 int *busranges = NULL, nranges, *ino_bitmaps = NULL, nbitmaps; 152 char *str; 153 bool no_sc; 154 155 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 156 str = prom_getpropstring(ma->ma_node, "compatible"); 157 if (strcmp(str, "pci108e,a801") == 0) 158 sc->sc_tomatillo = 1; 159 160 sc->sc_dev = self; 161 sc->sc_node = ma->ma_node; 162 sc->sc_dmat = ma->ma_dmatag; 163 sc->sc_bustag = ma->ma_bustag; 164 165 sc->sc_ver = prom_getpropint(sc->sc_node, "version#", 0); 166 167 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 168 sizeof(struct schizo_regs), 0, 169 &sc->sc_ctrlh)) { 170 aprint_error(": failed to map registers\n"); 171 return; 172 } 173 174 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 175 176 /* enable schizo ecc error interrupts */ 177 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 178 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 179 SCZ_ECCCTRL_UE_INTEN | 180 SCZ_ECCCTRL_CE_INTEN; 181 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 182 183 pbm = kmem_zalloc(sizeof(*pbm), KM_NOSLEEP); 184 if (pbm == NULL) 185 panic("schizo: can't alloc schizo pbm"); 186 187 #ifdef DEBUG 188 sc->sc_pbm = pbm; 189 #endif 190 pbm->sp_sc = sc; 191 pbm->sp_regt = sc->sc_bustag; 192 193 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 194 pbm->sp_bus_a = 1; 195 else 196 pbm->sp_bus_a = 0; 197 198 /* 199 * Map interrupt registers 200 */ 201 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 202 ma->ma_reg[0].ur_len, 203 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 204 aprint_error(": failed to map interrupt registers\n"); 205 kmem_free(pbm, sizeof(*pbm)); 206 return; 207 } 208 209 #ifdef DEBUG 210 /* 211 * Map ichip registers 212 */ 213 if (sc->sc_tomatillo) 214 if (bus_space_map(sc->sc_bustag, ma->ma_reg[3].ur_paddr, 215 ma->ma_reg[3].ur_len, 216 BUS_SPACE_MAP_LINEAR, &pbm->sp_ichiph)) { 217 aprint_error(": failed to map ichip registers\n"); 218 kmem_free(pbm, sizeof(*pbm)); 219 return; 220 } 221 #endif 222 223 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 224 &pbm->sp_nrange, (void **)&pbm->sp_range)) 225 panic("schizo: can't get ranges"); 226 227 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 228 (void **)&busranges)) 229 panic("schizo: can't get bus-range"); 230 231 aprint_normal(": %s, version %d, ign %x, bus %c %d to %d\n", 232 sc->sc_tomatillo ? "Tomatillo" : "Schizo", sc->sc_ver, 233 sc->sc_ign, pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 234 aprint_naive("\n"); 235 236 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 237 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 238 offsetof(struct schizo_regs, pbm_b), 239 sizeof(struct schizo_pbm_regs), 240 &pbm->sp_regh)) { 241 panic("schizo: unable to create PBM handle"); 242 } 243 244 is = &pbm->sp_is; 245 pbm->sp_sb.sb_is = is; 246 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 247 if (no_sc) 248 aprint_debug_dev(sc->sc_dev, "no streaming buffers\n"); 249 else { 250 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 251 252 /* 253 * Initialize the strbuf_ctl. 254 * 255 * The flush sync buffer must be 64-byte aligned. 256 */ 257 is->is_sb[0] = &pbm->sp_sb; 258 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 259 260 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 261 offsetof(struct schizo_pbm_regs, strbuf), 262 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 263 } 264 265 aprint_normal_dev(sc->sc_dev, " "); 266 if (sc->sc_tomatillo) 267 is->is_flags |= IOMMU_SYNC_BEFORE_UNMAP; 268 schizo_init_iommu(sc, pbm); 269 270 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 271 pbm->sp_iot = schizo_alloc_io_tag(pbm); 272 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 273 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 274 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 275 (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0); 276 277 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 278 panic("schizo: could not map config space"); 279 280 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 281 &_sparc_pci_chipset); 282 pbm->sp_pc->spc_busmax = busranges[1]; 283 pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode), 284 KM_NOSLEEP); 285 if (pbm->sp_pc->spc_busnode == NULL) 286 panic("schizo: kmem_alloc busnode"); 287 288 pba.pba_bus = busranges[0]; 289 pba.pba_bridgetag = NULL; 290 pba.pba_pc = pbm->sp_pc; 291 pba.pba_flags = pbm->sp_flags; 292 pba.pba_dmat = pbm->sp_dmat; 293 pba.pba_dmat64 = NULL; /* XXX */ 294 pba.pba_memt = pbm->sp_memt; 295 pba.pba_iot = pbm->sp_iot; 296 297 free(busranges, M_DEVBUF); 298 299 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 300 301 /* clear out the bus errors */ 302 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 303 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 304 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 305 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 306 307 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 308 /* enable/disable error interrupts and arbiter */ 309 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT; 310 if (sc->sc_tomatillo) { 311 reg &= ~SCZ_PCICTRL_SBH_INT; 312 reg |= TOM_PCICTRL_ARB; 313 reg |= TOM_PCICTRL_PRM | TOM_PCICTRL_PRO | 314 TOM_PCICTRL_PRL; 315 if (sc->sc_ver <= 1) /* 2.0 */ 316 reg |= TOM_PCICTRL_DTO_INT; 317 else 318 reg |= SCZ_PCICTRL_PTO; 319 } else 320 reg |= SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_ARB; 321 if (OF_getproplen(sc->sc_node, "no-bus-parking") < 0) 322 reg |= SCZ_PCICTRL_PARK; 323 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 324 325 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 326 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 327 SCZ_PCIDIAG_D_INTSYNC); 328 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 329 330 if (prom_getprop(sc->sc_node, "ino-bitmap", sizeof(int), &nbitmaps, 331 (void **)&ino_bitmaps)) { 332 /* No property - set defaults (double map UE, CE, SERR). */ 333 if (pbm->sp_bus_a) 334 ino_bitmap = __BIT(SCZ_PCIERR_A_INO); 335 else 336 ino_bitmap = __BIT(SCZ_PCIERR_B_INO); 337 ino_bitmap |= __BIT(SCZ_UE_INO) | __BIT(SCZ_CE_INO) | 338 __BIT(SCZ_SERR_INO); 339 } else 340 ino_bitmap = (uint64_t) ino_bitmaps[1] << 32 | ino_bitmaps[0]; 341 DPRINTF(SDB_INTR, ("ino_bitmap=0x%016" PRIx64 "\n", ino_bitmap)); 342 343 if (ino_bitmap & __BIT(SCZ_PCIERR_A_INO)) 344 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 345 pbm, SCZ_PCIERR_A_INO, "pci_a"); 346 if (ino_bitmap & __BIT(SCZ_PCIERR_B_INO)) 347 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 348 pbm, SCZ_PCIERR_B_INO, "pci_b"); 349 if (ino_bitmap & __BIT(SCZ_UE_INO)) 350 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 351 "ue"); 352 if (ino_bitmap & __BIT(SCZ_CE_INO)) 353 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 354 "ce"); 355 if (ino_bitmap & __BIT(SCZ_SERR_INO)) 356 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 357 SCZ_SERR_INO, "safari"); 358 359 if (sc->sc_tomatillo) { 360 /* 361 * Enable the IOCACHE. 362 */ 363 uint64_t iocache_csr; 364 365 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 366 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 367 TOM_IOCACHE_CSR_PEN_RDM | 368 TOM_IOCACHE_CSR_PEN_ONE | 369 TOM_IOCACHE_CSR_PEN_LINE; 370 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 371 } 372 373 config_found(sc->sc_dev, &pba, schizo_print); 374 } 375 376 int 377 schizo_ue(void *vsc) 378 { 379 struct schizo_softc *sc = vsc; 380 381 panic("%s: uncorrectable error", device_xname(sc->sc_dev)); 382 return (1); 383 } 384 385 int 386 schizo_ce(void *vsc) 387 { 388 struct schizo_softc *sc = vsc; 389 390 panic("%s: correctable error", device_xname(sc->sc_dev)); 391 return (1); 392 } 393 394 int 395 schizo_pci_error(void *vpbm) 396 { 397 struct schizo_pbm *sp = vpbm; 398 struct schizo_softc *sc = sp->sp_sc; 399 u_int64_t afsr, afar, ctrl, tfar; 400 u_int32_t csr; 401 char bits[128]; 402 403 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 404 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 405 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 406 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 407 408 printf("%s: pci bus %c error\n", device_xname(sc->sc_dev), 409 sp->sp_bus_a ? 'A' : 'B'); 410 411 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 412 printf("PCIAFSR=%s\n", bits); 413 printf("PCIAFAR=%" PRIx64 "\n", afar); 414 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 415 printf("PCICTRL=%s\n", bits); 416 #ifdef PCI_COMMAND_STATUS_BITS 417 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 418 printf("PCICSR=%s\n", bits); 419 #endif 420 421 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 422 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 423 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 424 425 if ((ctrl & TOM_IOMMU_ERR) == 0) 426 goto clear_error; 427 428 if (sc->sc_tomatillo) { 429 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 430 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 431 } 432 433 /* These are non-fatal if target abort was signalled. */ 434 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 435 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 436 ctrl & TOM_IOMMU_BADVA_ERR) { 437 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 438 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 439 goto clear_error; 440 } 441 } 442 } 443 444 panic("%s: %s: fatal", __func__, device_xname(sc->sc_dev)); 445 446 clear_error: 447 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 448 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 449 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 450 return (1); 451 } 452 453 int 454 schizo_safari_error(void *vsc) 455 { 456 struct schizo_softc *sc = vsc; 457 458 printf("%s: safari error\n", device_xname(sc->sc_dev)); 459 460 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 461 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 462 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 463 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 464 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 465 466 panic("%s: %s: fatal", __func__, device_xname(sc->sc_dev)); 467 return (1); 468 } 469 470 void 471 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 472 { 473 struct iommu_state *is = &pbm->sp_is; 474 int *vdma = NULL, nitem, tsbsize = 7; 475 u_int32_t iobase = -1; 476 char *name; 477 478 /* punch in our copies */ 479 is->is_bustag = pbm->sp_regt; 480 bus_space_subregion(is->is_bustag, pbm->sp_regh, 481 offsetof(struct schizo_pbm_regs, iommu), 482 sizeof(struct iommureg2), 483 &is->is_iommu); 484 485 /* 486 * Separate the men from the boys. If the `virtual-dma' 487 * property exists, use it. 488 */ 489 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 490 (void **)&vdma)) { 491 /* Damn. Gotta use these values. */ 492 iobase = vdma[0]; 493 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 494 switch (vdma[1]) { 495 TSBCASE(1); 496 TSBCASE(2); 497 TSBCASE(3); 498 TSBCASE(4); 499 TSBCASE(5); 500 TSBCASE(6); 501 TSBCASE(7); 502 default: 503 printf("bogus tsb size %x, using 7\n", vdma[1]); 504 tsbsize = 7; 505 } 506 #undef TSBCASE 507 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 508 free(vdma, M_DEVBUF); 509 } else { 510 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 511 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 512 } 513 514 /* give us a nice name.. */ 515 name = (char *)kmem_alloc(32, KM_NOSLEEP); 516 if (name == NULL) 517 518 panic("couldn't kmem_alloc iommu name"); 519 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 520 521 iommu_init(name, is, tsbsize, iobase); 522 } 523 524 int 525 schizo_print(void *aux, const char *p) 526 { 527 528 if (p == NULL) 529 return (UNCONF); 530 return (QUIET); 531 } 532 533 pcireg_t 534 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 535 { 536 struct schizo_pbm *sp = pc->cookie; 537 struct cpu_info *ci = curcpu(); 538 pcireg_t val = (pcireg_t)~0; 539 int s; 540 541 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 542 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 543 s = splhigh(); 544 ci->ci_pci_probe = true; 545 membar_Sync(); 546 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 547 PCITAG_OFFSET(tag) + reg); 548 membar_Sync(); 549 if (ci->ci_pci_fault) 550 val = (pcireg_t)~0; 551 ci->ci_pci_probe = ci->ci_pci_fault = false; 552 splx(s); 553 } 554 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 555 return (val); 556 } 557 558 void 559 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 560 { 561 struct schizo_pbm *sp = pc->cookie; 562 563 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 564 (long)tag, reg, (int)data)); 565 566 /* If we don't know it, just punt it. */ 567 if (PCITAG_NODE(tag) == -1) { 568 DPRINTF(SDB_CONF, (" .. bad addr\n")); 569 return; 570 } 571 572 if ((unsigned int)reg >= PCI_CONF_SIZE) 573 return; 574 575 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 576 PCITAG_OFFSET(tag) + reg, data); 577 DPRINTF(SDB_CONF, (" .. done\n")); 578 } 579 580 void 581 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 582 int (*handler)(void *), void *arg, int ino, const char *what) 583 { 584 struct intrhand *ih; 585 u_int64_t mapoff, clroff; 586 uintptr_t intrregs; 587 588 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 589 ino, sc->sc_ign, handler, arg)); 590 591 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 592 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 593 ino |= sc->sc_ign; 594 595 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 596 mapoff, clroff)); 597 598 ih = intrhand_alloc(); 599 600 ih->ih_arg = arg; 601 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 602 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 603 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 604 ih->ih_fun = handler; 605 ih->ih_pil = ipl; 606 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 607 ih->ih_pending = 0; 608 609 intr_establish(ipl, ipl != IPL_VM, ih); 610 611 schizo_pbm_write(pbm, mapoff, 612 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 613 schizo_pbm_write(pbm, clroff, 0); 614 } 615 616 bus_space_tag_t 617 schizo_alloc_mem_tag(struct schizo_pbm *sp) 618 { 619 return (schizo_alloc_bus_tag(sp, "mem", PCI_MEMORY_BUS_SPACE)); 620 } 621 622 bus_space_tag_t 623 schizo_alloc_io_tag(struct schizo_pbm *sp) 624 { 625 return (schizo_alloc_bus_tag(sp, "io", PCI_IO_BUS_SPACE)); 626 } 627 628 bus_space_tag_t 629 schizo_alloc_config_tag(struct schizo_pbm *sp) 630 { 631 return (schizo_alloc_bus_tag(sp, "cfg", PCI_CONFIG_BUS_SPACE)); 632 } 633 634 bus_space_tag_t 635 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 636 { 637 struct schizo_softc *sc = pbm->sp_sc; 638 bus_space_tag_t bt; 639 640 bt = (bus_space_tag_t) kmem_zalloc(sizeof(struct sparc_bus_space_tag), 641 KM_NOSLEEP); 642 if (bt == NULL) 643 panic("schizo: could not allocate bus tag"); 644 645 bt->cookie = pbm; 646 bt->parent = sc->sc_bustag; 647 bt->type = type; 648 bt->sparc_bus_map = schizo_bus_map; 649 bt->sparc_bus_mmap = schizo_bus_mmap; 650 bt->sparc_intr_establish = schizo_intr_establish; 651 return (bt); 652 } 653 654 bus_dma_tag_t 655 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 656 { 657 struct schizo_softc *sc = pbm->sp_sc; 658 bus_dma_tag_t dt, pdt = sc->sc_dmat; 659 660 dt = kmem_zalloc(sizeof(*dt), KM_NOSLEEP); 661 if (dt == NULL) 662 panic("schizo: could not alloc dma tag"); 663 664 dt->_cookie = pbm; 665 dt->_parent = pdt; 666 #define PCOPY(x) dt->x = pdt->x 667 dt->_dmamap_create = schizo_dmamap_create; 668 PCOPY(_dmamap_destroy); 669 dt->_dmamap_load = iommu_dvmamap_load; 670 PCOPY(_dmamap_load_mbuf); 671 PCOPY(_dmamap_load_uio); 672 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 673 dt->_dmamap_unload = iommu_dvmamap_unload; 674 dt->_dmamap_sync = iommu_dvmamap_sync; 675 dt->_dmamem_alloc = iommu_dvmamem_alloc; 676 dt->_dmamem_free = iommu_dvmamem_free; 677 dt->_dmamem_map = iommu_dvmamem_map; 678 dt->_dmamem_unmap = iommu_dvmamem_unmap; 679 PCOPY(_dmamem_mmap); 680 #undef PCOPY 681 return (dt); 682 } 683 684 pci_chipset_tag_t 685 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 686 { 687 pci_chipset_tag_t npc; 688 689 npc = kmem_alloc(sizeof *npc, KM_NOSLEEP); 690 if (npc == NULL) 691 panic("schizo: could not allocate pci_chipset_tag_t"); 692 memcpy(npc, pc, sizeof *pc); 693 npc->cookie = pbm; 694 npc->rootnode = node; 695 npc->spc_conf_read = schizo_conf_read; 696 npc->spc_conf_write = schizo_conf_write; 697 npc->spc_intr_map = schizo_pci_intr_map; 698 npc->spc_intr_establish = schizo_pci_intr_establish; 699 npc->spc_find_ino = NULL; 700 return (npc); 701 } 702 703 int 704 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 705 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 706 bus_dmamap_t *dmamp) 707 { 708 struct schizo_pbm *pbm = t->_cookie; 709 int error; 710 711 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 712 boundary, flags, dmamp); 713 if (error == 0) 714 (*dmamp)->_dm_cookie = &pbm->sp_sb; 715 return error; 716 } 717 718 static struct schizo_range * 719 get_schizorange(struct schizo_pbm *pbm, int ss) 720 { 721 int i; 722 723 for (i = 0; i < pbm->sp_nrange; i++) { 724 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 725 return (&pbm->sp_range[i]); 726 } 727 /* not found */ 728 return (NULL); 729 } 730 731 int 732 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 733 int flags, vaddr_t unused, bus_space_handle_t *hp) 734 { 735 bus_addr_t paddr; 736 struct schizo_pbm *pbm = t->cookie; 737 struct schizo_softc *sc = pbm->sp_sc; 738 struct schizo_range *sr; 739 int ss; 740 741 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 742 t->type, 743 (unsigned long long)offset, 744 (unsigned long long)size, 745 flags)); 746 747 /* 748 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it 749 * out for now 750 */ 751 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 752 753 ss = sparc_pci_childspace(t->type); 754 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 755 756 sr = get_schizorange(pbm, ss); 757 if (sr != NULL) { 758 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 759 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 760 "space %lx offset %lx paddr %qx\n", 761 __func__, (long)ss, (long)offset, 762 (unsigned long long)paddr)); 763 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 764 flags, 0, hp)); 765 } 766 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 767 return (EINVAL); 768 } 769 770 static paddr_t 771 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 772 int flags) 773 { 774 bus_addr_t offset = paddr; 775 struct schizo_pbm *pbm = t->cookie; 776 struct schizo_softc *sc = pbm->sp_sc; 777 struct schizo_range *sr; 778 int ss; 779 780 /* 781 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it 782 * out for now 783 */ 784 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 785 786 ss = sparc_pci_childspace(t->type); 787 788 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 789 prot, flags, (unsigned long long)paddr)); 790 791 sr = get_schizorange(pbm, ss); 792 if (sr != NULL) { 793 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 794 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 795 "space %lx offset %lx paddr %qx\n", 796 __func__, (long)ss, (long)offset, 797 (unsigned long long)paddr)); 798 return (bus_space_mmap(sc->sc_bustag, paddr, off, 799 prot, flags)); 800 } 801 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 802 return (-1); 803 } 804 805 /* 806 * Set the IGN for this schizo into the handle. 807 */ 808 int 809 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 810 { 811 struct schizo_pbm *pbm = pa->pa_pc->cookie; 812 struct schizo_softc *sc = pbm->sp_sc; 813 814 DPRINTF(SDB_INTMAP, ("IGN %x", *ihp)); 815 *ihp |= sc->sc_ign; 816 DPRINTF(SDB_INTMAP, (" adjusted to %x\n", *ihp)); 817 return (0); 818 } 819 820 static void * 821 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 822 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 823 { 824 struct schizo_pbm *pbm = t->cookie; 825 struct intrhand *ih = NULL; 826 uint64_t mapoff, clroff; 827 uintptr_t intrregs; 828 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 829 int ino; 830 long vec; 831 832 vec = INTVEC(ihandle); 833 ino = INTINO(vec); 834 835 ih = intrhand_alloc(); 836 837 DPRINTF(SDB_INTR, ("\n%s: ihandle %x level %d fn %p arg %p\n", __func__, 838 ihandle, level, handler, arg)); 839 840 if (level == IPL_NONE) 841 level = INTLEV(vec); 842 if (level == IPL_NONE) { 843 printf(": no IPL, setting IPL 2.\n"); 844 level = 2; 845 } 846 847 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 848 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 849 850 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 851 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 852 853 ih->ih_ivec = ihandle; 854 855 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 856 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 857 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 858 859 if (INTIGN(vec) == 0) 860 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 861 else 862 ino |= vec & INTMAP_IGN; 863 864 /* Register the map and clear intr registers */ 865 ih->ih_map = intrmapptr; 866 ih->ih_clr = intrclrptr; 867 868 ih->ih_fun = handler; 869 ih->ih_arg = arg; 870 ih->ih_pil = level; 871 ih->ih_number = ino; 872 ih->ih_pending = 0; 873 874 DPRINTF(SDB_INTR, ( 875 "; installing handler %p arg %p with inr %x pil %u\n", 876 handler, arg, ino, (u_int)ih->ih_pil)); 877 878 intr_establish(ih->ih_pil, level != IPL_VM, ih); 879 880 /* 881 * Enable the interrupt now we have the handler installed. 882 * Read the current value as we can't change it besides the 883 * valid bit so so make sure only this bit is changed. 884 */ 885 if (intrmapptr) { 886 u_int64_t imap; 887 888 imap = schizo_pbm_readintr(pbm, mapoff); 889 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 890 (unsigned long long)imap)); 891 imap |= INTMAP_V; 892 imap |= (CPU_UPAID << INTMAP_TID_SHIFT); 893 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 894 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 895 (unsigned long long)imap)); 896 schizo_pbm_writeintr(pbm, mapoff, imap); 897 imap = schizo_pbm_readintr(pbm, mapoff); 898 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 899 (unsigned long long)imap)); 900 ih->ih_number |= imap & INTMAP_INR; 901 } 902 if (intrclrptr) { 903 /* set state to IDLE */ 904 schizo_pbm_writeintr(pbm, clroff, 0); 905 } 906 907 return (ih); 908 } 909 910 static void * 911 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 912 int (*func)(void *), void *arg) 913 { 914 void *cookie; 915 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 916 917 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 918 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 919 920 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 921 return (cookie); 922 } 923 924 #ifdef DEBUG 925 void 926 schizo_print_regs(int unit, int what) 927 { 928 device_t dev; 929 struct schizo_softc *sc; 930 struct schizo_pbm *pbm; 931 const struct schizo_regname *r; 932 int i; 933 u_int64_t reg; 934 935 dev = device_find_by_driver_unit("schizo", unit); 936 if (dev == NULL) { 937 printf("Can't find device schizo%d\n", unit); 938 return; 939 } 940 941 if (!what) { 942 printf("0x01: Safari registers\n"); 943 printf("0x02: PCI registers\n"); 944 printf("0x04: Scratch pad registers (Tomatillo only)\n"); 945 printf("0x08: IOMMU registers\n"); 946 printf("0x10: Streaming cache registers (Schizo only)\n"); 947 printf("0x20: Interrupt registers\n"); 948 printf("0x40: I-chip registers (Tomatillo only)\n"); 949 return; 950 } 951 sc = device_private(dev); 952 pbm = sc->sc_pbm; 953 printf("%s (leaf %c) registers:\n", device_xname(sc->sc_dev), 954 pbm->sp_bus_a ? 'A' : 'B'); 955 956 printf(" Safari registers:\n"); 957 if (what & 0x01) { 958 for (r = schizo_regnames; r->size != 0; ++r) 959 for (i = 0; i <= r->n_reg; i += r->size) { 960 if ((!sc->sc_tomatillo && 961 !(r->type & REG_TYPE_SCHIZO)) || 962 (sc->sc_tomatillo && 963 !(r->type & REG_TYPE_TOMATILLO))) 964 continue; 965 switch (r->size) { 966 case 1: 967 reg = schizo_read_1(sc, r->offset + i); 968 break; 969 case 8: 970 /* fallthrough */ 971 default: 972 reg = schizo_read(sc, r->offset + i); 973 break; 974 } 975 printf("0x%06" PRIx64 " = 0x%016" PRIx64 " (%s", 976 r->offset + i, reg, r->name); 977 if (r->n_reg) 978 printf(" %d)\n", i / r->size); 979 else 980 printf(")\n"); 981 } 982 } 983 984 if (what & 0x02) { 985 printf(" PCI registers:\n"); 986 for (r = schizo_pbm_regnames; r->size != 0; ++r) 987 for (i = 0; i <= r->n_reg; i += r->size) { 988 if ((!sc->sc_tomatillo && 989 !(r->type & REG_TYPE_SCHIZO)) || 990 (sc->sc_tomatillo && 991 !(r->type & REG_TYPE_TOMATILLO))) 992 continue; 993 if ((pbm->sp_bus_a && 994 !(r->type & REG_TYPE_LEAF_A)) || 995 (!pbm->sp_bus_a && 996 !(r->type & REG_TYPE_LEAF_B))) 997 continue; 998 reg = schizo_pbm_read(pbm, r->offset + i); 999 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1000 " (%s", r->offset + i, reg, r->name); 1001 if (r->n_reg) 1002 printf(" %d)\n", i / r->size); 1003 else 1004 printf(")\n"); 1005 } 1006 } 1007 1008 if (what & 0x04 && sc->sc_tomatillo) { 1009 printf(" Scratch pad registers:\n"); 1010 for (r = tomatillo_scratch_regnames; r->size != 0; ++r) 1011 for (i = 0; i <= r->n_reg; i += r->size) { 1012 reg = schizo_pbm_read(pbm, r->offset + i); 1013 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1014 " (%s", r->offset + i, reg, r->name); 1015 if (r->n_reg) 1016 printf(" %d)\n", i / r->size); 1017 else 1018 printf(")\n"); 1019 } 1020 } 1021 1022 if (what & 0x08) { 1023 printf(" IOMMU registers:\n"); 1024 for (r = schizo_iommu_regnames; r->size != 0; ++r) 1025 for (i = 0; i <= r->n_reg; i += r->size) { 1026 if ((!sc->sc_tomatillo && 1027 !(r->type & REG_TYPE_SCHIZO)) || 1028 (sc->sc_tomatillo && 1029 !(r->type & REG_TYPE_TOMATILLO))) 1030 continue; 1031 reg = schizo_pbm_read(pbm, r->offset + i); 1032 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1033 " (%s", r->offset + i, reg, r->name); 1034 if (r->n_reg) 1035 printf(" %d)\n", i / r->size); 1036 else 1037 printf(")\n"); 1038 } 1039 } 1040 1041 if (what & 0x10 && !sc->sc_tomatillo) { 1042 printf(" Streaming cache registers:\n"); 1043 for (r = schizo_stream_regnames; r->size != 0; ++r) 1044 for (i = 0; i <= r->n_reg; i += r->size) { 1045 reg = schizo_pbm_read(pbm, r->offset + i); 1046 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1047 " (%s", r->offset + i, reg, r->name); 1048 if (r->n_reg) 1049 printf(" %d)\n", i / r->size); 1050 else 1051 printf(")\n"); 1052 } 1053 } 1054 1055 if (what & 0x20) { 1056 printf(" Interrupt registers:\n"); 1057 for (r = schizo_intr_regnames; r->size != 0; ++r) 1058 for (i = 0; i <= r->n_reg; i += r->size) { 1059 if ((!sc->sc_tomatillo && 1060 !(r->type & REG_TYPE_SCHIZO)) || 1061 (sc->sc_tomatillo && 1062 !(r->type & REG_TYPE_TOMATILLO))) 1063 continue; 1064 reg = schizo_pbm_readintr(pbm, r->offset + i); 1065 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1066 " (%s", r->offset + i, reg, r->name); 1067 if (r->n_reg) 1068 printf(" %d)\n", i / r->size); 1069 else 1070 printf(")\n"); 1071 } 1072 } 1073 1074 if (what & 0x40 && sc->sc_tomatillo) { 1075 printf(" I-chip registers:\n"); 1076 for (r = tomatillo_ichip_regnames; r->size != 0; ++r) 1077 for (i = 0; i <= r->n_reg; i += r->size) { 1078 if ((sc->sc_tomatillo && 1079 !(r->type & REG_TYPE_TOMATILLO))) 1080 continue; 1081 reg = tomatillo_pbm_readichip(pbm, 1082 r->offset + i); 1083 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1084 " (%s", r->offset + i, reg, r->name); 1085 if (r->n_reg) 1086 printf(" %d)\n", i / r->size); 1087 else 1088 printf(")\n"); 1089 } 1090 } 1091 } 1092 #endif 1093
Indexes created Tue Sep 30 20:09:53 GMT 2025