schizo.c revision 1.45
1 /* $NetBSD: schizo.c,v 1.45 2021/05/10 23:53:44 thorpej Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * Copyright (c) 2008, 2009, 2010, 2012 Matthew R. Green 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.45 2021/05/10 23:53:44 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/kmem.h> 40 #include <sys/malloc.h> 41 #include <sys/systm.h> 42 #include <sys/time.h> 43 #include <sys/reboot.h> 44 45 #define _SPARC_BUS_DMA_PRIVATE 46 #include <sys/bus.h> 47 #include <machine/autoconf.h> 48 #include <machine/psl.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/dev/iommuvar.h> 55 #include <sparc64/dev/schizoreg.h> 56 #include <sparc64/dev/schizovar.h> 57 #include <sparc64/sparc64/cache.h> 58 59 #ifdef DEBUG 60 #define SDB_PROM 0x01 61 #define SDB_BUSMAP 0x02 62 #define SDB_INTR 0x04 63 #define SDB_INTMAP 0x08 64 #define SDB_CONF 0x10 65 int schizo_debug = 0x0; 66 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 67 #else 68 #define DPRINTF(l, s) 69 #endif 70 71 extern struct sparc_pci_chipset _sparc_pci_chipset; 72 73 static int schizo_match(device_t, cfdata_t, void *); 74 static void schizo_attach(device_t, device_t, void *); 75 static int schizo_print(void *aux, const char *p); 76 77 #ifdef DEBUG 78 void schizo_print_regs(int unit, int what); 79 #endif 80 81 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc), 82 schizo_match, schizo_attach, NULL, NULL); 83 84 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 85 86 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 87 int (*handler)(void *), void *, int, const char *); 88 int schizo_ue(void *); 89 int schizo_ce(void *); 90 int schizo_safari_error(void *); 91 int schizo_pci_error(void *); 92 93 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 94 pci_chipset_tag_t); 95 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 96 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 97 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 98 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 99 int); 100 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 101 102 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 103 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 104 105 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 106 int flags, vaddr_t unused, bus_space_handle_t *hp); 107 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 108 off_t off, int prot, int flags); 109 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 110 void *, void(*)(void)); 111 static int schizo_pci_intr_map(const struct pci_attach_args *, 112 pci_intr_handle_t *); 113 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 114 int, int (*)(void *), void *); 115 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 116 bus_size_t, int, bus_dmamap_t *); 117 118 int 119 schizo_match(device_t parent, cfdata_t match, void *aux) 120 { 121 struct mainbus_attach_args *ma = aux; 122 char *str; 123 124 if (strcmp(ma->ma_name, "pci") != 0) 125 return (0); 126 127 str = prom_getpropstring(ma->ma_node, "model"); 128 if (strcmp(str, "schizo") == 0) 129 return (1); 130 131 str = prom_getpropstring(ma->ma_node, "compatible"); 132 if (strcmp(str, "pci108e,8001") == 0) 133 return (1); 134 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 135 return (1); 136 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 137 return (1); 138 139 return (0); 140 } 141 142 void 143 schizo_attach(device_t parent, device_t self, void *aux) 144 { 145 struct schizo_softc *sc = device_private(self); 146 struct mainbus_attach_args *ma = aux; 147 struct schizo_pbm *pbm; 148 struct iommu_state *is; 149 struct pcibus_attach_args pba; 150 uint64_t reg, eccctrl, ino_bitmap; 151 int *busranges = NULL, nranges, *ino_bitmaps = NULL, nbitmaps; 152 char *str; 153 bool no_sc; 154 155 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr); 156 str = prom_getpropstring(ma->ma_node, "compatible"); 157 if (strcmp(str, "pci108e,a801") == 0) 158 sc->sc_tomatillo = 1; 159 160 sc->sc_dev = self; 161 sc->sc_node = ma->ma_node; 162 sc->sc_dmat = ma->ma_dmatag; 163 sc->sc_bustag = ma->ma_bustag; 164 165 sc->sc_ver = prom_getpropint(sc->sc_node, "version#", 0); 166 167 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL, 168 sizeof(struct schizo_regs), 0, 169 &sc->sc_ctrlh)) { 170 aprint_error(": failed to map registers\n"); 171 return; 172 } 173 174 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 175 176 /* enable schizo ecc error interrupts */ 177 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 178 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 179 SCZ_ECCCTRL_UE_INTEN | 180 SCZ_ECCCTRL_CE_INTEN; 181 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 182 183 pbm = kmem_zalloc(sizeof(*pbm), KM_SLEEP); 184 #ifdef DEBUG 185 sc->sc_pbm = pbm; 186 #endif 187 pbm->sp_sc = sc; 188 pbm->sp_regt = sc->sc_bustag; 189 190 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 191 pbm->sp_bus_a = 1; 192 else 193 pbm->sp_bus_a = 0; 194 195 /* 196 * Map interrupt registers 197 */ 198 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr, 199 ma->ma_reg[0].ur_len, 200 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) { 201 aprint_error(": failed to map interrupt registers\n"); 202 kmem_free(pbm, sizeof(*pbm)); 203 return; 204 } 205 206 #ifdef DEBUG 207 /* 208 * Map ichip registers 209 */ 210 if (sc->sc_tomatillo) 211 if (bus_space_map(sc->sc_bustag, ma->ma_reg[3].ur_paddr, 212 ma->ma_reg[3].ur_len, 213 BUS_SPACE_MAP_LINEAR, &pbm->sp_ichiph)) { 214 aprint_error(": failed to map ichip registers\n"); 215 kmem_free(pbm, sizeof(*pbm)); 216 return; 217 } 218 #endif 219 220 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 221 &pbm->sp_nrange, (void **)&pbm->sp_range)) 222 panic("schizo: can't get ranges"); 223 224 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 225 (void **)&busranges)) 226 panic("schizo: can't get bus-range"); 227 228 aprint_normal(": %s, version %d, ign %x, bus %c %d to %d\n", 229 sc->sc_tomatillo ? "Tomatillo" : "Schizo", sc->sc_ver, 230 sc->sc_ign, pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 231 aprint_naive("\n"); 232 233 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 234 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 235 offsetof(struct schizo_regs, pbm_b), 236 sizeof(struct schizo_pbm_regs), 237 &pbm->sp_regh)) { 238 panic("schizo: unable to create PBM handle"); 239 } 240 241 is = &pbm->sp_is; 242 pbm->sp_sb.sb_is = is; 243 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0; 244 if (no_sc) 245 aprint_debug_dev(sc->sc_dev, "no streaming buffers\n"); 246 else { 247 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40]; 248 249 /* 250 * Initialize the strbuf_ctl. 251 * 252 * The flush sync buffer must be 64-byte aligned. 253 */ 254 is->is_sb[0] = &pbm->sp_sb; 255 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 256 257 bus_space_subregion(pbm->sp_regt, pbm->sp_regh, 258 offsetof(struct schizo_pbm_regs, strbuf), 259 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb); 260 } 261 262 aprint_normal_dev(sc->sc_dev, " "); 263 if (sc->sc_tomatillo) 264 is->is_flags |= IOMMU_SYNC_BEFORE_UNMAP; 265 schizo_init_iommu(sc, pbm); 266 267 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 268 pbm->sp_iot = schizo_alloc_io_tag(pbm); 269 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 270 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 271 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 272 (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0); 273 274 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 275 panic("schizo: could not map config space"); 276 277 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 278 &_sparc_pci_chipset); 279 pbm->sp_pc->spc_busmax = busranges[1]; 280 pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode), 281 KM_SLEEP); 282 283 pba.pba_bus = busranges[0]; 284 pba.pba_bridgetag = NULL; 285 pba.pba_pc = pbm->sp_pc; 286 pba.pba_flags = pbm->sp_flags; 287 pba.pba_dmat = pbm->sp_dmat; 288 pba.pba_dmat64 = NULL; /* XXX */ 289 pba.pba_memt = pbm->sp_memt; 290 pba.pba_iot = pbm->sp_iot; 291 292 free(busranges, M_DEVBUF); 293 294 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 295 296 /* clear out the bus errors */ 297 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 298 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 299 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 300 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 301 302 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 303 /* enable/disable error interrupts and arbiter */ 304 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT; 305 if (sc->sc_tomatillo) { 306 reg &= ~SCZ_PCICTRL_SBH_INT; 307 reg |= TOM_PCICTRL_ARB; 308 reg |= TOM_PCICTRL_PRM | TOM_PCICTRL_PRO | 309 TOM_PCICTRL_PRL; 310 if (sc->sc_ver <= 1) /* 2.0 */ 311 reg |= TOM_PCICTRL_DTO_INT; 312 else 313 reg |= SCZ_PCICTRL_PTO; 314 } else 315 reg |= SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_ARB; 316 if (OF_getproplen(sc->sc_node, "no-bus-parking") < 0) 317 reg |= SCZ_PCICTRL_PARK; 318 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 319 320 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 321 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 322 SCZ_PCIDIAG_D_INTSYNC); 323 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 324 325 if (prom_getprop(sc->sc_node, "ino-bitmap", sizeof(int), &nbitmaps, 326 (void **)&ino_bitmaps)) { 327 /* No property - set defaults (double map UE, CE, SERR). */ 328 if (pbm->sp_bus_a) 329 ino_bitmap = __BIT(SCZ_PCIERR_A_INO); 330 else 331 ino_bitmap = __BIT(SCZ_PCIERR_B_INO); 332 ino_bitmap |= __BIT(SCZ_UE_INO) | __BIT(SCZ_CE_INO) | 333 __BIT(SCZ_SERR_INO); 334 } else 335 ino_bitmap = (uint64_t) ino_bitmaps[1] << 32 | ino_bitmaps[0]; 336 DPRINTF(SDB_INTR, ("ino_bitmap=0x%016" PRIx64 "\n", ino_bitmap)); 337 338 if (ino_bitmap & __BIT(SCZ_PCIERR_A_INO)) 339 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 340 pbm, SCZ_PCIERR_A_INO, "pci_a"); 341 if (ino_bitmap & __BIT(SCZ_PCIERR_B_INO)) 342 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 343 pbm, SCZ_PCIERR_B_INO, "pci_b"); 344 if (ino_bitmap & __BIT(SCZ_UE_INO)) 345 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 346 "ue"); 347 if (ino_bitmap & __BIT(SCZ_CE_INO)) 348 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 349 "ce"); 350 if (ino_bitmap & __BIT(SCZ_SERR_INO)) 351 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 352 SCZ_SERR_INO, "safari"); 353 354 if (sc->sc_tomatillo) { 355 /* 356 * Enable the IOCACHE. 357 */ 358 uint64_t iocache_csr; 359 360 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN | 361 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) | 362 TOM_IOCACHE_CSR_PEN_RDM | 363 TOM_IOCACHE_CSR_PEN_ONE | 364 TOM_IOCACHE_CSR_PEN_LINE; 365 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr); 366 } 367 368 config_found(sc->sc_dev, &pba, schizo_print, 369 CFARG_DEVHANDLE, prom_node_to_devhandle(sc->sc_node), 370 CFARG_EOL); 371 } 372 373 int 374 schizo_ue(void *vsc) 375 { 376 struct schizo_softc *sc = vsc; 377 378 panic("%s: uncorrectable error", device_xname(sc->sc_dev)); 379 return (1); 380 } 381 382 int 383 schizo_ce(void *vsc) 384 { 385 struct schizo_softc *sc = vsc; 386 387 panic("%s: correctable error", device_xname(sc->sc_dev)); 388 return (1); 389 } 390 391 int 392 schizo_pci_error(void *vpbm) 393 { 394 struct schizo_pbm *sp = vpbm; 395 struct schizo_softc *sc = sp->sp_sc; 396 u_int64_t afsr, afar, ctrl, tfar; 397 u_int32_t csr; 398 char bits[128]; 399 400 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 401 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 402 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 403 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 404 405 printf("%s: pci bus %c error\n", device_xname(sc->sc_dev), 406 sp->sp_bus_a ? 'A' : 'B'); 407 408 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 409 printf("PCIAFSR=%s\n", bits); 410 printf("PCIAFAR=%" PRIx64 "\n", afar); 411 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 412 printf("PCICTRL=%s\n", bits); 413 #ifdef PCI_COMMAND_STATUS_BITS 414 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 415 printf("PCICSR=%s\n", bits); 416 #endif 417 418 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 419 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 420 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl); 421 422 if ((ctrl & TOM_IOMMU_ERR) == 0) 423 goto clear_error; 424 425 if (sc->sc_tomatillo) { 426 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 427 printf("IOMMUTFAR=%" PRIx64 "\n", tfar); 428 } 429 430 /* These are non-fatal if target abort was signalled. */ 431 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 432 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 433 ctrl & TOM_IOMMU_BADVA_ERR) { 434 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 435 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 436 goto clear_error; 437 } 438 } 439 } 440 441 panic("%s: %s: fatal", __func__, device_xname(sc->sc_dev)); 442 443 clear_error: 444 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 445 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 446 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 447 return (1); 448 } 449 450 int 451 schizo_safari_error(void *vsc) 452 { 453 struct schizo_softc *sc = vsc; 454 455 printf("%s: safari error\n", device_xname(sc->sc_dev)); 456 457 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 458 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR)); 459 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR)); 460 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR)); 461 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR)); 462 463 panic("%s: %s: fatal", __func__, device_xname(sc->sc_dev)); 464 return (1); 465 } 466 467 void 468 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 469 { 470 struct iommu_state *is = &pbm->sp_is; 471 int *vdma = NULL, nitem, tsbsize = 7; 472 u_int32_t iobase = -1; 473 char *name; 474 475 /* punch in our copies */ 476 is->is_bustag = pbm->sp_regt; 477 bus_space_subregion(is->is_bustag, pbm->sp_regh, 478 offsetof(struct schizo_pbm_regs, iommu), 479 sizeof(struct iommureg2), 480 &is->is_iommu); 481 482 /* 483 * Separate the men from the boys. If the `virtual-dma' 484 * property exists, use it. 485 */ 486 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 487 (void **)&vdma)) { 488 /* Damn. Gotta use these values. */ 489 iobase = vdma[0]; 490 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 491 switch (vdma[1]) { 492 TSBCASE(1); 493 TSBCASE(2); 494 TSBCASE(3); 495 TSBCASE(4); 496 TSBCASE(5); 497 TSBCASE(6); 498 TSBCASE(7); 499 default: 500 printf("bogus tsb size %x, using 7\n", vdma[1]); 501 tsbsize = 7; 502 } 503 #undef TSBCASE 504 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 505 free(vdma, M_DEVBUF); 506 } else { 507 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 508 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 509 } 510 511 /* give us a nice name.. */ 512 name = (char *)kmem_alloc(32, KM_SLEEP); 513 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 514 515 iommu_init(name, is, tsbsize, iobase); 516 } 517 518 int 519 schizo_print(void *aux, const char *p) 520 { 521 522 if (p == NULL) 523 return (UNCONF); 524 return (QUIET); 525 } 526 527 pcireg_t 528 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 529 { 530 struct schizo_pbm *sp = pc->cookie; 531 pcireg_t val = (pcireg_t)~0; 532 int s; 533 534 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 535 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 536 s = splhigh(); 537 struct cpu_info *ci = curcpu(); 538 ci->ci_pci_probe = true; 539 membar_Sync(); 540 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 541 PCITAG_OFFSET(tag) + reg); 542 membar_Sync(); 543 if (ci->ci_pci_fault) 544 val = (pcireg_t)~0; 545 ci->ci_pci_probe = ci->ci_pci_fault = false; 546 splx(s); 547 } 548 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 549 return (val); 550 } 551 552 void 553 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 554 { 555 struct schizo_pbm *sp = pc->cookie; 556 557 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 558 (long)tag, reg, (int)data)); 559 560 /* If we don't know it, just punt it. */ 561 if (PCITAG_NODE(tag) == -1) { 562 DPRINTF(SDB_CONF, (" .. bad addr\n")); 563 return; 564 } 565 566 if ((unsigned int)reg >= PCI_CONF_SIZE) 567 return; 568 569 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 570 PCITAG_OFFSET(tag) + reg, data); 571 DPRINTF(SDB_CONF, (" .. done\n")); 572 } 573 574 void 575 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 576 int (*handler)(void *), void *arg, int ino, const char *what) 577 { 578 struct intrhand *ih; 579 u_int64_t mapoff, clroff; 580 uintptr_t intrregs; 581 582 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 583 ino, sc->sc_ign, handler, arg)); 584 585 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 586 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 587 ino |= sc->sc_ign; 588 589 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n", 590 mapoff, clroff)); 591 592 ih = intrhand_alloc(); 593 594 ih->ih_arg = arg; 595 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 596 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff); 597 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff); 598 ih->ih_fun = handler; 599 ih->ih_pil = ipl; 600 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 601 ih->ih_pending = 0; 602 603 intr_establish(ipl, ipl != IPL_VM, ih); 604 605 schizo_pbm_write(pbm, mapoff, 606 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 607 schizo_pbm_write(pbm, clroff, 0); 608 } 609 610 bus_space_tag_t 611 schizo_alloc_mem_tag(struct schizo_pbm *sp) 612 { 613 return (schizo_alloc_bus_tag(sp, "mem", PCI_MEMORY_BUS_SPACE)); 614 } 615 616 bus_space_tag_t 617 schizo_alloc_io_tag(struct schizo_pbm *sp) 618 { 619 return (schizo_alloc_bus_tag(sp, "io", PCI_IO_BUS_SPACE)); 620 } 621 622 bus_space_tag_t 623 schizo_alloc_config_tag(struct schizo_pbm *sp) 624 { 625 return (schizo_alloc_bus_tag(sp, "cfg", PCI_CONFIG_BUS_SPACE)); 626 } 627 628 bus_space_tag_t 629 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 630 { 631 struct schizo_softc *sc = pbm->sp_sc; 632 bus_space_tag_t bt; 633 634 bt = kmem_zalloc(sizeof(*bt), KM_SLEEP); 635 bt->cookie = pbm; 636 bt->parent = sc->sc_bustag; 637 bt->type = type; 638 bt->sparc_bus_map = schizo_bus_map; 639 bt->sparc_bus_mmap = schizo_bus_mmap; 640 bt->sparc_intr_establish = schizo_intr_establish; 641 return (bt); 642 } 643 644 bus_dma_tag_t 645 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 646 { 647 struct schizo_softc *sc = pbm->sp_sc; 648 bus_dma_tag_t dt, pdt = sc->sc_dmat; 649 650 dt = kmem_zalloc(sizeof(*dt), KM_SLEEP); 651 dt->_cookie = pbm; 652 dt->_parent = pdt; 653 #define PCOPY(x) dt->x = pdt->x 654 dt->_dmamap_create = schizo_dmamap_create; 655 PCOPY(_dmamap_destroy); 656 dt->_dmamap_load = iommu_dvmamap_load; 657 PCOPY(_dmamap_load_mbuf); 658 PCOPY(_dmamap_load_uio); 659 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 660 dt->_dmamap_unload = iommu_dvmamap_unload; 661 dt->_dmamap_sync = iommu_dvmamap_sync; 662 dt->_dmamem_alloc = iommu_dvmamem_alloc; 663 dt->_dmamem_free = iommu_dvmamem_free; 664 dt->_dmamem_map = iommu_dvmamem_map; 665 dt->_dmamem_unmap = iommu_dvmamem_unmap; 666 PCOPY(_dmamem_mmap); 667 #undef PCOPY 668 return (dt); 669 } 670 671 pci_chipset_tag_t 672 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 673 { 674 pci_chipset_tag_t npc; 675 676 npc = kmem_alloc(sizeof *npc, KM_SLEEP); 677 memcpy(npc, pc, sizeof *pc); 678 npc->cookie = pbm; 679 npc->rootnode = node; 680 npc->spc_conf_read = schizo_conf_read; 681 npc->spc_conf_write = schizo_conf_write; 682 npc->spc_intr_map = schizo_pci_intr_map; 683 npc->spc_intr_establish = schizo_pci_intr_establish; 684 npc->spc_find_ino = NULL; 685 return (npc); 686 } 687 688 int 689 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 690 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 691 bus_dmamap_t *dmamp) 692 { 693 struct schizo_pbm *pbm = t->_cookie; 694 int error; 695 696 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 697 boundary, flags, dmamp); 698 if (error == 0) 699 (*dmamp)->_dm_cookie = &pbm->sp_sb; 700 return error; 701 } 702 703 static struct schizo_range * 704 get_schizorange(struct schizo_pbm *pbm, int ss) 705 { 706 int i; 707 708 for (i = 0; i < pbm->sp_nrange; i++) { 709 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 710 return (&pbm->sp_range[i]); 711 } 712 /* not found */ 713 return (NULL); 714 } 715 716 int 717 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 718 int flags, vaddr_t unused, bus_space_handle_t *hp) 719 { 720 bus_addr_t paddr; 721 struct schizo_pbm *pbm = t->cookie; 722 struct schizo_softc *sc = pbm->sp_sc; 723 struct schizo_range *sr; 724 int ss; 725 726 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 727 t->type, 728 (unsigned long long)offset, 729 (unsigned long long)size, 730 flags)); 731 732 /* 733 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it 734 * out for now 735 */ 736 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 737 738 ss = sparc_pci_childspace(t->type); 739 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 740 741 sr = get_schizorange(pbm, ss); 742 if (sr != NULL) { 743 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 744 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 745 "space %lx offset %lx paddr %qx\n", 746 __func__, (long)ss, (long)offset, 747 (unsigned long long)paddr)); 748 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 749 flags, 0, hp)); 750 } 751 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 752 return (EINVAL); 753 } 754 755 static paddr_t 756 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 757 int flags) 758 { 759 bus_addr_t offset = paddr; 760 struct schizo_pbm *pbm = t->cookie; 761 struct schizo_softc *sc = pbm->sp_sc; 762 struct schizo_range *sr; 763 int ss; 764 765 /* 766 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it 767 * out for now 768 */ 769 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 770 771 ss = sparc_pci_childspace(t->type); 772 773 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 774 prot, flags, (unsigned long long)paddr)); 775 776 sr = get_schizorange(pbm, ss); 777 if (sr != NULL) { 778 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 779 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 780 "space %lx offset %lx paddr %qx\n", 781 __func__, (long)ss, (long)offset, 782 (unsigned long long)paddr)); 783 return (bus_space_mmap(sc->sc_bustag, paddr, off, 784 prot, flags)); 785 } 786 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 787 return (-1); 788 } 789 790 /* 791 * Set the IGN for this schizo into the handle. 792 */ 793 int 794 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 795 { 796 struct schizo_pbm *pbm = pa->pa_pc->cookie; 797 struct schizo_softc *sc = pbm->sp_sc; 798 799 DPRINTF(SDB_INTMAP, ("IGN %x", *ihp)); 800 *ihp |= sc->sc_ign; 801 DPRINTF(SDB_INTMAP, (" adjusted to %x\n", *ihp)); 802 return (0); 803 } 804 805 static void * 806 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 807 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 808 { 809 struct schizo_pbm *pbm = t->cookie; 810 struct intrhand *ih = NULL; 811 uint64_t mapoff, clroff; 812 uintptr_t intrregs; 813 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 814 int ino; 815 long vec; 816 817 vec = INTVEC(ihandle); 818 ino = INTINO(vec); 819 820 ih = intrhand_alloc(); 821 822 DPRINTF(SDB_INTR, ("\n%s: ihandle %x level %d fn %p arg %p\n", __func__, 823 ihandle, level, handler, arg)); 824 825 if (level == IPL_NONE) 826 level = INTLEV(vec); 827 if (level == IPL_NONE) { 828 printf(": no IPL, setting IPL 2.\n"); 829 level = 2; 830 } 831 832 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 833 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 834 835 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %" 836 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff)); 837 838 ih->ih_ivec = ihandle; 839 840 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh); 841 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff); 842 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff); 843 844 if (INTIGN(vec) == 0) 845 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN; 846 else 847 ino |= vec & INTMAP_IGN; 848 849 /* Register the map and clear intr registers */ 850 ih->ih_map = intrmapptr; 851 ih->ih_clr = intrclrptr; 852 853 ih->ih_fun = handler; 854 ih->ih_arg = arg; 855 ih->ih_pil = level; 856 ih->ih_number = ino; 857 ih->ih_pending = 0; 858 859 DPRINTF(SDB_INTR, ( 860 "; installing handler %p arg %p with inr %x pil %u\n", 861 handler, arg, ino, (u_int)ih->ih_pil)); 862 863 intr_establish(ih->ih_pil, level != IPL_VM, ih); 864 865 /* 866 * Enable the interrupt now we have the handler installed. 867 * Read the current value as we can't change it besides the 868 * valid bit so so make sure only this bit is changed. 869 */ 870 if (intrmapptr) { 871 u_int64_t imap; 872 873 imap = schizo_pbm_readintr(pbm, mapoff); 874 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 875 (unsigned long long)imap)); 876 imap |= INTMAP_V; 877 imap |= (CPU_UPAID << INTMAP_TID_SHIFT); 878 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 879 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 880 (unsigned long long)imap)); 881 schizo_pbm_writeintr(pbm, mapoff, imap); 882 imap = schizo_pbm_readintr(pbm, mapoff); 883 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 884 (unsigned long long)imap)); 885 ih->ih_number |= imap & INTMAP_INR; 886 } 887 if (intrclrptr) { 888 /* set state to IDLE */ 889 schizo_pbm_writeintr(pbm, clroff, 0); 890 } 891 892 return (ih); 893 } 894 895 static void * 896 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 897 int (*func)(void *), void *arg) 898 { 899 void *cookie; 900 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 901 902 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 903 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 904 905 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 906 return (cookie); 907 } 908 909 #ifdef DEBUG 910 void 911 schizo_print_regs(int unit, int what) 912 { 913 device_t dev; 914 struct schizo_softc *sc; 915 struct schizo_pbm *pbm; 916 const struct schizo_regname *r; 917 int i; 918 u_int64_t reg; 919 920 dev = device_find_by_driver_unit("schizo", unit); 921 if (dev == NULL) { 922 printf("Can't find device schizo%d\n", unit); 923 return; 924 } 925 926 if (!what) { 927 printf("0x01: Safari registers\n"); 928 printf("0x02: PCI registers\n"); 929 printf("0x04: Scratch pad registers (Tomatillo only)\n"); 930 printf("0x08: IOMMU registers\n"); 931 printf("0x10: Streaming cache registers (Schizo only)\n"); 932 printf("0x20: Interrupt registers\n"); 933 printf("0x40: I-chip registers (Tomatillo only)\n"); 934 return; 935 } 936 sc = device_private(dev); 937 pbm = sc->sc_pbm; 938 printf("%s (leaf %c) registers:\n", device_xname(sc->sc_dev), 939 pbm->sp_bus_a ? 'A' : 'B'); 940 941 printf(" Safari registers:\n"); 942 if (what & 0x01) { 943 for (r = schizo_regnames; r->size != 0; ++r) 944 for (i = 0; i <= r->n_reg; i += r->size) { 945 if ((!sc->sc_tomatillo && 946 !(r->type & REG_TYPE_SCHIZO)) || 947 (sc->sc_tomatillo && 948 !(r->type & REG_TYPE_TOMATILLO))) 949 continue; 950 switch (r->size) { 951 case 1: 952 reg = schizo_read_1(sc, r->offset + i); 953 break; 954 case 8: 955 /* fallthrough */ 956 default: 957 reg = schizo_read(sc, r->offset + i); 958 break; 959 } 960 printf("0x%06" PRIx64 " = 0x%016" PRIx64 " (%s", 961 r->offset + i, reg, r->name); 962 if (r->n_reg) 963 printf(" %d)\n", i / r->size); 964 else 965 printf(")\n"); 966 } 967 } 968 969 if (what & 0x02) { 970 printf(" PCI registers:\n"); 971 for (r = schizo_pbm_regnames; r->size != 0; ++r) 972 for (i = 0; i <= r->n_reg; i += r->size) { 973 if ((!sc->sc_tomatillo && 974 !(r->type & REG_TYPE_SCHIZO)) || 975 (sc->sc_tomatillo && 976 !(r->type & REG_TYPE_TOMATILLO))) 977 continue; 978 if ((pbm->sp_bus_a && 979 !(r->type & REG_TYPE_LEAF_A)) || 980 (!pbm->sp_bus_a && 981 !(r->type & REG_TYPE_LEAF_B))) 982 continue; 983 reg = schizo_pbm_read(pbm, r->offset + i); 984 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 985 " (%s", r->offset + i, reg, r->name); 986 if (r->n_reg) 987 printf(" %d)\n", i / r->size); 988 else 989 printf(")\n"); 990 } 991 } 992 993 if (what & 0x04 && sc->sc_tomatillo) { 994 printf(" Scratch pad registers:\n"); 995 for (r = tomatillo_scratch_regnames; r->size != 0; ++r) 996 for (i = 0; i <= r->n_reg; i += r->size) { 997 reg = schizo_pbm_read(pbm, r->offset + i); 998 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 999 " (%s", r->offset + i, reg, r->name); 1000 if (r->n_reg) 1001 printf(" %d)\n", i / r->size); 1002 else 1003 printf(")\n"); 1004 } 1005 } 1006 1007 if (what & 0x08) { 1008 printf(" IOMMU registers:\n"); 1009 for (r = schizo_iommu_regnames; r->size != 0; ++r) 1010 for (i = 0; i <= r->n_reg; i += r->size) { 1011 if ((!sc->sc_tomatillo && 1012 !(r->type & REG_TYPE_SCHIZO)) || 1013 (sc->sc_tomatillo && 1014 !(r->type & REG_TYPE_TOMATILLO))) 1015 continue; 1016 reg = schizo_pbm_read(pbm, r->offset + i); 1017 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1018 " (%s", r->offset + i, reg, r->name); 1019 if (r->n_reg) 1020 printf(" %d)\n", i / r->size); 1021 else 1022 printf(")\n"); 1023 } 1024 } 1025 1026 if (what & 0x10 && !sc->sc_tomatillo) { 1027 printf(" Streaming cache registers:\n"); 1028 for (r = schizo_stream_regnames; r->size != 0; ++r) 1029 for (i = 0; i <= r->n_reg; i += r->size) { 1030 reg = schizo_pbm_read(pbm, r->offset + i); 1031 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1032 " (%s", r->offset + i, reg, r->name); 1033 if (r->n_reg) 1034 printf(" %d)\n", i / r->size); 1035 else 1036 printf(")\n"); 1037 } 1038 } 1039 1040 if (what & 0x20) { 1041 printf(" Interrupt registers:\n"); 1042 for (r = schizo_intr_regnames; r->size != 0; ++r) 1043 for (i = 0; i <= r->n_reg; i += r->size) { 1044 if ((!sc->sc_tomatillo && 1045 !(r->type & REG_TYPE_SCHIZO)) || 1046 (sc->sc_tomatillo && 1047 !(r->type & REG_TYPE_TOMATILLO))) 1048 continue; 1049 reg = schizo_pbm_readintr(pbm, r->offset + i); 1050 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1051 " (%s", r->offset + i, reg, r->name); 1052 if (r->n_reg) 1053 printf(" %d)\n", i / r->size); 1054 else 1055 printf(")\n"); 1056 } 1057 } 1058 1059 if (what & 0x40 && sc->sc_tomatillo) { 1060 printf(" I-chip registers:\n"); 1061 for (r = tomatillo_ichip_regnames; r->size != 0; ++r) 1062 for (i = 0; i <= r->n_reg; i += r->size) { 1063 if ((sc->sc_tomatillo && 1064 !(r->type & REG_TYPE_TOMATILLO))) 1065 continue; 1066 reg = tomatillo_pbm_readichip(pbm, 1067 r->offset + i); 1068 printf("0x%06" PRIx64 " = 0x%016" PRIx64 "" 1069 " (%s", r->offset + i, reg, r->name); 1070 if (r->n_reg) 1071 printf(" %d)\n", i / r->size); 1072 else 1073 printf(")\n"); 1074 } 1075 } 1076 } 1077 #endif 1078
Indexes created Tue Sep 30 20:09:53 GMT 2025