schizo.c revision 1.5
1 /* $NetBSD: schizo.c,v 1.5 2008/12/13 08:07:23 mrg Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/extent.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/time.h> 38 #include <sys/reboot.h> 39 40 #define _SPARC_BUS_DMA_PRIVATE 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/psl.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <sparc64/dev/iommureg.h> 49 #include <sparc64/dev/iommuvar.h> 50 #include <sparc64/dev/schizoreg.h> 51 #include <sparc64/dev/schizovar.h> 52 #include <sparc64/sparc64/cache.h> 53 54 #ifdef DEBUG 55 #define SDB_PROM 0x01 56 #define SDB_BUSMAP 0x02 57 #define SDB_INTR 0x04 58 #define SDB_INTMAP 0x08 59 #define SDB_CONF 0x10 60 int schizo_debug = 0x4; 61 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 62 #else 63 #define DPRINTF(l, s) 64 #endif 65 66 extern struct sparc_pci_chipset _sparc_pci_chipset; 67 68 static int schizo_match(struct device *, struct cfdata *, void *); 69 static void schizo_attach(struct device *, struct device *, void *); 70 static int schizo_print(void *aux, const char *p); 71 72 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 73 schizo_match, schizo_attach, NULL, NULL); 74 75 void schizo_init(struct schizo_softc *); 76 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 77 78 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 79 int (*handler)(void *), void *, int, const char *); 80 int schizo_ue(void *); 81 int schizo_ce(void *); 82 int schizo_safari_error(void *); 83 int schizo_pci_error(void *); 84 85 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 86 pci_chipset_tag_t); 87 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 91 int); 92 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 93 94 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 97 int schizo_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 98 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 99 int flags, vaddr_t unused, bus_space_handle_t *hp); 100 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 101 off_t off, int prot, int flags); 102 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 103 void *, void(*)(void)); 104 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 105 int, int (*)(void *), void *); 106 static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 107 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 108 bus_size_t, int, bus_dmamap_t *); 109 110 int 111 schizo_match(struct device *parent, struct cfdata *match, void *aux) 112 { 113 struct mainbus_attach_args *ma = aux; 114 char *str; 115 116 if (strcmp(ma->ma_name, "pci") != 0) 117 return (0); 118 119 str = prom_getpropstring(ma->ma_node, "model"); 120 if (strcmp(str, "schizo") == 0) 121 return (1); 122 123 str = prom_getpropstring(ma->ma_node, "compatible"); 124 if (strcmp(str, "pci108e,8001") == 0) 125 return (1); 126 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 127 return (1); 128 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 129 return (1); 130 131 return (0); 132 } 133 134 void 135 schizo_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct schizo_softc *sc = (struct schizo_softc *)self; 138 struct mainbus_attach_args *ma = aux; 139 uint64_t eccctrl; 140 char *str; 141 142 printf(": addr %lx ", ma->ma_reg[0].ur_paddr); 143 str = prom_getpropstring(ma->ma_node, "compatible"); 144 if (strcmp(str, "pci108e,a801") == 0) 145 sc->sc_tomatillo = 1; 146 147 sc->sc_node = ma->ma_node; 148 sc->sc_dmat = ma->ma_dmatag; 149 sc->sc_bustag = ma->ma_bustag; 150 sc->sc_ctrl = ma->ma_reg[1].ur_paddr - 0x10000UL; 151 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 152 sc->sc_reg0 = ma->ma_reg[0]; 153 154 if (bus_space_map(sc->sc_bustag, sc->sc_ctrl, 155 sizeof(struct schizo_regs), 0, 156 &sc->sc_ctrlh)) { 157 printf(": failed to map registers\n"); 158 return; 159 } 160 161 /* enable schizo ecc error interrupts */ 162 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 163 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 164 SCZ_ECCCTRL_UE_INTEN | 165 SCZ_ECCCTRL_CE_INTEN; 166 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 167 168 schizo_init(sc); 169 } 170 171 void 172 schizo_init(struct schizo_softc *sc) 173 { 174 struct schizo_pbm *pbm; 175 struct pcibus_attach_args pba; 176 int *busranges = NULL, nranges; 177 u_int64_t /*match,*/ reg; 178 179 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 180 if (pbm == NULL) 181 panic("schizo: can't alloc schizo pbm"); 182 183 pbm->sp_sc = sc; 184 pbm->sp_regt = sc->sc_bustag; 185 186 if ((sc->sc_reg0.ur_paddr & 0x00700000) == 0x00600000) 187 pbm->sp_bus_a = 1; 188 else 189 pbm->sp_bus_a = 0; 190 191 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 192 &pbm->sp_nrange, (void **)&pbm->sp_range)) 193 panic("schizo: can't get ranges"); 194 195 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 196 (void **)&busranges)) 197 panic("schizo: can't get bus-range"); 198 199 printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 200 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 201 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 202 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 203 204 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 205 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 206 offsetof(struct schizo_regs, pbm_b), 207 sizeof(struct schizo_pbm_regs), 208 &pbm->sp_regh)) { 209 panic("schizo: unable to create PBM handle"); 210 } 211 212 printf("%s: ", sc->sc_dv.dv_xname); 213 schizo_init_iommu(sc, pbm); 214 215 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 216 pbm->sp_iot = schizo_alloc_io_tag(pbm); 217 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 218 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 219 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 220 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 221 222 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 223 panic("schizo: could not map config space"); 224 225 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 226 &_sparc_pci_chipset); 227 pbm->sp_pc->spc_busmax = busranges[1]; 228 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 229 M_DEVBUF, M_NOWAIT | M_ZERO); 230 if (pbm->sp_pc->spc_busnode == NULL) 231 panic("schizo: malloc busnode"); 232 233 pba.pba_bus = busranges[0]; 234 pba.pba_bridgetag = NULL; 235 pba.pba_pc = pbm->sp_pc; 236 pba.pba_flags = pbm->sp_flags; 237 pba.pba_dmat = pbm->sp_dmat; 238 pba.pba_dmat64 = NULL; /* XXX */ 239 pba.pba_memt = pbm->sp_memt; 240 pba.pba_iot = pbm->sp_iot; 241 242 free(busranges, M_DEVBUF); 243 244 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 245 246 /* clear out the bus errors */ 247 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 248 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 249 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 250 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 251 252 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 253 /* enable/disable error interrupts and arbiter */ 254 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 255 reg &= ~SCZ_PCICTRL_SBH_INT; 256 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 257 258 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 259 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 260 SCZ_PCIDIAG_D_INTSYNC); 261 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 262 263 if (pbm->sp_bus_a) 264 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 265 pbm, SCZ_PCIERR_A_INO, "pci_a"); 266 else 267 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 268 pbm, SCZ_PCIERR_B_INO, "pci_b"); 269 270 /* double mapped */ 271 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 272 "ue"); 273 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 274 "ce"); 275 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 276 SCZ_SERR_INO, "safari"); 277 278 config_found(&sc->sc_dv, &pba, schizo_print); 279 } 280 281 int 282 schizo_ue(void *vsc) 283 { 284 struct schizo_softc *sc = vsc; 285 286 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 287 return (1); 288 } 289 290 int 291 schizo_ce(void *vsc) 292 { 293 struct schizo_softc *sc = vsc; 294 295 panic("%s: correctable error", sc->sc_dv.dv_xname); 296 return (1); 297 } 298 299 int 300 schizo_pci_error(void *vpbm) 301 { 302 struct schizo_pbm *sp = vpbm; 303 struct schizo_softc *sc = sp->sp_sc; 304 u_int64_t afsr, afar, ctrl, tfar; 305 u_int32_t csr; 306 char bits[128]; 307 308 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 309 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 310 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 311 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 312 313 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 314 sp->sp_bus_a ? 'A' : 'B'); 315 316 printf("PCIAFSR=%s\n", bitmask_snprintf(afsr, SCZ_PCIAFSR_BITS, 317 bits, sizeof(bits))); 318 printf("PCIAFAR=%lx\n", afar); 319 printf("PCICTRL=%s\n", bitmask_snprintf(ctrl, SCZ_PCICTRL_BITS, 320 bits, sizeof(bits))); 321 #ifdef PCI_COMMAND_STATUS_BITS 322 printf("PCICSR=%s\n", bitmask_snprintf(csr, PCI_COMMAND_STATUS_BITS, 323 bits, sizeof(bits))); 324 #endif 325 326 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 327 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 328 printf("IOMMUCTRL=%lx\n", ctrl); 329 330 if ((ctrl & TOM_IOMMU_ERR) == 0) 331 goto clear_error; 332 333 if (sc->sc_tomatillo) { 334 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 335 printf("IOMMUTFAR=%lx\n", tfar); 336 } 337 338 /* These are non-fatal if target abort was signalled. */ 339 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 340 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 341 ctrl & TOM_IOMMU_BADVA_ERR) { 342 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 343 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 344 goto clear_error; 345 } 346 } 347 } 348 349 panic("%s: fatal", sc->sc_dv.dv_xname); 350 351 clear_error: 352 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 353 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 354 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 355 return (1); 356 } 357 358 int 359 schizo_safari_error(void *vsc) 360 { 361 struct schizo_softc *sc = vsc; 362 363 printf("%s: safari error\n", sc->sc_dv.dv_xname); 364 365 printf("ERRLOG=%lx\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 366 printf("UE_AFSR=%lx\n", schizo_read(sc, SCZ_UE_AFSR)); 367 printf("UE_AFAR=%lx\n", schizo_read(sc, SCZ_UE_AFAR)); 368 printf("CE_AFSR=%lx\n", schizo_read(sc, SCZ_CE_AFSR)); 369 printf("CE_AFAR=%lx\n", schizo_read(sc, SCZ_CE_AFAR)); 370 371 panic("%s: fatal", sc->sc_dv.dv_xname); 372 return (1); 373 } 374 375 void 376 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 377 { 378 struct iommu_state *is = &pbm->sp_is; 379 int *vdma = NULL, nitem, tsbsize = 7; 380 u_int32_t iobase = -1; 381 vaddr_t va; 382 char *name; 383 384 va = (vaddr_t)pbm->sp_flush[0x40]; 385 386 /* punch in our copies */ 387 is->is_bustag = pbm->sp_regt; 388 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 389 offsetof(struct schizo_pbm_regs, iommu), 390 sizeof(struct schizo_iommureg), &is->is_iommu)) { 391 printf("schizo: unable to create streaming buffer handle\n"); 392 is->is_sb[0]->sb_flush = NULL; 393 } 394 395 /* initialize our strbuf_ctl */ 396 is->is_sb[0] = &pbm->sp_sb; 397 pbm->sp_sb.sb_is = is; 398 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 399 400 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 401 offsetof(struct schizo_pbm_regs, strbuf), 402 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb)) { 403 } 404 405 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 406 if (name == NULL) 407 panic("couldn't malloc iommu name"); 408 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 409 410 /* 411 * Separate the men from the boys. If the `virtual-dma' 412 * property exists, use it. 413 */ 414 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 415 (void **)&vdma)) { 416 /* Damn. Gotta use these values. */ 417 iobase = vdma[0]; 418 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 419 switch (vdma[1]) { 420 TSBCASE(1); TSBCASE(2); TSBCASE(3); 421 TSBCASE(4); TSBCASE(5); TSBCASE(6); 422 default: 423 printf("bogus tsb size %x, using 7\n", vdma[1]); 424 TSBCASE(7); 425 } 426 #undef TSBCASE 427 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 428 free(vdma, M_DEVBUF); 429 } else { 430 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 431 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 432 } 433 434 iommu_init(name, is, tsbsize, iobase); 435 } 436 437 int 438 schizo_print(void *aux, const char *p) 439 { 440 441 if (p == NULL) 442 return (UNCONF); 443 return (QUIET); 444 } 445 446 pcireg_t 447 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 448 { 449 struct schizo_pbm *sp = pc->cookie; 450 pcireg_t val; 451 452 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 453 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 454 PCITAG_OFFSET(tag) + reg); 455 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 456 return (val); 457 } 458 459 void 460 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 461 { 462 struct schizo_pbm *sp = pc->cookie; 463 464 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 465 (long)tag, reg, (int)data)); 466 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 467 PCITAG_OFFSET(tag) + reg, data); 468 DPRINTF(SDB_CONF, (" .. done\n")); 469 } 470 471 void 472 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 473 int (*handler)(void *), void *arg, int ino, const char *what) 474 { 475 struct intrhand *ih; 476 u_int64_t mapoff, clroff; 477 478 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 479 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 480 ino |= sc->sc_ign; 481 482 ih = (struct intrhand *) 483 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 484 if (ih == NULL) 485 return; 486 ih->ih_arg = arg; 487 ih->ih_map = (uint64_t *)sc->sc_reg0.ur_paddr + mapoff; 488 ih->ih_clr = (uint64_t *)sc->sc_reg0.ur_paddr + clroff; 489 ih->ih_fun = handler; 490 ih->ih_pil = (1<<ipl); 491 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 492 intr_establish(ipl, ipl != IPL_VM, ih); 493 494 schizo_pbm_write(pbm, mapoff, 495 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 496 } 497 498 bus_space_tag_t 499 schizo_alloc_mem_tag(struct schizo_pbm *sp) 500 { 501 return (schizo_alloc_bus_tag(sp, "mem", 502 PCI_MEMORY_BUS_SPACE)); 503 } 504 505 bus_space_tag_t 506 schizo_alloc_io_tag(struct schizo_pbm *sp) 507 { 508 return (schizo_alloc_bus_tag(sp, "io", 509 PCI_IO_BUS_SPACE)); 510 } 511 512 bus_space_tag_t 513 schizo_alloc_config_tag(struct schizo_pbm *sp) 514 { 515 return (schizo_alloc_bus_tag(sp, "cfg", 516 PCI_CONFIG_BUS_SPACE)); 517 } 518 519 bus_space_tag_t 520 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 521 { 522 struct schizo_softc *sc = pbm->sp_sc; 523 bus_space_tag_t bt; 524 525 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 526 M_DEVBUF, M_NOWAIT | M_ZERO); 527 if (bt == NULL) 528 panic("schizo: could not allocate bus tag"); 529 530 bt->cookie = pbm; 531 bt->parent = sc->sc_bustag; 532 bt->type = type; 533 bt->sparc_bus_map = schizo_bus_map; 534 bt->sparc_bus_mmap = schizo_bus_mmap; 535 bt->sparc_intr_establish = schizo_intr_establish; 536 return (bt); 537 } 538 539 bus_dma_tag_t 540 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 541 { 542 struct schizo_softc *sc = pbm->sp_sc; 543 bus_dma_tag_t dt, pdt = sc->sc_dmat; 544 545 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 546 if (dt == NULL) 547 panic("schizo: could not alloc dma tag"); 548 549 dt->_cookie = pbm; 550 dt->_parent = pdt; 551 #define PCOPY(x) dt->x = pdt->x 552 dt->_dmamap_create = schizo_dmamap_create; 553 PCOPY(_dmamap_destroy); 554 dt->_dmamap_load = iommu_dvmamap_load; 555 PCOPY(_dmamap_load_mbuf); 556 PCOPY(_dmamap_load_uio); 557 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 558 dt->_dmamap_unload = iommu_dvmamap_unload; 559 dt->_dmamap_sync = iommu_dvmamap_sync; 560 dt->_dmamem_alloc = iommu_dvmamem_alloc; 561 dt->_dmamem_free = iommu_dvmamem_free; 562 dt->_dmamem_map = iommu_dvmamem_map; 563 dt->_dmamem_unmap = iommu_dvmamem_unmap; 564 PCOPY(_dmamem_mmap); 565 #undef PCOPY 566 return (dt); 567 } 568 569 pci_chipset_tag_t 570 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 571 { 572 pci_chipset_tag_t npc; 573 574 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 575 if (npc == NULL) 576 panic("schizo: could not allocate pci_chipset_tag_t"); 577 memcpy(npc, pc, sizeof *pc); 578 npc->cookie = pbm; 579 npc->rootnode = node; 580 npc->spc_conf_read = schizo_conf_read; 581 npc->spc_conf_write = schizo_conf_write; 582 npc->spc_intr_establish = schizo_pci_intr_establish; 583 npc->spc_find_ino = schizo_pci_find_ino; 584 return (npc); 585 } 586 587 int 588 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 589 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 590 bus_dmamap_t *dmamp) 591 { 592 struct schizo_pbm *pbm = t->_cookie; 593 int error; 594 595 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 596 boundary, flags, dmamp); 597 if (error == 0) 598 (*dmamp)->_dm_cookie = &pbm->sp_sb; 599 return error; 600 } 601 602 static struct schizo_range * 603 get_schizorange(struct schizo_pbm *pbm, int ss) 604 { 605 int i; 606 607 for (i = 0; i < pbm->sp_nrange; i++) { 608 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 609 return (&pbm->sp_range[i]); 610 } 611 /* not found */ 612 return (NULL); 613 } 614 615 int 616 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 617 int flags, vaddr_t unused, bus_space_handle_t *hp) 618 { 619 bus_addr_t paddr; 620 struct schizo_pbm *pbm = t->cookie; 621 struct schizo_softc *sc = pbm->sp_sc; 622 struct schizo_range *sr; 623 int ss; 624 625 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 626 t->type, 627 (unsigned long long)offset, 628 (unsigned long long)size, 629 flags)); 630 631 ss = sparc_pci_childspace(t->type); 632 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 633 634 sr = get_schizorange(pbm, ss); 635 if (sr != NULL) { 636 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 637 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 638 "space %lx offset %lx paddr %qx\n", 639 __func__, (long)ss, (long)offset, 640 (unsigned long long)paddr)); 641 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 642 flags, 0, hp)); 643 } 644 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 645 return (EINVAL); 646 } 647 648 static paddr_t 649 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 650 int flags) 651 { 652 bus_addr_t offset = paddr; 653 struct schizo_pbm *pbm = t->cookie; 654 struct schizo_softc *sc = pbm->sp_sc; 655 struct schizo_range *sr; 656 int ss; 657 658 ss = sparc_pci_childspace(t->type); 659 660 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 661 prot, flags, (unsigned long long)paddr)); 662 663 sr = get_schizorange(pbm, ss); 664 if (sr != NULL) { 665 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 666 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 667 "space %lx offset %lx paddr %qx\n", 668 __func__, (long)ss, (long)offset, 669 (unsigned long long)paddr)); 670 return (bus_space_mmap(sc->sc_bustag, paddr, off, 671 prot, flags)); 672 } 673 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 674 return (-1); 675 } 676 677 static void * 678 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 679 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 680 { 681 struct schizo_pbm *pbm = t->cookie; 682 struct schizo_softc *sc = pbm->sp_sc; 683 struct intrhand *ih = NULL; 684 u_int64_t mapoff, clroff; 685 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 686 int ino; 687 long vec; 688 689 vec = INTVEC(ihandle); 690 ino = INTINO(vec); 691 692 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 693 if (ih == NULL) 694 return (NULL); 695 696 DPRINTF(SDB_INTR, ("%s: ihandle %d level %d fn %p arg %p\n", __func__, 697 ihandle, level, handler, arg)); 698 699 if (level == IPL_NONE) 700 level = INTLEV(vec); 701 if (level == IPL_NONE) { 702 printf(": no IPL, setting IPL 2.\n"); 703 level = 2; 704 } 705 706 DPRINTF(SDB_INTR, ("\n%s: intr %lx: %p\nHunting for IRQ...\n", 707 __func__, (long)ino, intrlev[ino])); 708 709 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 710 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 711 712 intrmapptr = (uint64_t *)sc->sc_reg0.ur_paddr + mapoff; 713 intrclrptr = (uint64_t *)sc->sc_reg0.ur_paddr + clroff; 714 if (INTIGN(vec) == 0) 715 ino |= schizo_pbm_read(pbm, mapoff) & INTMAP_IGN; 716 else 717 ino |= vec & INTMAP_IGN; 718 719 /* Register the map and clear intr registers */ 720 ih->ih_map = intrmapptr; 721 ih->ih_clr = intrclrptr; 722 723 ih->ih_fun = handler; 724 ih->ih_arg = arg; 725 ih->ih_pil = level; 726 ih->ih_number = ino | pbm->sp_sc->sc_ign; 727 728 DPRINTF(SDB_INTR, ( 729 "; installing handler %p arg %p with ino %u pil %u\n", 730 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 731 732 intr_establish(ih->ih_pil, level != IPL_VM, ih); 733 734 /* 735 * Enable the interrupt now we have the handler installed. 736 * Read the current value as we can't change it besides the 737 * valid bit so so make sure only this bit is changed. 738 */ 739 if (intrmapptr) { 740 u_int64_t imap; 741 742 imap = schizo_pbm_read(pbm, mapoff); 743 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 744 (unsigned long long)imap)); 745 imap |= INTMAP_V; 746 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 747 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 748 (unsigned long long)imap)); 749 schizo_pbm_write(pbm, mapoff, imap); 750 imap = schizo_pbm_read(pbm, mapoff); 751 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 752 (unsigned long long)imap)); 753 ih->ih_number |= imap & INTMAP_INR; 754 } 755 if (intrclrptr) { 756 /* set state to IDLE */ 757 schizo_pbm_write(pbm, clroff, 0); 758 } 759 760 return (ih); 761 } 762 763 static void * 764 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 765 int (*func)(void *), void *arg) 766 { 767 void *cookie; 768 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 769 770 DPRINTF(SDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 771 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 772 773 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 774 return (cookie); 775 } 776 777 static int 778 schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 779 { 780 #if 0 781 struct schizo_pbm *pbm = pa->pa_pc->cookie; 782 struct schizo_softc *sc = pbm->sp_sc; 783 u_int bus; 784 u_int dev; 785 u_int pin; 786 #endif 787 788 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 789 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 790 (int)PCITAG_DEV(pa->pa_tag), 791 (int)PCITAG_FUN(pa->pa_tag))); 792 DPRINTF(SDB_INTMAP, 793 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 794 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 795 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 796 PCITAG_NODE(pa->pa_intrtag), 797 (int)PCITAG_BUS(pa->pa_intrtag), 798 (int)PCITAG_DEV(pa->pa_intrtag), 799 (int)PCITAG_FUN(pa->pa_intrtag))); 800 801 #if 0 802 bus = (pp->pp_id == PSYCHO_PBM_B); 803 /* 804 * If we are on a ppb, use the devno on the underlying bus when forming 805 * the ivec. 806 */ 807 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 808 dev = PCITAG_DEV(pa->pa_intrtag); 809 else 810 dev = pa->pa_device; 811 dev--; 812 813 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 814 pp->pp_id == PSYCHO_PBM_B) 815 dev--; 816 817 pin = pa->pa_intrpin - 1; 818 DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 819 sc->sc_mode, pp->pp_id, dev, pin)); 820 821 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 822 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 823 #endif 824 825 return (0); 826 } 827
Indexes created Tue Sep 30 20:09:53 GMT 2025