schizo.c revision 1.8
1 /* $NetBSD: schizo.c,v 1.8 2008/12/16 22:35:26 christos Exp $ */ 2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/extent.h> 35 #include <sys/malloc.h> 36 #include <sys/systm.h> 37 #include <sys/time.h> 38 #include <sys/reboot.h> 39 40 #define _SPARC_BUS_DMA_PRIVATE 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/psl.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <sparc64/dev/iommureg.h> 49 #include <sparc64/dev/iommuvar.h> 50 #include <sparc64/dev/schizoreg.h> 51 #include <sparc64/dev/schizovar.h> 52 #include <sparc64/sparc64/cache.h> 53 54 #ifdef DEBUG 55 #define SDB_PROM 0x01 56 #define SDB_BUSMAP 0x02 57 #define SDB_INTR 0x04 58 #define SDB_INTMAP 0x08 59 #define SDB_CONF 0x10 60 int schizo_debug = 0x0; 61 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0) 62 #else 63 #define DPRINTF(l, s) 64 #endif 65 66 extern struct sparc_pci_chipset _sparc_pci_chipset; 67 68 static int schizo_match(struct device *, struct cfdata *, void *); 69 static void schizo_attach(struct device *, struct device *, void *); 70 static int schizo_print(void *aux, const char *p); 71 72 CFATTACH_DECL(schizo, sizeof(struct schizo_softc), 73 schizo_match, schizo_attach, NULL, NULL); 74 75 void schizo_init(struct schizo_softc *); 76 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *); 77 78 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int, 79 int (*handler)(void *), void *, int, const char *); 80 int schizo_ue(void *); 81 int schizo_ce(void *); 82 int schizo_safari_error(void *); 83 int schizo_pci_error(void *); 84 85 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int, 86 pci_chipset_tag_t); 87 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *); 88 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *); 89 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *); 90 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *, 91 int); 92 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *); 93 94 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int); 95 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 96 97 int schizo_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 98 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 99 int flags, vaddr_t unused, bus_space_handle_t *hp); 100 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 101 off_t off, int prot, int flags); 102 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 103 void *, void(*)(void)); 104 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 105 int, int (*)(void *), void *); 106 static int schizo_pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 107 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 108 bus_size_t, int, bus_dmamap_t *); 109 110 int 111 schizo_match(struct device *parent, struct cfdata *match, void *aux) 112 { 113 struct mainbus_attach_args *ma = aux; 114 char *str; 115 116 if (strcmp(ma->ma_name, "pci") != 0) 117 return (0); 118 119 str = prom_getpropstring(ma->ma_node, "model"); 120 if (strcmp(str, "schizo") == 0) 121 return (1); 122 123 str = prom_getpropstring(ma->ma_node, "compatible"); 124 if (strcmp(str, "pci108e,8001") == 0) 125 return (1); 126 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */ 127 return (1); 128 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */ 129 return (1); 130 131 return (0); 132 } 133 134 void 135 schizo_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct schizo_softc *sc = (struct schizo_softc *)self; 138 struct mainbus_attach_args *ma = aux; 139 uint64_t eccctrl, csr; 140 char *str; 141 142 printf(": addr %lx", ma->ma_reg[0].ur_paddr); 143 str = prom_getpropstring(ma->ma_node, "compatible"); 144 if (strcmp(str, "pci108e,a801") == 0) 145 sc->sc_tomatillo = 1; 146 147 sc->sc_node = ma->ma_node; 148 sc->sc_dmat = ma->ma_dmatag; 149 sc->sc_bustag = ma->ma_bustag; 150 sc->sc_ctrl = ma->ma_reg[1].ur_paddr - 0x10000UL; 151 sc->sc_reg0 = ma->ma_reg[0]; 152 153 if (bus_space_map(sc->sc_bustag, sc->sc_ctrl, 154 sizeof(struct schizo_regs), 0, 155 &sc->sc_ctrlh)) { 156 printf(": failed to map registers\n"); 157 return; 158 } 159 160 csr = schizo_read(sc, SCZ_CONTROL_STATUS); 161 sc->sc_ign = ((csr & SCZ_CONTROL_STATUS_AID_MASK) >> 162 SCZ_CONTROL_STATUS_AID_SHIFT); 163 164 /* enable schizo ecc error interrupts */ 165 eccctrl = schizo_read(sc, SCZ_ECCCTRL); 166 eccctrl |= SCZ_ECCCTRL_EE_INTEN | 167 SCZ_ECCCTRL_UE_INTEN | 168 SCZ_ECCCTRL_CE_INTEN; 169 schizo_write(sc, SCZ_ECCCTRL, eccctrl); 170 171 schizo_init(sc); 172 } 173 174 void 175 schizo_init(struct schizo_softc *sc) 176 { 177 struct schizo_pbm *pbm; 178 struct pcibus_attach_args pba; 179 int *busranges = NULL, nranges; 180 u_int64_t /*match,*/ reg; 181 182 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 183 if (pbm == NULL) 184 panic("schizo: can't alloc schizo pbm"); 185 186 pbm->sp_sc = sc; 187 pbm->sp_regt = sc->sc_bustag; 188 189 if ((sc->sc_reg0.ur_paddr & 0x00700000) == 0x00600000) 190 pbm->sp_bus_a = 1; 191 else 192 pbm->sp_bus_a = 0; 193 194 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range), 195 &pbm->sp_nrange, (void **)&pbm->sp_range)) 196 panic("schizo: can't get ranges"); 197 198 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 199 (void **)&busranges)) 200 panic("schizo: can't get bus-range"); 201 202 printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n", 203 sc->sc_tomatillo ? "Tomatillo" : "Schizo", 204 prom_getpropint(sc->sc_node, "version#", 0), sc->sc_ign, 205 pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]); 206 207 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh, 208 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) : 209 offsetof(struct schizo_regs, pbm_b), 210 sizeof(struct schizo_pbm_regs), 211 &pbm->sp_regh)) { 212 panic("schizo: unable to create PBM handle"); 213 } 214 215 printf("%s: ", sc->sc_dv.dv_xname); 216 schizo_init_iommu(sc, pbm); 217 218 pbm->sp_memt = schizo_alloc_mem_tag(pbm); 219 pbm->sp_iot = schizo_alloc_io_tag(pbm); 220 pbm->sp_cfgt = schizo_alloc_config_tag(pbm); 221 pbm->sp_dmat = schizo_alloc_dma_tag(pbm); 222 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 223 (pbm->sp_iot ? PCI_FLAGS_IO_ENABLED : 0); 224 225 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh)) 226 panic("schizo: could not map config space"); 227 228 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node, 229 &_sparc_pci_chipset); 230 pbm->sp_pc->spc_busmax = busranges[1]; 231 pbm->sp_pc->spc_busnode = malloc(sizeof(*pbm->sp_pc->spc_busnode), 232 M_DEVBUF, M_NOWAIT | M_ZERO); 233 if (pbm->sp_pc->spc_busnode == NULL) 234 panic("schizo: malloc busnode"); 235 236 pba.pba_bus = busranges[0]; 237 pba.pba_bridgetag = NULL; 238 pba.pba_pc = pbm->sp_pc; 239 pba.pba_flags = pbm->sp_flags; 240 pba.pba_dmat = pbm->sp_dmat; 241 pba.pba_dmat64 = NULL; /* XXX */ 242 pba.pba_memt = pbm->sp_memt; 243 pba.pba_iot = pbm->sp_iot; 244 245 free(busranges, M_DEVBUF); 246 247 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5); 248 249 /* clear out the bus errors */ 250 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL)); 251 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR)); 252 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG, 253 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG)); 254 255 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL); 256 /* enable/disable error interrupts and arbiter */ 257 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB; 258 reg &= ~SCZ_PCICTRL_SBH_INT; 259 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg); 260 261 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG); 262 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY | 263 SCZ_PCIDIAG_D_INTSYNC); 264 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg); 265 266 if (pbm->sp_bus_a) 267 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 268 pbm, SCZ_PCIERR_A_INO, "pci_a"); 269 else 270 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error, 271 pbm, SCZ_PCIERR_B_INO, "pci_b"); 272 273 /* double mapped */ 274 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO, 275 "ue"); 276 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO, 277 "ce"); 278 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc, 279 SCZ_SERR_INO, "safari"); 280 281 config_found(&sc->sc_dv, &pba, schizo_print); 282 } 283 284 int 285 schizo_ue(void *vsc) 286 { 287 struct schizo_softc *sc = vsc; 288 289 panic("%s: uncorrectable error", sc->sc_dv.dv_xname); 290 return (1); 291 } 292 293 int 294 schizo_ce(void *vsc) 295 { 296 struct schizo_softc *sc = vsc; 297 298 panic("%s: correctable error", sc->sc_dv.dv_xname); 299 return (1); 300 } 301 302 int 303 schizo_pci_error(void *vpbm) 304 { 305 struct schizo_pbm *sp = vpbm; 306 struct schizo_softc *sc = sp->sp_sc; 307 u_int64_t afsr, afar, ctrl, tfar; 308 u_int32_t csr; 309 char bits[128]; 310 311 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR); 312 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR); 313 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL); 314 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG); 315 316 printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname, 317 sp->sp_bus_a ? 'A' : 'B'); 318 319 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr); 320 printf("PCIAFSR=%s\n", bits); 321 printf("PCIAFAR=%lx\n", afar); 322 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl); 323 printf("PCICTRL=%s\n", bits); 324 #ifdef PCI_COMMAND_STATUS_BITS 325 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr); 326 printf("PCICSR=%s\n", bits); 327 #endif 328 329 if (ctrl & SCZ_PCICTRL_MMU_ERR) { 330 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL); 331 printf("IOMMUCTRL=%lx\n", ctrl); 332 333 if ((ctrl & TOM_IOMMU_ERR) == 0) 334 goto clear_error; 335 336 if (sc->sc_tomatillo) { 337 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR); 338 printf("IOMMUTFAR=%lx\n", tfar); 339 } 340 341 /* These are non-fatal if target abort was signalled. */ 342 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR || 343 ctrl & TOM_IOMMU_ILLTSBTBW_ERR || 344 ctrl & TOM_IOMMU_BADVA_ERR) { 345 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) { 346 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl); 347 goto clear_error; 348 } 349 } 350 } 351 352 panic("%s: fatal", sc->sc_dv.dv_xname); 353 354 clear_error: 355 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr); 356 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl); 357 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr); 358 return (1); 359 } 360 361 int 362 schizo_safari_error(void *vsc) 363 { 364 struct schizo_softc *sc = vsc; 365 366 printf("%s: safari error\n", sc->sc_dv.dv_xname); 367 368 printf("ERRLOG=%lx\n", schizo_read(sc, SCZ_SAFARI_ERRLOG)); 369 printf("UE_AFSR=%lx\n", schizo_read(sc, SCZ_UE_AFSR)); 370 printf("UE_AFAR=%lx\n", schizo_read(sc, SCZ_UE_AFAR)); 371 printf("CE_AFSR=%lx\n", schizo_read(sc, SCZ_CE_AFSR)); 372 printf("CE_AFAR=%lx\n", schizo_read(sc, SCZ_CE_AFAR)); 373 374 panic("%s: fatal", sc->sc_dv.dv_xname); 375 return (1); 376 } 377 378 void 379 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm) 380 { 381 struct iommu_state *is = &pbm->sp_is; 382 int *vdma = NULL, nitem, tsbsize = 7; 383 u_int32_t iobase = -1; 384 vaddr_t va; 385 char *name; 386 387 va = (vaddr_t)pbm->sp_flush[0x40]; 388 389 /* punch in our copies */ 390 is->is_bustag = pbm->sp_regt; 391 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 392 offsetof(struct schizo_pbm_regs, iommu), 393 sizeof(struct schizo_iommureg), &is->is_iommu)) { 394 printf("schizo: unable to create streaming buffer handle\n"); 395 is->is_sb[0]->sb_flush = NULL; 396 } 397 398 /* initialize our strbuf_ctl */ 399 is->is_sb[0] = &pbm->sp_sb; 400 pbm->sp_sb.sb_is = is; 401 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f); 402 403 if (bus_space_subregion(is->is_bustag, pbm->sp_regh, 404 offsetof(struct schizo_pbm_regs, strbuf), 405 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb)) { 406 } 407 408 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 409 if (name == NULL) 410 panic("couldn't malloc iommu name"); 411 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 412 413 /* 414 * Separate the men from the boys. If the `virtual-dma' 415 * property exists, use it. 416 */ 417 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 418 (void **)&vdma)) { 419 /* Damn. Gotta use these values. */ 420 iobase = vdma[0]; 421 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 422 switch (vdma[1]) { 423 TSBCASE(1); TSBCASE(2); TSBCASE(3); 424 TSBCASE(4); TSBCASE(5); TSBCASE(6); 425 default: 426 printf("bogus tsb size %x, using 7\n", vdma[1]); 427 TSBCASE(7); 428 } 429 #undef TSBCASE 430 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase)); 431 free(vdma, M_DEVBUF); 432 } else { 433 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, " 434 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 435 } 436 437 iommu_init(name, is, tsbsize, iobase); 438 } 439 440 int 441 schizo_print(void *aux, const char *p) 442 { 443 444 if (p == NULL) 445 return (UNCONF); 446 return (QUIET); 447 } 448 449 pcireg_t 450 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 451 { 452 struct schizo_pbm *sp = pc->cookie; 453 pcireg_t val; 454 455 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 456 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh, 457 PCITAG_OFFSET(tag) + reg); 458 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val)); 459 return (val); 460 } 461 462 void 463 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 464 { 465 struct schizo_pbm *sp = pc->cookie; 466 467 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__, 468 (long)tag, reg, (int)data)); 469 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh, 470 PCITAG_OFFSET(tag) + reg, data); 471 DPRINTF(SDB_CONF, (" .. done\n")); 472 } 473 474 void 475 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl, 476 int (*handler)(void *), void *arg, int ino, const char *what) 477 { 478 struct intrhand *ih; 479 u_int64_t mapoff, clroff; 480 481 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__, 482 ino, sc->sc_ign, handler, arg)); 483 484 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 485 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 486 ino |= (sc->sc_ign << INTMAP_IGN_SHIFT); 487 488 DPRINTF(SDB_INTR, (" mapoff %lx clroff %lx\n", mapoff, clroff)); 489 490 ih = (struct intrhand *) 491 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 492 if (ih == NULL) 493 return; 494 ih->ih_arg = arg; 495 ih->ih_map = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + mapoff); 496 ih->ih_clr = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + clroff); 497 ih->ih_fun = handler; 498 ih->ih_pil = (1<<ipl); 499 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff)); 500 intr_establish(ipl, ipl != IPL_VM, ih); 501 502 schizo_pbm_write(pbm, mapoff, 503 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT)); 504 } 505 506 bus_space_tag_t 507 schizo_alloc_mem_tag(struct schizo_pbm *sp) 508 { 509 return (schizo_alloc_bus_tag(sp, "mem", 510 PCI_MEMORY_BUS_SPACE)); 511 } 512 513 bus_space_tag_t 514 schizo_alloc_io_tag(struct schizo_pbm *sp) 515 { 516 return (schizo_alloc_bus_tag(sp, "io", 517 PCI_IO_BUS_SPACE)); 518 } 519 520 bus_space_tag_t 521 schizo_alloc_config_tag(struct schizo_pbm *sp) 522 { 523 return (schizo_alloc_bus_tag(sp, "cfg", 524 PCI_CONFIG_BUS_SPACE)); 525 } 526 527 bus_space_tag_t 528 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type) 529 { 530 struct schizo_softc *sc = pbm->sp_sc; 531 bus_space_tag_t bt; 532 533 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 534 M_DEVBUF, M_NOWAIT | M_ZERO); 535 if (bt == NULL) 536 panic("schizo: could not allocate bus tag"); 537 538 bt->cookie = pbm; 539 bt->parent = sc->sc_bustag; 540 bt->type = type; 541 bt->sparc_bus_map = schizo_bus_map; 542 bt->sparc_bus_mmap = schizo_bus_mmap; 543 bt->sparc_intr_establish = schizo_intr_establish; 544 return (bt); 545 } 546 547 bus_dma_tag_t 548 schizo_alloc_dma_tag(struct schizo_pbm *pbm) 549 { 550 struct schizo_softc *sc = pbm->sp_sc; 551 bus_dma_tag_t dt, pdt = sc->sc_dmat; 552 553 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 554 if (dt == NULL) 555 panic("schizo: could not alloc dma tag"); 556 557 dt->_cookie = pbm; 558 dt->_parent = pdt; 559 #define PCOPY(x) dt->x = pdt->x 560 dt->_dmamap_create = schizo_dmamap_create; 561 PCOPY(_dmamap_destroy); 562 dt->_dmamap_load = iommu_dvmamap_load; 563 PCOPY(_dmamap_load_mbuf); 564 PCOPY(_dmamap_load_uio); 565 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 566 dt->_dmamap_unload = iommu_dvmamap_unload; 567 dt->_dmamap_sync = iommu_dvmamap_sync; 568 dt->_dmamem_alloc = iommu_dvmamem_alloc; 569 dt->_dmamem_free = iommu_dvmamem_free; 570 dt->_dmamem_map = iommu_dvmamem_map; 571 dt->_dmamem_unmap = iommu_dvmamem_unmap; 572 PCOPY(_dmamem_mmap); 573 #undef PCOPY 574 return (dt); 575 } 576 577 pci_chipset_tag_t 578 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc) 579 { 580 pci_chipset_tag_t npc; 581 582 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 583 if (npc == NULL) 584 panic("schizo: could not allocate pci_chipset_tag_t"); 585 memcpy(npc, pc, sizeof *pc); 586 npc->cookie = pbm; 587 npc->rootnode = node; 588 npc->spc_conf_read = schizo_conf_read; 589 npc->spc_conf_write = schizo_conf_write; 590 npc->spc_intr_establish = schizo_pci_intr_establish; 591 npc->spc_find_ino = schizo_pci_find_ino; 592 return (npc); 593 } 594 595 int 596 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size, 597 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 598 bus_dmamap_t *dmamp) 599 { 600 struct schizo_pbm *pbm = t->_cookie; 601 int error; 602 603 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 604 boundary, flags, dmamp); 605 if (error == 0) 606 (*dmamp)->_dm_cookie = &pbm->sp_sb; 607 return error; 608 } 609 610 static struct schizo_range * 611 get_schizorange(struct schizo_pbm *pbm, int ss) 612 { 613 int i; 614 615 for (i = 0; i < pbm->sp_nrange; i++) { 616 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss) 617 return (&pbm->sp_range[i]); 618 } 619 /* not found */ 620 return (NULL); 621 } 622 623 int 624 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 625 int flags, vaddr_t unused, bus_space_handle_t *hp) 626 { 627 bus_addr_t paddr; 628 struct schizo_pbm *pbm = t->cookie; 629 struct schizo_softc *sc = pbm->sp_sc; 630 struct schizo_range *sr; 631 int ss; 632 633 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d", 634 t->type, 635 (unsigned long long)offset, 636 (unsigned long long)size, 637 flags)); 638 639 ss = sparc_pci_childspace(t->type); 640 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss)); 641 642 sr = get_schizorange(pbm, ss); 643 if (sr != NULL) { 644 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 645 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 646 "space %lx offset %lx paddr %qx\n", 647 __func__, (long)ss, (long)offset, 648 (unsigned long long)paddr)); 649 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 650 flags, 0, hp)); 651 } 652 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 653 return (EINVAL); 654 } 655 656 static paddr_t 657 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 658 int flags) 659 { 660 bus_addr_t offset = paddr; 661 struct schizo_pbm *pbm = t->cookie; 662 struct schizo_softc *sc = pbm->sp_sc; 663 struct schizo_range *sr; 664 int ss; 665 666 ss = sparc_pci_childspace(t->type); 667 668 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n", 669 prot, flags, (unsigned long long)paddr)); 670 671 sr = get_schizorange(pbm, ss); 672 if (sr != NULL) { 673 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset); 674 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr " 675 "space %lx offset %lx paddr %qx\n", 676 __func__, (long)ss, (long)offset, 677 (unsigned long long)paddr)); 678 return (bus_space_mmap(sc->sc_bustag, paddr, off, 679 prot, flags)); 680 } 681 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__)); 682 return (-1); 683 } 684 685 static void * 686 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level, 687 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 688 { 689 struct schizo_pbm *pbm = t->cookie; 690 struct schizo_softc *sc = pbm->sp_sc; 691 struct intrhand *ih = NULL; 692 uint64_t mapoff, clroff; 693 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 694 int ino; 695 long vec; 696 697 vec = INTVEC(ihandle); 698 ino = INTINO(vec); 699 700 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 701 if (ih == NULL) 702 return (NULL); 703 704 DPRINTF(SDB_INTR, ("\n%s: ihandle %d level %d fn %p arg %p\n", __func__, 705 ihandle, level, handler, arg)); 706 707 if (level == IPL_NONE) 708 level = INTLEV(vec); 709 if (level == IPL_NONE) { 710 printf(": no IPL, setting IPL 2.\n"); 711 level = 2; 712 } 713 714 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]); 715 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]); 716 717 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %lx clroff %lx\n", 718 __func__, ino, intrlev[ino], mapoff, clroff)); 719 720 intrmapptr = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + mapoff); 721 intrclrptr = (uint64_t *)((char *)sc->sc_reg0.ur_paddr + clroff); 722 723 if (INTIGN(vec) == 0) 724 ino |= schizo_pbm_read(pbm, mapoff) & INTMAP_IGN; 725 else 726 ino |= vec & INTMAP_IGN; 727 728 /* Register the map and clear intr registers */ 729 ih->ih_map = intrmapptr; 730 ih->ih_clr = intrclrptr; 731 732 ih->ih_fun = handler; 733 ih->ih_arg = arg; 734 ih->ih_pil = level; 735 ih->ih_number = ino; 736 737 DPRINTF(SDB_INTR, ( 738 "; installing handler %p arg %p with inr %x pil %u\n", 739 handler, arg, ino, (u_int)ih->ih_pil)); 740 741 intr_establish(ih->ih_pil, level != IPL_VM, ih); 742 743 /* 744 * Enable the interrupt now we have the handler installed. 745 * Read the current value as we can't change it besides the 746 * valid bit so so make sure only this bit is changed. 747 */ 748 if (intrmapptr) { 749 u_int64_t imap; 750 751 imap = schizo_pbm_read(pbm, mapoff); 752 DPRINTF(SDB_INTR, ("; read intrmap = %016qx", 753 (unsigned long long)imap)); 754 imap |= INTMAP_V; 755 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 756 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n", 757 (unsigned long long)imap)); 758 schizo_pbm_write(pbm, mapoff, imap); 759 imap = schizo_pbm_read(pbm, mapoff); 760 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx", 761 (unsigned long long)imap)); 762 ih->ih_number |= imap & INTMAP_INR; 763 } 764 if (intrclrptr) { 765 /* set state to IDLE */ 766 schizo_pbm_write(pbm, clroff, 0); 767 } 768 769 return (ih); 770 } 771 772 static void * 773 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 774 int (*func)(void *), void *arg) 775 { 776 void *cookie; 777 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie; 778 779 DPRINTF(SDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 780 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg); 781 782 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie)); 783 return (cookie); 784 } 785 786 static int 787 schizo_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 788 { 789 #if 0 790 struct schizo_pbm *pbm = pa->pa_pc->cookie; 791 struct schizo_softc *sc = pbm->sp_sc; 792 u_int bus; 793 u_int dev; 794 u_int pin; 795 #endif 796 797 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 798 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 799 (int)PCITAG_DEV(pa->pa_tag), 800 (int)PCITAG_FUN(pa->pa_tag))); 801 DPRINTF(SDB_INTMAP, 802 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 803 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 804 DPRINTF(SDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 805 PCITAG_NODE(pa->pa_intrtag), 806 (int)PCITAG_BUS(pa->pa_intrtag), 807 (int)PCITAG_DEV(pa->pa_intrtag), 808 (int)PCITAG_FUN(pa->pa_intrtag))); 809 810 #if 0 811 bus = (pp->pp_id == PSYCHO_PBM_B); 812 /* 813 * If we are on a ppb, use the devno on the underlying bus when forming 814 * the ivec. 815 */ 816 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 817 dev = PCITAG_DEV(pa->pa_intrtag); 818 else 819 dev = pa->pa_device; 820 dev--; 821 822 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 823 pp->pp_id == PSYCHO_PBM_B) 824 dev--; 825 826 pin = pa->pa_intrpin - 1; 827 DPRINTF(SDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, pin %d\n", 828 sc->sc_mode, pp->pp_id, dev, pin)); 829 830 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 831 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 832 #endif 833 834 return (0); 835 } 836
Indexes created Tue Sep 30 20:09:53 GMT 2025