schizoreg.h revision 1.3.2.2
1 1.3.2.2 haad /* $NetBSD: schizoreg.h,v 1.3.2.2 2008/12/13 01:13:29 haad Exp $ */ 2 1.3.2.2 haad /* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */ 3 1.3.2.2 haad 4 1.3.2.2 haad /* 5 1.3.2.2 haad * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 1.3.2.2 haad * All rights reserved. 7 1.3.2.2 haad * 8 1.3.2.2 haad * Redistribution and use in source and binary forms, with or without 9 1.3.2.2 haad * modification, are permitted provided that the following conditions 10 1.3.2.2 haad * are met: 11 1.3.2.2 haad * 1. Redistributions of source code must retain the above copyright 12 1.3.2.2 haad * notice, this list of conditions and the following disclaimer. 13 1.3.2.2 haad * 2. Redistributions in binary form must reproduce the above copyright 14 1.3.2.2 haad * notice, this list of conditions and the following disclaimer in the 15 1.3.2.2 haad * documentation and/or other materials provided with the distribution. 16 1.3.2.2 haad * 17 1.3.2.2 haad * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.3.2.2 haad * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 1.3.2.2 haad * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 20 1.3.2.2 haad * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 21 1.3.2.2 haad * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 1.3.2.2 haad * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 1.3.2.2 haad * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.3.2.2 haad * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 1.3.2.2 haad * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 26 1.3.2.2 haad * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 1.3.2.2 haad * POSSIBILITY OF SUCH DAMAGE. 28 1.3.2.2 haad */ 29 1.3.2.2 haad struct schizo_pbm_regs { 30 1.3.2.2 haad volatile u_int64_t _unused1[64]; /* 0x0000 - 0x01ff */ 31 1.3.2.2 haad struct iommureg iommu; /* 0x0200 - 0x03ff */ 32 1.3.2.2 haad volatile u_int64_t _unused2[384]; 33 1.3.2.2 haad volatile u_int64_t imap[64]; 34 1.3.2.2 haad volatile u_int64_t _unused3[64]; 35 1.3.2.2 haad volatile u_int64_t iclr[64]; 36 1.3.2.2 haad volatile u_int64_t _unused4[320]; 37 1.3.2.2 haad volatile u_int64_t ctrl; 38 1.3.2.2 haad volatile u_int64_t __unused0; 39 1.3.2.2 haad volatile u_int64_t afsr; 40 1.3.2.2 haad volatile u_int64_t afar; 41 1.3.2.2 haad volatile u_int64_t _unused5[252]; 42 1.3.2.2 haad struct iommu_strbuf strbuf; 43 1.3.2.2 haad volatile u_int64_t strbuf_ctxflush; 44 1.3.2.2 haad volatile u_int64_t _unused6[4012]; 45 1.3.2.2 haad volatile u_int64_t iommu_tag; 46 1.3.2.2 haad volatile u_int64_t _unused7[15]; 47 1.3.2.2 haad volatile u_int64_t iommu_data; 48 1.3.2.2 haad volatile u_int64_t _unused8[63]; 49 1.3.2.2 haad volatile u_int64_t istat[2]; 50 1.3.2.2 haad volatile u_int64_t _unused9[2814]; 51 1.3.2.2 haad volatile u_int64_t strbuf_ctxmatch; 52 1.3.2.2 haad volatile u_int64_t _unused10[122879]; 53 1.3.2.2 haad }; 54 1.3.2.2 haad 55 1.3.2.2 haad struct schizo_regs { 56 1.3.2.2 haad volatile u_int64_t _unused0[8]; 57 1.3.2.2 haad volatile u_int64_t pcia_mem_match; 58 1.3.2.2 haad volatile u_int64_t pcia_mem_mask; 59 1.3.2.2 haad volatile u_int64_t pcia_io_match; 60 1.3.2.2 haad volatile u_int64_t pcia_io_mask; 61 1.3.2.2 haad volatile u_int64_t pcib_mem_match; 62 1.3.2.2 haad volatile u_int64_t pcib_mem_mask; 63 1.3.2.2 haad volatile u_int64_t pcib_io_match; 64 1.3.2.2 haad volatile u_int64_t pcib_io_mask; 65 1.3.2.2 haad volatile u_int64_t _unused1[8176]; 66 1.3.2.2 haad 67 1.3.2.2 haad volatile u_int64_t control_status; 68 1.3.2.2 haad volatile u_int64_t error_control; 69 1.3.2.2 haad volatile u_int64_t interrupt_control; 70 1.3.2.2 haad volatile u_int64_t safari_errlog; 71 1.3.2.2 haad volatile u_int64_t eccctrl; 72 1.3.2.2 haad volatile u_int64_t _unused3[1]; 73 1.3.2.2 haad volatile u_int64_t ue_afsr; 74 1.3.2.2 haad volatile u_int64_t ue_afar; 75 1.3.2.2 haad volatile u_int64_t ce_afsr; 76 1.3.2.2 haad volatile u_int64_t ce_afar; 77 1.3.2.2 haad 78 1.3.2.2 haad volatile u_int64_t _unused4[253942]; 79 1.3.2.2 haad struct schizo_pbm_regs pbm_a; 80 1.3.2.2 haad struct schizo_pbm_regs pbm_b; 81 1.3.2.2 haad }; 82 1.3.2.2 haad 83 1.3.2.2 haad //#define SCZ_PCIA_MEM_MATCH 0x00040 84 1.3.2.2 haad //#define SCZ_PCIA_MEM_MASK 0x00048 85 1.3.2.2 haad //#define SCZ_PCIA_IO_MATCH 0x00050 86 1.3.2.2 haad //#define SCZ_PCIA_IO_MASK 0x00058 87 1.3.2.2 haad //#define SCZ_PCIB_MEM_MATCH 0x00060 88 1.3.2.2 haad //#define SCZ_PCIB_MEM_MASK 0x00068 89 1.3.2.2 haad //#define SCZ_PCIB_IO_MATCH 0x00070 90 1.3.2.2 haad //#define SCZ_PCIB_IO_MASK 0x00078 91 1.3.2.2 haad #define SCZ_CONTROL_STATUS 0x10000 92 1.3.2.2 haad #define SCZ_SAFARI_INTCTRL 0x10010 93 1.3.2.2 haad #define SCZ_SAFARI_ERRLOG 0x10018 94 1.3.2.2 haad #define SCZ_ECCCTRL 0x10020 95 1.3.2.2 haad #define SCZ_UE_AFSR 0x10030 96 1.3.2.2 haad #define SCZ_UE_AFAR 0x10038 97 1.3.2.2 haad #define SCZ_CE_AFSR 0x10040 98 1.3.2.2 haad #define SCZ_CE_AFAR 0x10048 99 1.3.2.2 haad 100 1.3.2.2 haad /* These are relative to the PBM */ 101 1.3.2.2 haad #define SCZ_PCI_IOMMU_CTRL 0x00200 102 1.3.2.2 haad #define SCZ_PCI_IOMMU_TSBBASE 0x00208 103 1.3.2.2 haad #define SCZ_PCI_IOMMU_FLUSH 0x00210 104 1.3.2.2 haad #define SCZ_PCI_IOMMU_CTXFLUSH 0x00218 105 1.3.2.2 haad #define TOM_PCI_IOMMU_TFAR 0x00220 106 1.3.2.2 haad #define SCZ_PCI_IMAP_BASE 0x01000 107 1.3.2.2 haad #define SCZ_PCI_ICLR_BASE 0x01400 108 1.3.2.2 haad #define SCZ_PCI_INTR_RETRY 0x01a00 /* interrupt retry */ 109 1.3.2.2 haad #define SCZ_PCI_DMA_FLUSH 0x01a08 /* pci consistent dma flush */ 110 1.3.2.2 haad #define SCZ_PCI_CTRL 0x02000 111 1.3.2.2 haad #define SCZ_PCI_AFSR 0x02010 112 1.3.2.2 haad #define SCZ_PCI_AFAR 0x02018 113 1.3.2.2 haad #define SCZ_PCI_DIAG 0x02020 114 1.3.2.2 haad #define SCZ_PCI_ESTAR 0x02028 115 1.3.2.2 haad #define SCZ_PCI_STRBUF_CTRL 0x02800 116 1.3.2.2 haad #define SCZ_PCI_STRBUF_FLUSH 0x02808 117 1.3.2.2 haad #define SCZ_PCI_STRBUF_FSYNC 0x02810 118 1.3.2.2 haad #define SCZ_PCI_STRBUF_CTXFLUSH 0x02818 119 1.3.2.2 haad #define SCZ_PCI_IOMMU_TAG 0x0a580 120 1.3.2.2 haad #define SCZ_PCI_IOMMU_DATA 0x0a600 121 1.3.2.2 haad #define SCZ_PCI_STRBUF_CTXMATCH 0x10000 122 1.3.2.2 haad 123 1.3.2.2 haad #define SCZ_ECCCTRL_EE_INTEN 0x8000000000000000UL 124 1.3.2.2 haad #define SCZ_ECCCTRL_UE_INTEN 0x4000000000000000UL 125 1.3.2.2 haad #define SCZ_ECCCTRL_CE_INTEN 0x2000000000000000UL 126 1.3.2.2 haad 127 1.3.2.2 haad #define SCZ_UEAFSR_PPIO 0x8000000000000000UL 128 1.3.2.2 haad #define SCZ_UEAFSR_PDRD 0x4000000000000000UL 129 1.3.2.2 haad #define SCZ_UEAFSR_PDWR 0x2000000000000000UL 130 1.3.2.2 haad #define SCZ_UEAFSR_SPIO 0x1000000000000000UL 131 1.3.2.2 haad #define SCZ_UEAFSR_SDMA 0x0800000000000000UL 132 1.3.2.2 haad #define SCZ_UEAFSR_ERRPNDG 0x0300000000000000UL 133 1.3.2.2 haad #define SCZ_UEAFSR_BMSK 0x000003ff00000000UL 134 1.3.2.2 haad #define SCZ_UEAFSR_QOFF 0x00000000c0000000UL 135 1.3.2.2 haad #define SCZ_UEAFSR_AID 0x000000001f000000UL 136 1.3.2.2 haad #define SCZ_UEAFSR_PARTIAL 0x0000000000800000UL 137 1.3.2.2 haad #define SCZ_UEAFSR_OWNEDIN 0x0000000000400000UL 138 1.3.2.2 haad #define SCZ_UEAFSR_MTAGSYND 0x00000000000f0000UL 139 1.3.2.2 haad #define SCZ_UEAFSR_MTAG 0x000000000000e000UL 140 1.3.2.2 haad #define SCZ_UEAFSR_ECCSYND 0x00000000000001ffUL 141 1.3.2.2 haad 142 1.3.2.2 haad #define SCZ_UEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 143 1.3.2.2 haad #define SCZ_UEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 144 1.3.2.2 haad #define SCZ_UEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 145 1.3.2.2 haad #define SZC_UEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 146 1.3.2.2 haad #define SCZ_UEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 147 1.3.2.2 haad #define SCZ_UEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 148 1.3.2.2 haad #define SCZ_UEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 149 1.3.2.2 haad #define SCZ_UEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 150 1.3.2.2 haad #define SCZ_UEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 151 1.3.2.2 haad #define SZC_UEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 152 1.3.2.2 haad #define SZC_UEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 153 1.3.2.2 haad #define SZC_UEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 154 1.3.2.2 haad #define SCZ_UEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 155 1.3.2.2 haad #define SCZ_UEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 156 1.3.2.2 haad 157 1.3.2.2 haad #define SCZ_CEAFSR_PPIO 0x8000000000000000UL 158 1.3.2.2 haad #define SCZ_CEAFSR_PDRD 0x4000000000000000UL 159 1.3.2.2 haad #define SCZ_CEAFSR_PDWR 0x2000000000000000UL 160 1.3.2.2 haad #define SCZ_CEAFSR_SPIO 0x1000000000000000UL 161 1.3.2.2 haad #define SCZ_CEAFSR_SDMA 0x0800000000000000UL 162 1.3.2.2 haad #define SCZ_CEAFSR_ERRPNDG 0x0300000000000000UL 163 1.3.2.2 haad #define SCZ_CEAFSR_BMSK 0x000003ff00000000UL 164 1.3.2.2 haad #define SCZ_CEAFSR_QOFF 0x00000000c0000000UL 165 1.3.2.2 haad #define SCZ_CEAFSR_AID 0x000000001f000000UL 166 1.3.2.2 haad #define SCZ_CEAFSR_PARTIAL 0x0000000000800000UL 167 1.3.2.2 haad #define SCZ_CEAFSR_OWNEDIN 0x0000000000400000UL 168 1.3.2.2 haad #define SCZ_CEAFSR_MTAGSYND 0x00000000000f0000UL 169 1.3.2.2 haad #define SCZ_CEAFSR_MTAG 0x000000000000e000UL 170 1.3.2.2 haad #define SCZ_CEAFSR_ECCSYND 0x00000000000001ffUL 171 1.3.2.2 haad 172 1.3.2.2 haad #define SCZ_CEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 173 1.3.2.2 haad #define SCZ_CEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 174 1.3.2.2 haad #define SCZ_CEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 175 1.3.2.2 haad #define SZC_CEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 176 1.3.2.2 haad #define SCZ_CEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 177 1.3.2.2 haad #define SCZ_CEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 178 1.3.2.2 haad #define SCZ_CEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 179 1.3.2.2 haad #define SCZ_CEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 180 1.3.2.2 haad #define SCZ_CEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 181 1.3.2.2 haad #define SZC_CEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 182 1.3.2.2 haad #define SZC_CEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 183 1.3.2.2 haad #define SZC_CEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 184 1.3.2.2 haad #define SCZ_CEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 185 1.3.2.2 haad #define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 186 1.3.2.2 haad 187 1.3.2.2 haad #define SCZ_PCICTRL_BUS_UNUS (1UL << 63UL) /* bus unusable */ 188 1.3.2.2 haad #define TOM_PCICTRL_DTO_ERR (1UL << 62UL) /* pci discard timeout */ 189 1.3.2.2 haad #define TOM_PCICTRL_DTO_INT (1UL << 61UL) /* discard intr en */ 190 1.3.2.2 haad #define SCZ_PCICTRL_ESLCK (1UL << 51UL) /* error slot locked */ 191 1.3.2.2 haad #define SCZ_PCICTRL_ERRSLOT (7UL << 48UL) /* error slot */ 192 1.3.2.2 haad #define SCZ_PCICTRL_TTO_ERR (1UL << 38UL) /* pci trdy# timeout */ 193 1.3.2.2 haad #define SCZ_PCICTRL_RTRY_ERR (1UL << 37UL) /* pci rtry# timeout */ 194 1.3.2.2 haad #define SCZ_PCICTRL_MMU_ERR (1UL << 36UL) /* pci mmu error */ 195 1.3.2.2 haad #define SCZ_PCICTRL_SBH_ERR (1UL << 35UL) /* pci strm hole */ 196 1.3.2.2 haad #define SCZ_PCICTRL_SERR (1UL << 34UL) /* pci serr# sampled */ 197 1.3.2.2 haad #define SCZ_PCICTRL_PCISPD (1UL << 33UL) /* speed (0=clk/2,1=clk) */ 198 1.3.2.2 haad #define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */ 199 1.3.2.2 haad #define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */ 200 1.3.2.2 haad #define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */ 201 1.3.2.2 haad #define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */ 202 1.3.2.2 haad #define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */ 203 1.3.2.2 haad #define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */ 204 1.3.2.2 haad #define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */ 205 1.3.2.2 haad #define SCZ_PCICTRL_BITS "\20\277UNUS\276DTO\275DTO_INT\263ESLCK\246TTO\245RTRY\244MMU\243SBH\242SERR\241SPD\223MMU_INT\222SBH_INT\221EEN\220PARK\210PCIRST" 206 1.3.2.2 haad 207 1.3.2.2 haad #define SCZ_PCIAFSR_PMA 0x8000000000000000UL 208 1.3.2.2 haad #define SCZ_PCIAFSR_PTA 0x4000000000000000UL 209 1.3.2.2 haad #define SCZ_PCIAFSR_PRTRY 0x2000000000000000UL 210 1.3.2.2 haad #define SCZ_PCIAFSR_PPERR 0x1000000000000000UL 211 1.3.2.2 haad #define SCZ_PCIAFSR_PTTO 0x0800000000000000UL 212 1.3.2.2 haad #define SCZ_PCIAFSR_PUNUS 0x0400000000000000UL 213 1.3.2.2 haad #define SCZ_PCIAFSR_SMA 0x0200000000000000UL 214 1.3.2.2 haad #define SCZ_PCIAFSR_STA 0x0100000000000000UL 215 1.3.2.2 haad #define SCZ_PCIAFSR_SRTRY 0x0080000000000000UL 216 1.3.2.2 haad #define SCZ_PCIAFSR_SPERR 0x0040000000000000UL 217 1.3.2.2 haad #define SCZ_PCIAFSR_STTO 0x0020000000000000UL 218 1.3.2.2 haad #define SCZ_PCIAFSR_SUNUS 0x0010000000000000UL 219 1.3.2.2 haad #define SCZ_PCIAFSR_BMSK 0x000003ff00000000UL 220 1.3.2.2 haad #define SCZ_PCIAFSR_BLK 0x0000000080000000UL 221 1.3.2.2 haad #define SCZ_PCIAFSR_CFG 0x0000000040000000UL 222 1.3.2.2 haad #define SCZ_PCIAFSR_MEM 0x0000000020000000UL 223 1.3.2.2 haad #define SCZ_PCIAFSR_IO 0x0000000010000000UL 224 1.3.2.2 haad 225 1.3.2.2 haad #define SCZ_PCIAFSR_BITS "\20\277PMA\276PTA\275PRTRY\274PPERR\273PTTO\272PUNUS\271SMA\270STA\267SRTRY\266SPERR\265STTO\264SUNUS\237BLK\236CFG\235MEM\234IO" 226 1.3.2.2 haad 227 1.3.2.2 haad #define SCZ_PCIDIAG_D_BADECC (1UL << 10UL) /* disable bad ecc */ 228 1.3.2.2 haad #define SCZ_PCIDIAG_D_BYPASS (1UL << 9UL) /* disable mmu bypass */ 229 1.3.2.2 haad #define SCZ_PCIDIAG_D_TTO (1UL << 8UL) /* disable trdy# timeout */ 230 1.3.2.2 haad #define SCZ_PCIDIAG_D_RTRYARB (1UL << 7UL) /* disable retry arb */ 231 1.3.2.2 haad #define SCZ_PCIDIAG_D_RETRY (1UL << 6UL) /* disable retry lim */ 232 1.3.2.2 haad #define SCZ_PCIDIAG_D_INTSYNC (1UL << 5UL) /* disable write sync */ 233 1.3.2.2 haad #define SCZ_PCIDIAG_I_DMADPAR (1UL << 3UL) /* invert dma parity */ 234 1.3.2.2 haad #define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */ 235 1.3.2.2 haad #define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */ 236 1.3.2.2 haad 237 1.3.2.2 haad #define TOM_IOMMU_ERR (1UL << 24) 238 1.3.2.2 haad #define TOM_IOMMU_ERR_MASK (3UL << 25) 239 1.3.2.2 haad #define TOM_IOMMU_PROT_ERR (0UL << 25) 240 1.3.2.2 haad #define TOM_IOMMU_INV_ERR (1UL << 25) 241 1.3.2.2 haad #define TOM_IOMMU_TO_ERR (2UL << 25) 242 1.3.2.2 haad #define TOM_IOMMU_ECC_ERR (3UL << 25) 243 1.3.2.2 haad #define TOM_IOMMU_ILLTSBTBW_ERR (1UL << 27) 244 1.3.2.2 haad #define TOM_IOMMU_BADVA_ERR (1UL << 28) 245 1.3.2.2 haad 246 1.3.2.2 haad #define SCZ_PBM_A_REGS (0x600000UL - 0x400000UL) 247 1.3.2.2 haad #define SCZ_PBM_B_REGS (0x700000UL - 0x400000UL) 248 1.3.2.2 haad 249 1.3.2.2 haad #define SCZ_UE_INO 0x30 /* uncorrectable error */ 250 1.3.2.2 haad #define SCZ_CE_INO 0x31 /* correctable ecc error */ 251 1.3.2.2 haad #define SCZ_PCIERR_A_INO 0x32 /* PCI A bus error */ 252 1.3.2.2 haad #define SCZ_PCIERR_B_INO 0x33 /* PCI B bus error */ 253 1.3.2.2 haad #define SCZ_SERR_INO 0x34 /* safari interface error */ 254 1.3.2.2 haad 255 1.3.2.2 haad struct schizo_range { 256 1.3.2.2 haad u_int32_t cspace; 257 1.3.2.2 haad u_int32_t child_hi; 258 1.3.2.2 haad u_int32_t child_lo; 259 1.3.2.2 haad u_int32_t phys_hi; 260 1.3.2.2 haad u_int32_t phys_lo; 261 1.3.2.2 haad u_int32_t size_hi; 262 1.3.2.2 haad u_int32_t size_lo; 263 1.3.2.2 haad }; 264
Indexes created Thu Oct 30 16:09:53 GMT 2025