schizoreg.h revision 1.5.4.2
1 /* $NetBSD: schizoreg.h,v 1.5.4.2 2009/01/19 13:16:47 skrll Exp $ */ 2 /* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 20 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 26 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* XXX merge with iommureg.h */ 31 /* iommmu registers */ 32 struct schizo_iommureg { 33 volatile u_int64_t iommu_cr; /* IOMMU control register */ 34 volatile u_int64_t iommu_tsb; /* IOMMU TSB base register */ 35 volatile u_int64_t iommu_flush; /* IOMMU flush register */ 36 volatile u_int64_t iommu_ctxflush; 37 volatile u_int64_t iommu_reserved[28]; 38 volatile u_int64_t iommu_cache_flush; 39 volatile u_int64_t iommu_cache_invalidate; 40 volatile u_int64_t iommu_reserved2[30]; 41 }; 42 43 struct schizo_pbm_regs { 44 volatile u_int64_t _unused1[64]; /* 0x0000 - 0x01ff */ 45 struct schizo_iommureg iommu; /* 0x0200 - 0x03ff */ 46 volatile u_int64_t _unused2[384]; 47 volatile u_int64_t imap[64]; 48 volatile u_int64_t _unused3[64]; 49 volatile u_int64_t iclr[64]; 50 volatile u_int64_t _unused4[320]; 51 volatile u_int64_t ctrl; 52 volatile u_int64_t __unused0; 53 volatile u_int64_t afsr; 54 volatile u_int64_t afar; 55 volatile u_int64_t _unused5[252]; 56 struct iommu_strbuf strbuf; 57 volatile u_int64_t strbuf_ctxflush; 58 volatile u_int64_t _unused6[4012]; 59 volatile u_int64_t iommu_tag; 60 volatile u_int64_t _unused7[15]; 61 volatile u_int64_t iommu_data; 62 volatile u_int64_t _unused8[63]; 63 volatile u_int64_t istat[2]; 64 volatile u_int64_t _unused9[2814]; 65 volatile u_int64_t strbuf_ctxmatch; 66 volatile u_int64_t _unused10[122879]; 67 }; 68 69 struct schizo_regs { 70 volatile u_int64_t _unused0[8]; 71 volatile u_int64_t pcia_mem_match; 72 volatile u_int64_t pcia_mem_mask; 73 volatile u_int64_t pcia_io_match; 74 volatile u_int64_t pcia_io_mask; 75 volatile u_int64_t pcib_mem_match; 76 volatile u_int64_t pcib_mem_mask; 77 volatile u_int64_t pcib_io_match; 78 volatile u_int64_t pcib_io_mask; 79 volatile u_int64_t _unused1[8176]; 80 81 volatile u_int64_t control_status; 82 volatile u_int64_t error_control; 83 volatile u_int64_t interrupt_control; 84 volatile u_int64_t safari_errlog; 85 volatile u_int64_t eccctrl; 86 volatile u_int64_t _unused3[1]; 87 volatile u_int64_t ue_afsr; 88 volatile u_int64_t ue_afar; 89 volatile u_int64_t ce_afsr; 90 volatile u_int64_t ce_afar; 91 92 volatile u_int64_t _unused4[253942]; 93 struct schizo_pbm_regs pbm_a; 94 struct schizo_pbm_regs pbm_b; 95 }; 96 97 #define SCZ_PCIA_MEM_MATCH 0x00040 98 #define SCZ_PCIA_MEM_MASK 0x00048 99 #define SCZ_PCIA_IO_MATCH 0x00050 100 #define SCZ_PCIA_IO_MASK 0x00058 101 #define SCZ_PCIB_MEM_MATCH 0x00060 102 #define SCZ_PCIB_MEM_MASK 0x00068 103 #define SCZ_PCIB_IO_MATCH 0x00070 104 #define SCZ_PCIB_IO_MASK 0x00078 105 106 #define SCZ_CONTROL_STATUS 0x10000 107 # define SCZ_CONTROL_STATUS_AID_MASK 0x1f00000 108 # define SCZ_CONTROL_STATUS_AID_SHIFT 20 109 #define SCZ_SAFARI_INTCTRL 0x10010 110 #define SCZ_SAFARI_ERRLOG 0x10018 111 #define SCZ_ECCCTRL 0x10020 112 #define SCZ_UE_AFSR 0x10030 113 #define SCZ_UE_AFAR 0x10038 114 #define SCZ_CE_AFSR 0x10040 115 #define SCZ_CE_AFAR 0x10048 116 117 /* These are relative to the PBM */ 118 #define SCZ_PCI_IOMMU_CTRL 0x00200 119 #define SCZ_PCI_IOMMU_TSBBASE 0x00208 120 #define SCZ_PCI_IOMMU_FLUSH 0x00210 121 #define SCZ_PCI_IOMMU_CTXFLUSH 0x00218 122 #define TOM_PCI_IOMMU_TFAR 0x00220 123 #define SCZ_PCI_IMAP_BASE 0x01000 124 #define SCZ_PCI_ICLR_BASE 0x01400 125 #define SCZ_PCI_INTR_RETRY 0x01a00 /* interrupt retry */ 126 #define SCZ_PCI_DMA_FLUSH 0x01a08 /* pci consistent dma flush */ 127 #define SCZ_PCI_CTRL 0x02000 128 #define SCZ_PCI_AFSR 0x02010 129 #define SCZ_PCI_AFAR 0x02018 130 #define SCZ_PCI_DIAG 0x02020 131 #define SCZ_PCI_ESTAR 0x02028 132 #define SCZ_PCI_STRBUF_CTRL 0x02800 133 #define SCZ_PCI_STRBUF_FLUSH 0x02808 134 #define SCZ_PCI_STRBUF_FSYNC 0x02810 135 #define SCZ_PCI_STRBUF_CTXFLUSH 0x02818 136 #define SCZ_PCI_IOMMU_TAG 0x0a580 137 #define SCZ_PCI_IOMMU_DATA 0x0a600 138 #define SCZ_PCI_STRBUF_CTXMATCH 0x10000 139 140 #define SCZ_ECCCTRL_EE_INTEN 0x8000000000000000UL 141 #define SCZ_ECCCTRL_UE_INTEN 0x4000000000000000UL 142 #define SCZ_ECCCTRL_CE_INTEN 0x2000000000000000UL 143 144 #define SCZ_UEAFSR_PPIO 0x8000000000000000UL 145 #define SCZ_UEAFSR_PDRD 0x4000000000000000UL 146 #define SCZ_UEAFSR_PDWR 0x2000000000000000UL 147 #define SCZ_UEAFSR_SPIO 0x1000000000000000UL 148 #define SCZ_UEAFSR_SDMA 0x0800000000000000UL 149 #define SCZ_UEAFSR_ERRPNDG 0x0300000000000000UL 150 #define SCZ_UEAFSR_BMSK 0x000003ff00000000UL 151 #define SCZ_UEAFSR_QOFF 0x00000000c0000000UL 152 #define SCZ_UEAFSR_AID 0x000000001f000000UL 153 #define SCZ_UEAFSR_PARTIAL 0x0000000000800000UL 154 #define SCZ_UEAFSR_OWNEDIN 0x0000000000400000UL 155 #define SCZ_UEAFSR_MTAGSYND 0x00000000000f0000UL 156 #define SCZ_UEAFSR_MTAG 0x000000000000e000UL 157 #define SCZ_UEAFSR_ECCSYND 0x00000000000001ffUL 158 159 #define SCZ_UEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 160 #define SCZ_UEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 161 #define SCZ_UEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 162 #define SZC_UEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 163 #define SCZ_UEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 164 #define SCZ_UEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 165 #define SCZ_UEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 166 #define SCZ_UEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 167 #define SCZ_UEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 168 #define SZC_UEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 169 #define SZC_UEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 170 #define SZC_UEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 171 #define SCZ_UEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 172 #define SCZ_UEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 173 174 #define SCZ_CEAFSR_PPIO 0x8000000000000000UL 175 #define SCZ_CEAFSR_PDRD 0x4000000000000000UL 176 #define SCZ_CEAFSR_PDWR 0x2000000000000000UL 177 #define SCZ_CEAFSR_SPIO 0x1000000000000000UL 178 #define SCZ_CEAFSR_SDMA 0x0800000000000000UL 179 #define SCZ_CEAFSR_ERRPNDG 0x0300000000000000UL 180 #define SCZ_CEAFSR_BMSK 0x000003ff00000000UL 181 #define SCZ_CEAFSR_QOFF 0x00000000c0000000UL 182 #define SCZ_CEAFSR_AID 0x000000001f000000UL 183 #define SCZ_CEAFSR_PARTIAL 0x0000000000800000UL 184 #define SCZ_CEAFSR_OWNEDIN 0x0000000000400000UL 185 #define SCZ_CEAFSR_MTAGSYND 0x00000000000f0000UL 186 #define SCZ_CEAFSR_MTAG 0x000000000000e000UL 187 #define SCZ_CEAFSR_ECCSYND 0x00000000000001ffUL 188 189 #define SCZ_CEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 190 #define SCZ_CEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 191 #define SCZ_CEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 192 #define SZC_CEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 193 #define SCZ_CEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 194 #define SCZ_CEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 195 #define SCZ_CEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 196 #define SCZ_CEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 197 #define SCZ_CEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 198 #define SZC_CEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 199 #define SZC_CEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 200 #define SZC_CEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 201 #define SCZ_CEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 202 #define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 203 204 #define SCZ_PCICTRL_BUS_UNUS (1UL << 63UL) /* bus unusable */ 205 #define TOM_PCICTRL_DTO_ERR (1UL << 62UL) /* pci discard timeout */ 206 #define TOM_PCICTRL_DTO_INT (1UL << 61UL) /* discard intr en */ 207 #define SCZ_PCICTRL_ESLCK (1UL << 51UL) /* error slot locked */ 208 #define SCZ_PCICTRL_ERRSLOT (7UL << 48UL) /* error slot */ 209 #define SCZ_PCICTRL_TTO_ERR (1UL << 38UL) /* pci trdy# timeout */ 210 #define SCZ_PCICTRL_RTRY_ERR (1UL << 37UL) /* pci rtry# timeout */ 211 #define SCZ_PCICTRL_MMU_ERR (1UL << 36UL) /* pci mmu error */ 212 #define SCZ_PCICTRL_SBH_ERR (1UL << 35UL) /* pci strm hole */ 213 #define SCZ_PCICTRL_SERR (1UL << 34UL) /* pci serr# sampled */ 214 #define SCZ_PCICTRL_PCISPD (1UL << 33UL) /* speed (0=clk/2,1=clk) */ 215 #define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */ 216 #define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */ 217 #define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */ 218 #define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */ 219 #define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */ 220 #define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */ 221 #define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */ 222 #define SCZ_PCICTRL_BITS "\20\277UNUS\276DTO\275DTO_INT\263ESLCK\246TTO\245RTRY\244MMU\243SBH\242SERR\241SPD\223MMU_INT\222SBH_INT\221EEN\220PARK\210PCIRST" 223 224 #define SCZ_PCIAFSR_PMA 0x8000000000000000UL 225 #define SCZ_PCIAFSR_PTA 0x4000000000000000UL 226 #define SCZ_PCIAFSR_PRTRY 0x2000000000000000UL 227 #define SCZ_PCIAFSR_PPERR 0x1000000000000000UL 228 #define SCZ_PCIAFSR_PTTO 0x0800000000000000UL 229 #define SCZ_PCIAFSR_PUNUS 0x0400000000000000UL 230 #define SCZ_PCIAFSR_SMA 0x0200000000000000UL 231 #define SCZ_PCIAFSR_STA 0x0100000000000000UL 232 #define SCZ_PCIAFSR_SRTRY 0x0080000000000000UL 233 #define SCZ_PCIAFSR_SPERR 0x0040000000000000UL 234 #define SCZ_PCIAFSR_STTO 0x0020000000000000UL 235 #define SCZ_PCIAFSR_SUNUS 0x0010000000000000UL 236 #define SCZ_PCIAFSR_BMSK 0x000003ff00000000UL 237 #define SCZ_PCIAFSR_BLK 0x0000000080000000UL 238 #define SCZ_PCIAFSR_CFG 0x0000000040000000UL 239 #define SCZ_PCIAFSR_MEM 0x0000000020000000UL 240 #define SCZ_PCIAFSR_IO 0x0000000010000000UL 241 242 #define SCZ_PCIAFSR_BITS "\20\277PMA\276PTA\275PRTRY\274PPERR\273PTTO\272PUNUS\271SMA\270STA\267SRTRY\266SPERR\265STTO\264SUNUS\237BLK\236CFG\235MEM\234IO" 243 244 #define SCZ_PCIDIAG_D_BADECC (1UL << 10UL) /* disable bad ecc */ 245 #define SCZ_PCIDIAG_D_BYPASS (1UL << 9UL) /* disable mmu bypass */ 246 #define SCZ_PCIDIAG_D_TTO (1UL << 8UL) /* disable trdy# timeout */ 247 #define SCZ_PCIDIAG_D_RTRYARB (1UL << 7UL) /* disable retry arb */ 248 #define SCZ_PCIDIAG_D_RETRY (1UL << 6UL) /* disable retry lim */ 249 #define SCZ_PCIDIAG_D_INTSYNC (1UL << 5UL) /* disable write sync */ 250 #define SCZ_PCIDIAG_I_DMADPAR (1UL << 3UL) /* invert dma parity */ 251 #define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */ 252 #define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */ 253 254 #define TOM_IOMMU_ERR (1UL << 24) 255 #define TOM_IOMMU_ERR_MASK (3UL << 25) 256 #define TOM_IOMMU_PROT_ERR (0UL << 25) 257 #define TOM_IOMMU_INV_ERR (1UL << 25) 258 #define TOM_IOMMU_TO_ERR (2UL << 25) 259 #define TOM_IOMMU_ECC_ERR (3UL << 25) 260 #define TOM_IOMMU_ILLTSBTBW_ERR (1UL << 27) 261 #define TOM_IOMMU_BADVA_ERR (1UL << 28) 262 263 #define SCZ_PBM_A_REGS (0x600000UL - 0x400000UL) 264 #define SCZ_PBM_B_REGS (0x700000UL - 0x400000UL) 265 266 #define SCZ_UE_INO 0x30 /* uncorrectable error */ 267 #define SCZ_CE_INO 0x31 /* correctable ecc error */ 268 #define SCZ_PCIERR_A_INO 0x32 /* PCI A bus error */ 269 #define SCZ_PCIERR_B_INO 0x33 /* PCI B bus error */ 270 #define SCZ_SERR_INO 0x34 /* safari interface error */ 271 272 struct schizo_range { 273 u_int32_t cspace; 274 u_int32_t child_hi; 275 u_int32_t child_lo; 276 u_int32_t phys_hi; 277 u_int32_t phys_lo; 278 u_int32_t size_hi; 279 u_int32_t size_lo; 280 }; 281
Indexes created Tue Oct 28 07:09:57 GMT 2025