schizoreg.h revision 1.7
1 /* $NetBSD: schizoreg.h,v 1.7 2011/01/02 10:43:18 mrg Exp $ */ 2 /* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * Copyright (c) 2010 Matthew R. Green 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* XXX merge with iommureg.h */ 32 /* iommmu registers */ 33 struct schizo_iommureg { 34 volatile u_int64_t iommu_cr; /* IOMMU control register */ 35 volatile u_int64_t iommu_tsb; /* IOMMU TSB base register */ 36 volatile u_int64_t iommu_flush; /* IOMMU flush register */ 37 volatile u_int64_t iommu_ctxflush; 38 volatile u_int64_t iommu_reserved[28]; 39 volatile u_int64_t iommu_cache_flush; 40 volatile u_int64_t iommu_cache_invalidate; 41 volatile u_int64_t iommu_reserved2[30]; 42 }; 43 44 struct schizo_pbm_regs { 45 volatile u_int64_t _unused1[64]; /* 0x0000 - 0x01ff */ 46 struct schizo_iommureg iommu; /* 0x0200 - 0x03ff */ 47 volatile u_int64_t _unused2[384]; 48 volatile u_int64_t imap[64]; 49 volatile u_int64_t _unused3[64]; 50 volatile u_int64_t iclr[64]; 51 volatile u_int64_t _unused4[320]; 52 volatile u_int64_t ctrl; 53 volatile u_int64_t __unused0; 54 volatile u_int64_t afsr; 55 volatile u_int64_t afar; 56 volatile u_int64_t _unused5[252]; 57 struct iommu_strbuf strbuf; 58 volatile u_int64_t strbuf_ctxflush; 59 volatile u_int64_t _unused6[4012]; 60 volatile u_int64_t iommu_tag; 61 volatile u_int64_t _unused7[15]; 62 volatile u_int64_t iommu_data; 63 volatile u_int64_t _unused8[63]; 64 volatile u_int64_t istat[2]; 65 volatile u_int64_t _unused9[2814]; 66 volatile u_int64_t strbuf_ctxmatch; 67 volatile u_int64_t _unused10[122879]; 68 }; 69 70 struct schizo_regs { 71 volatile u_int64_t _unused0[8]; 72 volatile u_int64_t pcia_mem_match; 73 volatile u_int64_t pcia_mem_mask; 74 volatile u_int64_t pcia_io_match; 75 volatile u_int64_t pcia_io_mask; 76 volatile u_int64_t pcib_mem_match; 77 volatile u_int64_t pcib_mem_mask; 78 volatile u_int64_t pcib_io_match; 79 volatile u_int64_t pcib_io_mask; 80 volatile u_int64_t _unused1[8176]; 81 82 volatile u_int64_t control_status; 83 volatile u_int64_t error_control; 84 volatile u_int64_t interrupt_control; 85 volatile u_int64_t safari_errlog; 86 volatile u_int64_t eccctrl; 87 volatile u_int64_t _unused3[1]; 88 volatile u_int64_t ue_afsr; 89 volatile u_int64_t ue_afar; 90 volatile u_int64_t ce_afsr; 91 volatile u_int64_t ce_afar; 92 93 volatile u_int64_t _unused4[253942]; 94 struct schizo_pbm_regs pbm_a; 95 struct schizo_pbm_regs pbm_b; 96 }; 97 98 #define SCZ_PCIA_MEM_MATCH 0x00040 99 #define SCZ_PCIA_MEM_MASK 0x00048 100 #define SCZ_PCIA_IO_MATCH 0x00050 101 #define SCZ_PCIA_IO_MASK 0x00058 102 #define SCZ_PCIB_MEM_MATCH 0x00060 103 #define SCZ_PCIB_MEM_MASK 0x00068 104 #define SCZ_PCIB_IO_MATCH 0x00070 105 #define SCZ_PCIB_IO_MASK 0x00078 106 107 #define SCZ_CONTROL_STATUS 0x10000 108 # define SCZ_CONTROL_STATUS_AID_MASK 0x1f00000 109 # define SCZ_CONTROL_STATUS_AID_SHIFT 20 110 #define SCZ_SAFARI_INTCTRL 0x10010 111 #define SCZ_SAFARI_ERRLOG 0x10018 112 #define SCZ_ECCCTRL 0x10020 113 #define SCZ_UE_AFSR 0x10030 114 #define SCZ_UE_AFAR 0x10038 115 #define SCZ_CE_AFSR 0x10040 116 #define SCZ_CE_AFAR 0x10048 117 118 /* These are relative to the PBM */ 119 #define SCZ_PCI_IOMMU_CTRL 0x00200 120 #define SCZ_PCI_IOMMU_TSBBASE 0x00208 121 #define SCZ_PCI_IOMMU_FLUSH 0x00210 122 #define SCZ_PCI_IOMMU_CTXFLUSH 0x00218 123 #define TOM_PCI_IOMMU_TFAR 0x00220 124 #define SCZ_PCI_IMAP_BASE 0x01000 125 #define SCZ_PCI_ICLR_BASE 0x01400 126 #define SCZ_PCI_INTR_RETRY 0x01a00 /* interrupt retry */ 127 #define SCZ_PCI_DMA_FLUSH 0x01a08 /* pci consistent dma flush */ 128 #define SCZ_PCI_CTRL 0x02000 129 #define SCZ_PCI_AFSR 0x02010 130 #define SCZ_PCI_AFAR 0x02018 131 #define SCZ_PCI_DIAG 0x02020 132 #define SCZ_PCI_ESTAR 0x02028 133 #define SCZ_PCI_IOCACHE_CSR 0x02248 134 #define SCZ_PCI_IOCACHE_TAG_DIAG_BASE 0x02250 135 #define SCZ_PCI_IOCACHE_TAG_DATA_BASE 0x02290 136 #define SCZ_PCI_STRBUF_CTRL 0x02800 137 #define SCZ_PCI_STRBUF_FLUSH 0x02808 138 #define SCZ_PCI_STRBUF_FSYNC 0x02810 139 #define SCZ_PCI_STRBUF_CTXFLUSH 0x02818 140 #define SCZ_PCI_IOMMU_TAG 0x0a580 141 #define SCZ_PCI_IOMMU_DATA 0x0a600 142 #define SCZ_PCI_STRBUF_CTXMATCH 0x10000 143 144 #define SCZ_ECCCTRL_EE_INTEN 0x8000000000000000UL 145 #define SCZ_ECCCTRL_UE_INTEN 0x4000000000000000UL 146 #define SCZ_ECCCTRL_CE_INTEN 0x2000000000000000UL 147 148 #define SCZ_UEAFSR_PPIO 0x8000000000000000UL 149 #define SCZ_UEAFSR_PDRD 0x4000000000000000UL 150 #define SCZ_UEAFSR_PDWR 0x2000000000000000UL 151 #define SCZ_UEAFSR_SPIO 0x1000000000000000UL 152 #define SCZ_UEAFSR_SDMA 0x0800000000000000UL 153 #define SCZ_UEAFSR_ERRPNDG 0x0300000000000000UL 154 #define SCZ_UEAFSR_BMSK 0x000003ff00000000UL 155 #define SCZ_UEAFSR_QOFF 0x00000000c0000000UL 156 #define SCZ_UEAFSR_AID 0x000000001f000000UL 157 #define SCZ_UEAFSR_PARTIAL 0x0000000000800000UL 158 #define SCZ_UEAFSR_OWNEDIN 0x0000000000400000UL 159 #define SCZ_UEAFSR_MTAGSYND 0x00000000000f0000UL 160 #define SCZ_UEAFSR_MTAG 0x000000000000e000UL 161 #define SCZ_UEAFSR_ECCSYND 0x00000000000001ffUL 162 163 #define SCZ_UEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 164 #define SCZ_UEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 165 #define SCZ_UEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 166 #define SZC_UEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 167 #define SCZ_UEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 168 #define SCZ_UEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 169 #define SCZ_UEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 170 #define SCZ_UEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 171 #define SCZ_UEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 172 #define SZC_UEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 173 #define SZC_UEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 174 #define SZC_UEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 175 #define SCZ_UEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 176 #define SCZ_UEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 177 178 #define SCZ_CEAFSR_PPIO 0x8000000000000000UL 179 #define SCZ_CEAFSR_PDRD 0x4000000000000000UL 180 #define SCZ_CEAFSR_PDWR 0x2000000000000000UL 181 #define SCZ_CEAFSR_SPIO 0x1000000000000000UL 182 #define SCZ_CEAFSR_SDMA 0x0800000000000000UL 183 #define SCZ_CEAFSR_ERRPNDG 0x0300000000000000UL 184 #define SCZ_CEAFSR_BMSK 0x000003ff00000000UL 185 #define SCZ_CEAFSR_QOFF 0x00000000c0000000UL 186 #define SCZ_CEAFSR_AID 0x000000001f000000UL 187 #define SCZ_CEAFSR_PARTIAL 0x0000000000800000UL 188 #define SCZ_CEAFSR_OWNEDIN 0x0000000000400000UL 189 #define SCZ_CEAFSR_MTAGSYND 0x00000000000f0000UL 190 #define SCZ_CEAFSR_MTAG 0x000000000000e000UL 191 #define SCZ_CEAFSR_ECCSYND 0x00000000000001ffUL 192 193 #define SCZ_CEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 194 #define SCZ_CEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 195 #define SCZ_CEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 196 #define SZC_CEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 197 #define SCZ_CEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 198 #define SCZ_CEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 199 #define SCZ_CEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 200 #define SCZ_CEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 201 #define SCZ_CEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 202 #define SZC_CEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 203 #define SZC_CEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 204 #define SZC_CEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 205 #define SCZ_CEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 206 #define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 207 208 #define SCZ_PCICTRL_BUS_UNUS (1ULL << 63UL) /* bus unusable */ 209 #define TOM_PCICTRL_DTO_ERR (1ULL << 62UL) /* pci discard timeout */ 210 #define TOM_PCICTRL_DTO_INT (1ULL << 61UL) /* discard intr en */ 211 #define SCZ_PCICTRL_ESLCK (1ULL << 51UL) /* error slot locked */ 212 #define SCZ_PCICTRL_ERRSLOT (7ULL << 48UL) /* error slot */ 213 #define SCZ_PCICTRL_TTO_ERR (1ULL << 38UL) /* pci trdy# timeout */ 214 #define SCZ_PCICTRL_RTRY_ERR (1ULL << 37UL) /* pci rtry# timeout */ 215 #define SCZ_PCICTRL_MMU_ERR (1ULL << 36UL) /* pci mmu error */ 216 #define SCZ_PCICTRL_SBH_ERR (1ULL << 35UL) /* pci strm hole */ 217 #define SCZ_PCICTRL_SERR (1ULL << 34UL) /* pci serr# sampled */ 218 #define SCZ_PCICTRL_PCISPD (1ULL << 33UL) /* speed (0=clk/2,1=clk) */ 219 #define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */ 220 #define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */ 221 #define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */ 222 #define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */ 223 #define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */ 224 #define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */ 225 #define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */ 226 #define SCZ_PCICTRL_BITS "\20\277UNUS\276DTO\275DTO_INT\263ESLCK\246TTO\245RTRY\244MMU\243SBH\242SERR\241SPD\223MMU_INT\222SBH_INT\221EEN\220PARK\210PCIRST" 227 228 #define SCZ_PCIAFSR_PMA 0x8000000000000000UL 229 #define SCZ_PCIAFSR_PTA 0x4000000000000000UL 230 #define SCZ_PCIAFSR_PRTRY 0x2000000000000000UL 231 #define SCZ_PCIAFSR_PPERR 0x1000000000000000UL 232 #define SCZ_PCIAFSR_PTTO 0x0800000000000000UL 233 #define SCZ_PCIAFSR_PUNUS 0x0400000000000000UL 234 #define SCZ_PCIAFSR_SMA 0x0200000000000000UL 235 #define SCZ_PCIAFSR_STA 0x0100000000000000UL 236 #define SCZ_PCIAFSR_SRTRY 0x0080000000000000UL 237 #define SCZ_PCIAFSR_SPERR 0x0040000000000000UL 238 #define SCZ_PCIAFSR_STTO 0x0020000000000000UL 239 #define SCZ_PCIAFSR_SUNUS 0x0010000000000000UL 240 #define SCZ_PCIAFSR_BMSK 0x000003ff00000000UL 241 #define SCZ_PCIAFSR_BLK 0x0000000080000000UL 242 #define SCZ_PCIAFSR_CFG 0x0000000040000000UL 243 #define SCZ_PCIAFSR_MEM 0x0000000020000000UL 244 #define SCZ_PCIAFSR_IO 0x0000000010000000UL 245 246 #define SCZ_PCIAFSR_BITS "\20\277PMA\276PTA\275PRTRY\274PPERR\273PTTO\272PUNUS\271SMA\270STA\267SRTRY\266SPERR\265STTO\264SUNUS\237BLK\236CFG\235MEM\234IO" 247 248 #define SCZ_PCIDIAG_D_BADECC (1UL << 10UL) /* disable bad ecc */ 249 #define SCZ_PCIDIAG_D_BYPASS (1UL << 9UL) /* disable mmu bypass */ 250 #define SCZ_PCIDIAG_D_TTO (1UL << 8UL) /* disable trdy# timeout */ 251 #define SCZ_PCIDIAG_D_RTRYARB (1UL << 7UL) /* disable retry arb */ 252 #define SCZ_PCIDIAG_D_RETRY (1UL << 6UL) /* disable retry lim */ 253 #define SCZ_PCIDIAG_D_INTSYNC (1UL << 5UL) /* disable write sync */ 254 #define SCZ_PCIDIAG_I_DMADPAR (1UL << 3UL) /* invert dma parity */ 255 #define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */ 256 #define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */ 257 258 /* Enable prefetch bits */ 259 #define TOM_IOCACHE_CSR_WRT_PEN (1UL << 19UL) /* for partial line writes */ 260 #define TOM_IOCACHE_CSR_NCP_RDM (1UL << 18UL) /* memory read multiple (NC) */ 261 #define TOM_IOCACHE_CSR_NCP_ONE (1UL << 17UL) /* memory read (NC) */ 262 #define TOM_IOCACHE_CSR_NCP_LINE (1UL << 16UL) /* memory read line (NC) */ 263 #define TOM_IOCACHE_CSR_PEN_RDM (1UL << 2UL) /* memory read multiple */ 264 #define TOM_IOCACHE_CSR_PEN_ONE (1UL << 1UL) /* memory read */ 265 #define TOM_IOCACHE_CSR_PEN_LINE (1UL << 0UL) /* memory read line */ 266 /* Prefetch lines selection 0x0 = 1, 0x3 = 4 */ 267 #define TOM_IOCACHE_CSR_PLEN_RDM_MASK 0x000000000000c000UL /* read multiple */ 268 #define TOM_IOCACHE_CSR_PLEN_RDM_SHIFT 14 269 #define TOM_IOCACHE_CSR_PLEN_ONE_MASK 0x0000000000003000UL /* read one */ 270 #define TOM_IOCACHE_CSR_PLEN_ONE_SHIFT 12 271 #define TOM_IOCACHE_CSR_PLEN_LINE_MASK 0x0000000000000c00UL /* read line */ 272 #define TOM_IOCACHE_CSR_PLEN_LINE_SHIFT 10 273 /* Prefetch offset selection 0x00 = 1, 0x7e = 127, 0x7f = invalid */ 274 #define TOM_IOCACHE_CSR_POFFSET_MASK 0x00000000000003f8UL 275 276 #define TOM_IOCACHE_CSR_BITS "\177\020" \ 277 "b\19WRT_PEN\0b\18NCP_RDM\0b17NCP_ONE\0b\16NCP_LINE\0" \ 278 "f\14\2PLEN_RDM\0f\12\2PEN_ONE\0f\10\2PEN_LINE\0" \ 279 "f\3\7POFFSET\0" \ 280 "b\2PEN_RDM\0b\1PEN_ONE\0b\0PEN_LINE\0\0" 281 282 #define TOM_IOMMU_ERR (1UL << 24) 283 #define TOM_IOMMU_ERR_MASK (3UL << 25) 284 #define TOM_IOMMU_PROT_ERR (0UL << 25) 285 #define TOM_IOMMU_INV_ERR (1UL << 25) 286 #define TOM_IOMMU_TO_ERR (2UL << 25) 287 #define TOM_IOMMU_ECC_ERR (3UL << 25) 288 #define TOM_IOMMU_ILLTSBTBW_ERR (1UL << 27) 289 #define TOM_IOMMU_BADVA_ERR (1UL << 28) 290 291 #define SCZ_PBM_A_REGS (0x600000UL - 0x400000UL) 292 #define SCZ_PBM_B_REGS (0x700000UL - 0x400000UL) 293 294 #define SCZ_UE_INO 0x30 /* uncorrectable error */ 295 #define SCZ_CE_INO 0x31 /* correctable ecc error */ 296 #define SCZ_PCIERR_A_INO 0x32 /* PCI A bus error */ 297 #define SCZ_PCIERR_B_INO 0x33 /* PCI B bus error */ 298 #define SCZ_SERR_INO 0x34 /* safari interface error */ 299 300 struct schizo_range { 301 u_int32_t cspace; 302 u_int32_t child_hi; 303 u_int32_t child_lo; 304 u_int32_t phys_hi; 305 u_int32_t phys_lo; 306 u_int32_t size_hi; 307 u_int32_t size_lo; 308 }; 309
Indexes created Tue Oct 28 12:10:06 GMT 2025