vpci.c revision 1.7 1 1.7 palle /* $NetBSD: vpci.c,v 1.7 2016/05/10 19:23:59 palle Exp $ */
2 1.1 palle /*
3 1.1 palle * Copyright (c) 2015 Palle Lyckegaard
4 1.1 palle * All rights reserved.
5 1.1 palle *
6 1.1 palle * Driver for virtual PCIe host bridge on sun4v systems.
7 1.1 palle *
8 1.1 palle * Based on NetBSD pyro and OpenBSD vpci drivers.
9 1.1 palle *
10 1.1 palle * Redistribution and use in source and binary forms, with or without
11 1.1 palle * modification, are permitted provided that the following conditions
12 1.1 palle * are met:
13 1.1 palle * 1. Redistributions of source code must retain the above copyright
14 1.1 palle * notice, this list of conditions and the following disclaimer.
15 1.1 palle * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 palle * notice, this list of conditions and the following disclaimer in the
17 1.1 palle * documentation and/or other materials provided with the distribution.
18 1.1 palle *
19 1.1 palle * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 1.1 palle * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 1.1 palle * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 1.1 palle * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 1.1 palle * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 1.1 palle * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 1.1 palle * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 palle * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 1.1 palle * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 1.1 palle * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 palle * POSSIBILITY OF SUCH DAMAGE.
30 1.1 palle */
31 1.1 palle
32 1.1 palle #include <sys/cdefs.h>
33 1.7 palle __KERNEL_RCSID(0, "$NetBSD: vpci.c,v 1.7 2016/05/10 19:23:59 palle Exp $");
34 1.1 palle
35 1.1 palle #include <sys/param.h>
36 1.1 palle #include <sys/device.h>
37 1.1 palle #include <sys/errno.h>
38 1.1 palle #include <sys/malloc.h>
39 1.1 palle #include <sys/systm.h>
40 1.1 palle
41 1.1 palle #define _SPARC_BUS_DMA_PRIVATE
42 1.1 palle #include <sys/bus.h>
43 1.1 palle #include <machine/autoconf.h>
44 1.1 palle
45 1.1 palle #ifdef DDB
46 1.1 palle #include <machine/db_machdep.h>
47 1.1 palle #endif
48 1.1 palle
49 1.1 palle #include <dev/pci/pcivar.h>
50 1.1 palle #include <dev/pci/pcireg.h>
51 1.1 palle
52 1.1 palle #include <sparc64/dev/iommureg.h>
53 1.1 palle #include <sparc64/dev/iommuvar.h>
54 1.1 palle #include <sparc64/dev/vpcivar.h>
55 1.1 palle
56 1.3 nakayama #include <machine/hypervisor.h>
57 1.1 palle
58 1.1 palle #ifdef DEBUG
59 1.2 palle #define VDB_PROM 0x01
60 1.2 palle #define VDB_BUSMAP 0x02
61 1.2 palle #define VDB_INTR 0x04
62 1.2 palle #define VDB_CONF_READ 0x08
63 1.2 palle #define VDB_CONF_WRITE 0x10
64 1.2 palle #define VDB_CONF VDB_CONF_READ|VDB_CONF_WRITE
65 1.2 palle int vpci_debug = 0x00;
66 1.1 palle #define DPRINTF(l, s) do { if (vpci_debug & l) printf s; } while (0)
67 1.1 palle #else
68 1.1 palle #define DPRINTF(l, s)
69 1.1 palle #endif
70 1.1 palle
71 1.1 palle #if 0
72 1.1 palle FIXME
73 1.1 palle #define FIRE_RESET_GEN 0x7010
74 1.1 palle
75 1.1 palle #define FIRE_RESET_GEN_XIR 0x0000000000000002L
76 1.1 palle
77 1.1 palle #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0
78 1.1 palle #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040
79 1.1 palle #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080
80 1.1 palle #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100
81 1.1 palle #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200
82 1.1 palle #define FIRE_INTRMAP_T_JPID_SHIFT 26
83 1.1 palle #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000
84 1.1 palle
85 1.1 palle #define OBERON_INTRMAP_T_DESTID_SHIFT 21
86 1.1 palle #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000
87 1.1 palle #endif
88 1.1 palle
89 1.1 palle extern struct sparc_pci_chipset _sparc_pci_chipset;
90 1.1 palle
91 1.1 palle int vpci_match(device_t, cfdata_t, void *);
92 1.1 palle void vpci_attach(device_t, device_t, void *);
93 1.1 palle int vpci_print(void *, const char *);
94 1.1 palle
95 1.1 palle CFATTACH_DECL_NEW(vpci, sizeof(struct vpci_softc),
96 1.1 palle vpci_match, vpci_attach, NULL, NULL);
97 1.1 palle
98 1.1 palle void vpci_init(struct vpci_softc */*FIXME, int*/, struct mainbus_attach_args *);
99 1.1 palle void vpci_init_iommu(struct vpci_softc *, struct vpci_pbm *);
100 1.1 palle pci_chipset_tag_t vpci_alloc_chipset(struct vpci_pbm *, int,
101 1.1 palle pci_chipset_tag_t);
102 1.1 palle bus_space_tag_t vpci_alloc_mem_tag(struct vpci_pbm *);
103 1.1 palle bus_space_tag_t vpci_alloc_io_tag(struct vpci_pbm *);
104 1.1 palle bus_space_tag_t vpci_alloc_config_tag(struct vpci_pbm *);
105 1.1 palle bus_space_tag_t vpci_alloc_bus_tag(struct vpci_pbm *, const char *, int);
106 1.1 palle bus_dma_tag_t vpci_alloc_dma_tag(struct vpci_pbm *);
107 1.1 palle
108 1.1 palle #if 0
109 1.1 palle int vpci_conf_size(pci_chipset_tag_t, pcitag_t);
110 1.1 palle #endif
111 1.1 palle pcireg_t vpci_conf_read(pci_chipset_tag_t, pcitag_t, int);
112 1.1 palle void vpci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
113 1.1 palle
114 1.1 palle static void * vpci_pci_intr_establish(pci_chipset_tag_t pc,
115 1.1 palle pci_intr_handle_t ih, int level,
116 1.1 palle int (*func)(void *), void *arg);
117 1.7 palle void vpci_intr_ack(struct intrhand *);
118 1.1 palle int vpci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
119 1.1 palle int vpci_bus_map(bus_space_tag_t, bus_addr_t,
120 1.1 palle bus_size_t, int, vaddr_t, bus_space_handle_t *);
121 1.1 palle paddr_t vpci_bus_mmap(bus_space_tag_t, bus_addr_t, off_t,
122 1.1 palle int, int);
123 1.1 palle void *vpci_intr_establish(bus_space_tag_t, int, int,
124 1.1 palle int (*)(void *), void *, void (*)(void));
125 1.1 palle
126 1.1 palle int vpci_dmamap_create(bus_dma_tag_t, bus_size_t, int,
127 1.1 palle bus_size_t, bus_size_t, int, bus_dmamap_t *);
128 1.1 palle
129 1.1 palle int
130 1.1 palle vpci_match(device_t parent, cfdata_t match, void *aux)
131 1.1 palle {
132 1.1 palle struct mainbus_attach_args *ma = aux;
133 1.1 palle char compat[32];
134 1.1 palle
135 1.1 palle if (strcmp(ma->ma_name, "pci") != 0)
136 1.1 palle return (0);
137 1.1 palle
138 1.1 palle if (OF_getprop(ma->ma_node, "compatible", compat, sizeof(compat)) == -1)
139 1.1 palle return (0);
140 1.1 palle
141 1.1 palle if (strcmp(compat, "SUNW,sun4v-pci") == 0)
142 1.1 palle return (1);
143 1.1 palle
144 1.1 palle return (0);
145 1.1 palle }
146 1.1 palle
147 1.1 palle void
148 1.1 palle vpci_attach(device_t parent, device_t self, void *aux)
149 1.1 palle {
150 1.1 palle struct vpci_softc *sc = device_private(self);
151 1.1 palle struct mainbus_attach_args *ma = aux;
152 1.1 palle #if 0
153 1.1 palle FIXME
154 1.1 palle char *str;
155 1.1 palle int busa;
156 1.1 palle #endif
157 1.1 palle sc->sc_dev = self;
158 1.1 palle sc->sc_node = ma->ma_node;
159 1.1 palle sc->sc_dmat = ma->ma_dmatag;
160 1.1 palle sc->sc_bustag = ma->ma_bustag;
161 1.1 palle sc->sc_csr = ma->ma_reg[0].ur_paddr;
162 1.1 palle #if 0
163 1.1 palle FIXME
164 1.1 palle sc->sc_xbc = ma->ma_reg[1].ur_paddr;
165 1.1 palle sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT);
166 1.1 palle
167 1.1 palle if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000)
168 1.1 palle busa = 1;
169 1.1 palle else
170 1.1 palle busa = 0;
171 1.1 palle #endif
172 1.1 palle #if 0
173 1.1 palle FIXME
174 1.1 palle if (bus_space_map(sc->sc_bustag, sc->sc_csr,
175 1.1 palle ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, &sc->sc_csrh)) {
176 1.1 palle printf(": failed to map csr registers\n");
177 1.1 palle return;
178 1.1 palle }
179 1.1 palle #endif
180 1.1 palle #if 0
181 1.1 palle FIXME
182 1.1 palle if (bus_space_map(sc->sc_bustag, sc->sc_xbc,
183 1.1 palle ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) {
184 1.1 palle printf(": failed to map xbc registers\n");
185 1.1 palle return;
186 1.1 palle }
187 1.1 palle
188 1.1 palle str = prom_getpropstring(ma->ma_node, "compatible");
189 1.1 palle if (strcmp(str, "pciex108e,80f8") == 0)
190 1.1 palle sc->sc_oberon = 1;
191 1.1 palle
192 1.1 palle #endif
193 1.1 palle vpci_init(sc/*FIXME, busa*/, ma);
194 1.1 palle }
195 1.1 palle
196 1.1 palle void
197 1.1 palle vpci_init(struct vpci_softc *sc/*FIXME, int busa*/, struct mainbus_attach_args *ma)
198 1.1 palle {
199 1.1 palle struct vpci_pbm *pbm;
200 1.1 palle struct pcibus_attach_args pba;
201 1.1 palle int *busranges = NULL, nranges;
202 1.1 palle
203 1.1 palle pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO);
204 1.1 palle if (pbm == NULL)
205 1.1 palle panic("vpci: can't alloc vpci pbm");
206 1.1 palle
207 1.1 palle pbm->vp_sc = sc;
208 1.1 palle pbm->vp_devhandle = (ma->ma_reg[0].ur_paddr >> 32) & 0x0fffffff;
209 1.1 palle #if 0
210 1.1 palle FiXME
211 1.1 palle pbm->vp_bus_a = busa;
212 1.1 palle #endif
213 1.1 palle
214 1.1 palle if (prom_getprop(sc->sc_node, "ranges", sizeof(struct vpci_range),
215 1.1 palle &pbm->vp_nrange, (void **)&pbm->vp_range))
216 1.1 palle panic("vpci: can't get ranges");
217 1.1 palle for (int range = 0; range < pbm->vp_nrange; range++)
218 1.1 palle DPRINTF(VDB_PROM,
219 1.1 palle ("\nvpci_attach: range %d cspace %08x "
220 1.1 palle "child_hi %08x child_lo %08x phys_hi %08x phys_lo %08x "
221 1.1 palle "size_hi %08x size_lo %08x", range,
222 1.1 palle pbm->vp_range[range].cspace,
223 1.1 palle pbm->vp_range[range].child_hi,
224 1.1 palle pbm->vp_range[range].child_lo,
225 1.1 palle pbm->vp_range[range].phys_hi,
226 1.1 palle pbm->vp_range[range].phys_lo,
227 1.1 palle pbm->vp_range[range].size_hi,
228 1.1 palle pbm->vp_range[range].size_lo));
229 1.1 palle
230 1.1 palle if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges,
231 1.1 palle (void **)&busranges))
232 1.1 palle panic("vpci: can't get bus-range");
233 1.1 palle for (int range = 0; range < nranges; range++)
234 1.1 palle DPRINTF(VDB_PROM, ("\nvpci_attach: bus-range %d %08x", range, busranges[range]));
235 1.2 palle
236 1.4 palle aprint_normal(": bus %d to %d", busranges[0], busranges[1]);
237 1.4 palle
238 1.1 palle vpci_init_iommu(sc, pbm);
239 1.2 palle
240 1.1 palle pbm->vp_memt = vpci_alloc_mem_tag(pbm);
241 1.1 palle pbm->vp_iot = vpci_alloc_io_tag(pbm);
242 1.1 palle pbm->vp_cfgt = vpci_alloc_config_tag(pbm);
243 1.1 palle pbm->vp_dmat = vpci_alloc_dma_tag(pbm);
244 1.1 palle pbm->vp_flags = (pbm->vp_memt ? PCI_FLAGS_MEM_OKAY : 0) |
245 1.1 palle (pbm->vp_iot ? PCI_FLAGS_IO_OKAY : 0);
246 1.1 palle #if 0
247 1.1 palle FIXME
248 1.1 palle if (bus_space_map(pbm->vp_cfgt, 0, 0x10000000, 0, &pbm->vp_cfgh))
249 1.1 palle panic("vpci: can't map config space");
250 1.1 palle #endif
251 1.1 palle pbm->vp_pc = vpci_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset);
252 1.1 palle pbm->vp_pc->spc_busmax = busranges[1];
253 1.1 palle pbm->vp_pc->spc_busnode = malloc(sizeof(*pbm->vp_pc->spc_busnode),
254 1.1 palle M_DEVBUF, M_NOWAIT | M_ZERO);
255 1.1 palle if (pbm->vp_pc->spc_busnode == NULL)
256 1.1 palle panic("vpci: malloc busnode");
257 1.1 palle
258 1.1 palle #if 0
259 1.1 palle pbm->vp_pc->bustag = pbm->vp_cfgt;
260 1.1 palle pbm->vp_pc->bushandle = pbm->vp_cfgh;
261 1.1 palle #endif
262 1.1 palle
263 1.1 palle bzero(&pba, sizeof(pba));
264 1.1 palle pba.pba_bus = busranges[0];
265 1.1 palle pba.pba_pc = pbm->vp_pc;
266 1.1 palle pba.pba_flags = pbm->vp_flags;
267 1.1 palle pba.pba_dmat = pbm->vp_dmat;
268 1.1 palle pba.pba_dmat64 = NULL; /* XXX */
269 1.1 palle pba.pba_memt = pbm->vp_memt;
270 1.1 palle pba.pba_iot = pbm->vp_iot;
271 1.1 palle
272 1.1 palle free(busranges, M_DEVBUF);
273 1.1 palle
274 1.1 palle config_found(sc->sc_dev, &pba, vpci_print);
275 1.1 palle }
276 1.1 palle
277 1.1 palle void
278 1.1 palle vpci_init_iommu(struct vpci_softc *sc, struct vpci_pbm *pbm)
279 1.1 palle {
280 1.1 palle struct iommu_state *is = &pbm->vp_is;
281 1.2 palle int *vdma = NULL;
282 1.2 palle int nitem;
283 1.2 palle int tsbsize = 0;
284 1.1 palle u_int32_t iobase = -1;
285 1.2 palle u_int32_t iolen = 0;
286 1.1 palle char *name;
287 1.1 palle
288 1.1 palle pbm->vp_sb.sb_is = is;
289 1.1 palle is->is_bustag = sc->sc_bustag;
290 1.1 palle
291 1.1 palle if (bus_space_subregion(is->is_bustag, sc->sc_csrh,
292 1.1 palle 0x40000, 0x100, &is->is_iommu)) {
293 1.1 palle panic("vpci: unable to create iommu handle");
294 1.1 palle }
295 1.1 palle
296 1.2 palle /* Construct tsbsize */
297 1.2 palle if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem,
298 1.2 palle (void **)&vdma)) {
299 1.2 palle DPRINTF(VDB_BUSMAP, ("vpci_init_iommu: vdma[0]=0x%x vdma[1]=0x%x\n",
300 1.2 palle vdma[0], vdma[1]));
301 1.2 palle iobase = vdma[0];
302 1.2 palle iolen = vdma[1];
303 1.6 joerg for (tsbsize = 8; (1 << (tsbsize+23)) > iolen;)
304 1.6 joerg tsbsize--;
305 1.2 palle DPRINTF(VDB_BUSMAP, ("vpci_init_iommu: iobase=0x%x iolen = 0x%x tsbsize=0x%x\n",
306 1.2 palle iobase, iolen, tsbsize));
307 1.2 palle free(vdma, M_DEVBUF);
308 1.2 palle } else
309 1.2 palle panic("vpci_init_iommu: getprop virtual-dma failed");
310 1.4 palle
311 1.5 palle aprint_normal(" vdma %x length %x\n", iobase, iolen);
312 1.5 palle aprint_naive("\n");
313 1.2 palle
314 1.1 palle /* We have no STC. */
315 1.1 palle is->is_sb[0] = NULL;
316 1.1 palle
317 1.1 palle name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
318 1.1 palle if (name == NULL)
319 1.1 palle panic("couldn't malloc iommu name");
320 1.1 palle snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev));
321 1.1 palle
322 1.1 palle /* Tell iommu how to set the TSB size. */
323 1.1 palle is->is_flags = IOMMU_TSBSIZE_IN_PTSB;
324 1.1 palle
325 1.2 palle is->is_devhandle = pbm->vp_devhandle;
326 1.1 palle iommu_init(name, is, tsbsize, iobase);
327 1.1 palle }
328 1.2 palle
329 1.1 palle
330 1.1 palle int
331 1.1 palle vpci_print(void *aux, const char *p)
332 1.1 palle {
333 1.1 palle if (p == NULL)
334 1.1 palle return (UNCONF);
335 1.1 palle return (QUIET);
336 1.1 palle }
337 1.1 palle
338 1.1 palle pcireg_t
339 1.1 palle vpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
340 1.1 palle {
341 1.1 palle struct vpci_pbm *pbm = pc->cookie;
342 1.1 palle uint64_t error_flag, data;
343 1.1 palle
344 1.1 palle int64_t hv_rc;
345 1.2 palle DPRINTF(VDB_CONF_READ, ("%s: tag %lx reg %x ", __func__, (long)tag, reg));
346 1.1 palle hv_rc = hv_pci_config_get(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4,
347 1.1 palle &error_flag, &data);
348 1.1 palle if (hv_rc != H_EOK)
349 1.1 palle panic("hv_pci_config_get() failed - rc = %" PRId64 "\n",
350 1.1 palle hv_rc);
351 1.1 palle
352 1.1 palle pcireg_t val = error_flag ? (pcireg_t)~0 : data;
353 1.2 palle DPRINTF(VDB_CONF_READ, (" returning %08x\n", (u_int)val));
354 1.1 palle return val;
355 1.1 palle }
356 1.1 palle
357 1.1 palle void
358 1.1 palle vpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
359 1.1 palle {
360 1.1 palle
361 1.1 palle struct vpci_pbm *pbm = pc->cookie;
362 1.1 palle uint64_t error_flag;
363 1.1 palle int64_t hv_rc;
364 1.2 palle DPRINTF(VDB_CONF_WRITE, ("%s: tag %lx; reg %x; data %x", __func__,
365 1.1 palle (long)tag, reg, (int)data));
366 1.1 palle hv_rc = hv_pci_config_put(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4,
367 1.1 palle data, &error_flag);
368 1.1 palle if (hv_rc != H_EOK)
369 1.1 palle panic("hv_pci_config_put() failed - rc = %" PRId64 "\n",
370 1.1 palle hv_rc);
371 1.2 palle DPRINTF(VDB_CONF_WRITE, (" .. done\n"));
372 1.1 palle }
373 1.1 palle
374 1.1 palle /*
375 1.1 palle * Bus-specific interrupt mapping
376 1.1 palle */
377 1.1 palle int
378 1.1 palle vpci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
379 1.1 palle {
380 1.1 palle struct vpci_pbm *pbm = pa->pa_pc->cookie;
381 1.1 palle uint64_t devhandle = pbm->vp_devhandle;
382 1.1 palle uint64_t devino = INTINO(*ihp);
383 1.1 palle DPRINTF(VDB_INTR, ("vpci_intr_map(): devino 0x%lx\n", devino));
384 1.1 palle uint64_t sysino;
385 1.1 palle int err;
386 1.1 palle
387 1.1 palle if (*ihp != (pci_intr_handle_t)-1) {
388 1.1 palle err = hv_intr_devino_to_sysino(devhandle, devino, &sysino);
389 1.1 palle if (err != H_EOK)
390 1.1 palle return (-1);
391 1.1 palle
392 1.1 palle KASSERT(sysino == INTVEC(sysino));
393 1.1 palle *ihp = sysino;
394 1.1 palle DPRINTF(VDB_INTR, ("vpci_intr_map(): sysino 0x%lx\n", sysino));
395 1.1 palle return (0);
396 1.1 palle }
397 1.1 palle
398 1.1 palle return (-1);
399 1.1 palle }
400 1.1 palle
401 1.1 palle bus_space_tag_t
402 1.1 palle vpci_alloc_mem_tag(struct vpci_pbm *vp)
403 1.1 palle {
404 1.1 palle return (vpci_alloc_bus_tag(vp, "mem", PCI_MEMORY_BUS_SPACE));
405 1.1 palle }
406 1.1 palle
407 1.1 palle bus_space_tag_t
408 1.1 palle vpci_alloc_io_tag(struct vpci_pbm *vp)
409 1.1 palle {
410 1.1 palle return (vpci_alloc_bus_tag(vp, "io", PCI_IO_BUS_SPACE));
411 1.1 palle }
412 1.1 palle
413 1.1 palle bus_space_tag_t
414 1.1 palle vpci_alloc_config_tag(struct vpci_pbm *vp)
415 1.1 palle {
416 1.1 palle return (vpci_alloc_bus_tag(vp, "cfg", PCI_CONFIG_BUS_SPACE));
417 1.1 palle }
418 1.1 palle
419 1.1 palle bus_space_tag_t
420 1.1 palle vpci_alloc_bus_tag(struct vpci_pbm *pbm, const char *name, int type)
421 1.1 palle {
422 1.1 palle struct vpci_softc *sc = pbm->vp_sc;
423 1.1 palle struct sparc_bus_space_tag *bt;
424 1.1 palle
425 1.1 palle bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO);
426 1.1 palle if (bt == NULL)
427 1.1 palle panic("vpci: could not allocate bus tag");
428 1.1 palle
429 1.1 palle #if 0
430 1.1 palle snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)",
431 1.1 palle device_xname(sc->sc_dev), name, ss, asi);
432 1.1 palle #endif
433 1.1 palle
434 1.1 palle bt->cookie = pbm;
435 1.1 palle bt->parent = sc->sc_bustag;
436 1.1 palle bt->type = type;
437 1.1 palle bt->sparc_bus_map = vpci_bus_map;
438 1.1 palle bt->sparc_bus_mmap = vpci_bus_mmap;
439 1.1 palle bt->sparc_intr_establish = vpci_intr_establish;
440 1.1 palle return (bt);
441 1.1 palle }
442 1.1 palle
443 1.1 palle bus_dma_tag_t
444 1.1 palle vpci_alloc_dma_tag(struct vpci_pbm *pbm)
445 1.1 palle {
446 1.1 palle struct vpci_softc *sc = pbm->vp_sc;
447 1.1 palle bus_dma_tag_t dt, pdt = sc->sc_dmat;
448 1.1 palle
449 1.1 palle dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO);
450 1.1 palle if (dt == NULL)
451 1.1 palle panic("vpci: could not alloc dma tag");
452 1.1 palle
453 1.1 palle dt->_cookie = pbm;
454 1.1 palle dt->_parent = pdt;
455 1.1 palle #define PCOPY(x) dt->x = pdt->x
456 1.1 palle dt->_dmamap_create = vpci_dmamap_create;
457 1.1 palle PCOPY(_dmamap_destroy);
458 1.1 palle dt->_dmamap_load = iommu_dvmamap_load;
459 1.1 palle PCOPY(_dmamap_load_mbuf);
460 1.1 palle PCOPY(_dmamap_load_uio);
461 1.1 palle dt->_dmamap_load_raw = iommu_dvmamap_load_raw;
462 1.1 palle dt->_dmamap_unload = iommu_dvmamap_unload;
463 1.1 palle dt->_dmamap_sync = iommu_dvmamap_sync;
464 1.1 palle dt->_dmamem_alloc = iommu_dvmamem_alloc;
465 1.1 palle dt->_dmamem_free = iommu_dvmamem_free;
466 1.2 palle dt->_dmamem_map = iommu_dvmamem_map;
467 1.2 palle dt->_dmamem_unmap = iommu_dvmamem_unmap;
468 1.1 palle PCOPY(_dmamem_mmap);
469 1.1 palle #undef PCOPY
470 1.1 palle return (dt);
471 1.1 palle }
472 1.1 palle
473 1.1 palle pci_chipset_tag_t
474 1.1 palle vpci_alloc_chipset(struct vpci_pbm *pbm, int node, pci_chipset_tag_t pc)
475 1.1 palle {
476 1.1 palle pci_chipset_tag_t npc;
477 1.1 palle
478 1.1 palle npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT);
479 1.1 palle if (npc == NULL)
480 1.1 palle panic("vpci: could not allocate pci_chipset_tag_t");
481 1.1 palle memcpy(npc, pc, sizeof *pc);
482 1.1 palle npc->cookie = pbm;
483 1.1 palle npc->rootnode = node;
484 1.1 palle npc->spc_conf_read = vpci_conf_read;
485 1.1 palle npc->spc_conf_write = vpci_conf_write;
486 1.1 palle npc->spc_intr_map = vpci_intr_map;
487 1.1 palle npc->spc_intr_establish = vpci_pci_intr_establish;
488 1.1 palle npc->spc_find_ino = NULL;
489 1.1 palle return (npc);
490 1.1 palle }
491 1.1 palle
492 1.1 palle int
493 1.1 palle vpci_dmamap_create(bus_dma_tag_t t, bus_size_t size,
494 1.1 palle int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags,
495 1.1 palle bus_dmamap_t *dmamp)
496 1.1 palle {
497 1.1 palle struct vpci_pbm *pbm = t->_cookie;
498 1.1 palle int error;
499 1.1 palle
500 1.1 palle error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
501 1.1 palle boundary, flags, dmamp);
502 1.1 palle if (error == 0)
503 1.1 palle (*dmamp)->_dm_cookie = &pbm->vp_sb;
504 1.1 palle return error;
505 1.1 palle }
506 1.1 palle
507 1.1 palle int
508 1.1 palle vpci_bus_map(bus_space_tag_t t, bus_addr_t offset,
509 1.1 palle bus_size_t size, int flags, vaddr_t unused, bus_space_handle_t *hp)
510 1.1 palle {
511 1.1 palle struct vpci_pbm *pbm = t->cookie;
512 1.1 palle struct vpci_softc *sc = pbm->vp_sc;
513 1.1 palle int i, ss;
514 1.1 palle
515 1.2 palle DPRINTF(VDB_BUSMAP, ("vpci_bus_map: type %d off %qx sz %qx flags %d",
516 1.1 palle t->type,
517 1.1 palle (unsigned long long)offset,
518 1.1 palle (unsigned long long)size,
519 1.1 palle flags));
520 1.1 palle
521 1.1 palle ss = sparc_pci_childspace(t->type);
522 1.2 palle DPRINTF(VDB_BUSMAP, (" cspace %d\n", ss));
523 1.1 palle
524 1.1 palle if (t->parent == 0 || t->parent->sparc_bus_map == 0) {
525 1.1 palle printf("\n_vpci_bus_map: invalid parent");
526 1.1 palle return (EINVAL);
527 1.1 palle }
528 1.1 palle
529 1.1 palle for (i = 0; i < pbm->vp_nrange; i++) {
530 1.1 palle bus_addr_t paddr;
531 1.1 palle struct vpci_range *pr = &pbm->vp_range[i];
532 1.1 palle
533 1.1 palle if (((pr->cspace >> 24) & 0x03) != ss)
534 1.1 palle continue;
535 1.1 palle
536 1.1 palle paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset);
537 1.1 palle return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size,
538 1.1 palle flags, 0, hp));
539 1.1 palle }
540 1.1 palle
541 1.1 palle return (EINVAL);
542 1.1 palle }
543 1.1 palle
544 1.1 palle paddr_t
545 1.1 palle vpci_bus_mmap(bus_space_tag_t t, bus_addr_t paddr,
546 1.1 palle off_t off, int prot, int flags)
547 1.1 palle {
548 1.1 palle bus_addr_t offset = paddr;
549 1.1 palle struct vpci_pbm *pbm = t->cookie;
550 1.1 palle struct vpci_softc *sc = pbm->vp_sc;
551 1.1 palle int i, ss;
552 1.1 palle
553 1.1 palle ss = sparc_pci_childspace(t->type);
554 1.1 palle
555 1.1 palle DPRINTF(VDB_BUSMAP, ("vpci_bus_mmap: prot %d flags %d pa %qx\n",
556 1.1 palle prot, flags, (unsigned long long)paddr));
557 1.1 palle
558 1.1 palle if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) {
559 1.1 palle printf("\n_vpci_bus_mmap: invalid parent");
560 1.1 palle return (-1);
561 1.1 palle }
562 1.1 palle
563 1.1 palle for (i = 0; i < pbm->vp_nrange; i++) {
564 1.1 palle struct vpci_range *pr = &pbm->vp_range[i];
565 1.1 palle
566 1.1 palle if (((pr->cspace >> 24) & 0x03) != ss)
567 1.1 palle continue;
568 1.1 palle
569 1.1 palle paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset);
570 1.1 palle return (bus_space_mmap(sc->sc_bustag, paddr, off,
571 1.1 palle prot, flags));
572 1.1 palle }
573 1.1 palle
574 1.1 palle return (-1);
575 1.1 palle }
576 1.1 palle
577 1.1 palle void *
578 1.1 palle vpci_intr_establish(bus_space_tag_t t, int ihandle, int level,
579 1.1 palle int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */)
580 1.1 palle {
581 1.1 palle struct intrhand *ih = NULL;
582 1.1 palle int ino;
583 1.1 palle
584 1.1 palle ino = INTINO(ihandle);
585 1.1 palle DPRINTF(VDB_INTR, ("%s: ih %lx; level %d ino %#x\n", __func__, (u_long)ihandle, level, ino));
586 1.1 palle
587 1.1 palle if (level == IPL_NONE) {
588 1.1 palle level = INTLEV(ihandle);
589 1.1 palle printf(": IPL_NONE, setting IPL %d.\n", level);
590 1.1 palle }
591 1.1 palle if (level == IPL_NONE) {
592 1.1 palle level = 2;
593 1.1 palle printf(": no IPL, setting IPL 2.\n");
594 1.1 palle }
595 1.1 palle
596 1.1 palle ino |= INTVEC(ihandle);
597 1.1 palle DPRINTF(VDB_INTR, ("%s: ih %lx; level %d ino %#x\n", __func__, (u_long)ihandle, level, ino));
598 1.1 palle
599 1.7 palle ih = intrhand_alloc();
600 1.1 palle
601 1.1 palle ih->ih_ivec = ihandle;
602 1.1 palle ih->ih_fun = handler;
603 1.1 palle ih->ih_arg = arg;
604 1.1 palle ih->ih_pil = level;
605 1.1 palle ih->ih_number = ino;
606 1.1 palle ih->ih_pending = 0;
607 1.7 palle ih->ih_ack = vpci_intr_ack;
608 1.1 palle intr_establish(ih->ih_pil, level != IPL_VM, ih);
609 1.1 palle
610 1.7 palle uint64_t sysino = INTVEC(ihandle);
611 1.7 palle DPRINTF(VDB_INTR, ("vpci_intr_establish(): sysino 0x%lx\n", sysino));
612 1.7 palle
613 1.7 palle int err;
614 1.7 palle
615 1.7 palle err = hv_intr_settarget(sysino, cpus->ci_cpuid);
616 1.7 palle if (err != H_EOK)
617 1.7 palle printf("hv_intr_settarget(%lu, %u) failed - err = %d\n",
618 1.7 palle (long unsigned int)sysino, cpus->ci_cpuid, err);
619 1.7 palle
620 1.7 palle /* Clear pending interrupts. */
621 1.7 palle err = hv_intr_setstate(sysino, INTR_IDLE);
622 1.7 palle if (err != H_EOK)
623 1.7 palle printf("hv_intr_setstate(%lu, INTR_IDLE) failed - err = %d\n",
624 1.7 palle (long unsigned int)sysino, err);
625 1.7 palle
626 1.7 palle err = hv_intr_setenabled(sysino, INTR_ENABLED);
627 1.7 palle if (err != H_EOK)
628 1.7 palle printf("hv_intr_setenabled(%lu) failed - err = %d\n",
629 1.7 palle (long unsigned int)sysino, err);
630 1.7 palle
631 1.7 palle DPRINTF(VDB_INTR, ("%s() returning %p\n", __func__, ih));
632 1.1 palle return (ih);
633 1.1 palle }
634 1.1 palle
635 1.7 palle void
636 1.7 palle vpci_intr_ack(struct intrhand *ih)
637 1.7 palle {
638 1.7 palle int err;
639 1.7 palle err = hv_intr_setstate(ih->ih_number, INTR_IDLE);
640 1.7 palle if (err != H_EOK)
641 1.7 palle panic("%s(%u, INTR_IDLE) failed - err = %d\n",
642 1.7 palle __func__, ih->ih_number, err);
643 1.7 palle }
644 1.7 palle
645 1.1 palle static void *
646 1.1 palle vpci_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
647 1.1 palle int (*func)(void *), void *arg)
648 1.1 palle {
649 1.1 palle void *cookie;
650 1.1 palle struct vpci_pbm *pbm = (struct vpci_pbm *)pc->cookie;
651 1.1 palle
652 1.1 palle DPRINTF(VDB_INTR, ("%s: ih %lx; level %d\n", __func__, (u_long)ih, level));
653 1.1 palle cookie = bus_intr_establish(pbm->vp_memt, ih, level, func, arg);
654 1.1 palle
655 1.1 palle DPRINTF(VDB_INTR, ("%s: returning handle %p\n", __func__, cookie));
656 1.1 palle return (cookie);
657 1.1 palle }
658