vpci.c revision 1.8.8.1
1 /* $NetBSD: vpci.c,v 1.8.8.1 2021/04/03 22:28:38 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2015 Palle Lyckegaard 4 * All rights reserved. 5 * 6 * Driver for virtual PCIe host bridge on sun4v systems. 7 * 8 * Based on NetBSD pyro and OpenBSD vpci drivers. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: vpci.c,v 1.8.8.1 2021/04/03 22:28:38 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/malloc.h> 39 #include <sys/kmem.h> 40 #include <sys/systm.h> 41 42 #define _SPARC_BUS_DMA_PRIVATE 43 #include <sys/bus.h> 44 #include <machine/autoconf.h> 45 46 #ifdef DDB 47 #include <machine/db_machdep.h> 48 #endif 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/dev/iommuvar.h> 55 #include <sparc64/dev/vpcivar.h> 56 57 #include <machine/hypervisor.h> 58 59 #ifdef DEBUG 60 #define VDB_PROM 0x01 61 #define VDB_BUSMAP 0x02 62 #define VDB_INTR 0x04 63 #define VDB_CONF_READ 0x08 64 #define VDB_CONF_WRITE 0x10 65 #define VDB_CONF VDB_CONF_READ|VDB_CONF_WRITE 66 int vpci_debug = 0x00; 67 #define DPRINTF(l, s) do { if (vpci_debug & l) printf s; } while (0) 68 #else 69 #define DPRINTF(l, s) 70 #endif 71 72 #if 0 73 FIXME 74 #define FIRE_RESET_GEN 0x7010 75 76 #define FIRE_RESET_GEN_XIR 0x0000000000000002L 77 78 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 79 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 80 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 81 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 82 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 83 #define FIRE_INTRMAP_T_JPID_SHIFT 26 84 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 85 86 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 87 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 88 #endif 89 90 extern struct sparc_pci_chipset _sparc_pci_chipset; 91 92 int vpci_match(device_t, cfdata_t, void *); 93 void vpci_attach(device_t, device_t, void *); 94 int vpci_print(void *, const char *); 95 96 CFATTACH_DECL_NEW(vpci, sizeof(struct vpci_softc), 97 vpci_match, vpci_attach, NULL, NULL); 98 99 void vpci_init(struct vpci_softc */*FIXME, int*/, struct mainbus_attach_args *); 100 void vpci_init_iommu(struct vpci_softc *, struct vpci_pbm *); 101 pci_chipset_tag_t vpci_alloc_chipset(struct vpci_pbm *, int, 102 pci_chipset_tag_t); 103 bus_space_tag_t vpci_alloc_mem_tag(struct vpci_pbm *); 104 bus_space_tag_t vpci_alloc_io_tag(struct vpci_pbm *); 105 bus_space_tag_t vpci_alloc_config_tag(struct vpci_pbm *); 106 bus_space_tag_t vpci_alloc_bus_tag(struct vpci_pbm *, const char *, int); 107 bus_dma_tag_t vpci_alloc_dma_tag(struct vpci_pbm *); 108 109 #if 0 110 int vpci_conf_size(pci_chipset_tag_t, pcitag_t); 111 #endif 112 pcireg_t vpci_conf_read(pci_chipset_tag_t, pcitag_t, int); 113 void vpci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 114 115 static void * vpci_pci_intr_establish(pci_chipset_tag_t pc, 116 pci_intr_handle_t ih, int level, 117 int (*func)(void *), void *arg); 118 void vpci_intr_ack(struct intrhand *); 119 int vpci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 120 int vpci_bus_map(bus_space_tag_t, bus_addr_t, 121 bus_size_t, int, vaddr_t, bus_space_handle_t *); 122 paddr_t vpci_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, 123 int, int); 124 void *vpci_intr_establish(bus_space_tag_t, int, int, 125 int (*)(void *), void *, void (*)(void)); 126 127 int vpci_dmamap_create(bus_dma_tag_t, bus_size_t, int, 128 bus_size_t, bus_size_t, int, bus_dmamap_t *); 129 130 int 131 vpci_match(device_t parent, cfdata_t match, void *aux) 132 { 133 struct mainbus_attach_args *ma = aux; 134 char compat[32]; 135 136 if (strcmp(ma->ma_name, "pci") != 0) 137 return (0); 138 139 if (OF_getprop(ma->ma_node, "compatible", compat, sizeof(compat)) == -1) 140 return (0); 141 142 if (strcmp(compat, "SUNW,sun4v-pci") == 0) 143 return (1); 144 145 return (0); 146 } 147 148 void 149 vpci_attach(device_t parent, device_t self, void *aux) 150 { 151 struct vpci_softc *sc = device_private(self); 152 struct mainbus_attach_args *ma = aux; 153 #if 0 154 FIXME 155 char *str; 156 int busa; 157 #endif 158 sc->sc_dev = self; 159 sc->sc_node = ma->ma_node; 160 sc->sc_dmat = ma->ma_dmatag; 161 sc->sc_bustag = ma->ma_bustag; 162 sc->sc_csr = ma->ma_reg[0].ur_paddr; 163 #if 0 164 FIXME 165 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 166 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 167 168 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 169 busa = 1; 170 else 171 busa = 0; 172 #endif 173 #if 0 174 FIXME 175 if (bus_space_map(sc->sc_bustag, sc->sc_csr, 176 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, &sc->sc_csrh)) { 177 printf(": failed to map csr registers\n"); 178 return; 179 } 180 #endif 181 #if 0 182 FIXME 183 if (bus_space_map(sc->sc_bustag, sc->sc_xbc, 184 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 185 printf(": failed to map xbc registers\n"); 186 return; 187 } 188 189 str = prom_getpropstring(ma->ma_node, "compatible"); 190 if (strcmp(str, "pciex108e,80f8") == 0) 191 sc->sc_oberon = 1; 192 193 #endif 194 vpci_init(sc/*FIXME, busa*/, ma); 195 } 196 197 void 198 vpci_init(struct vpci_softc *sc/*FIXME, int busa*/, struct mainbus_attach_args *ma) 199 { 200 struct vpci_pbm *pbm; 201 struct pcibus_attach_args pba; 202 int *busranges = NULL, nranges; 203 204 pbm = kmem_zalloc(sizeof(*pbm), KM_SLEEP); 205 pbm->vp_sc = sc; 206 pbm->vp_devhandle = (ma->ma_reg[0].ur_paddr >> 32) & 0x0fffffff; 207 #if 0 208 FiXME 209 pbm->vp_bus_a = busa; 210 #endif 211 212 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct vpci_range), 213 &pbm->vp_nrange, (void **)&pbm->vp_range)) 214 panic("vpci: can't get ranges"); 215 for (int range = 0; range < pbm->vp_nrange; range++) 216 DPRINTF(VDB_PROM, 217 ("\nvpci_attach: range %d cspace %08x " 218 "child_hi %08x child_lo %08x phys_hi %08x phys_lo %08x " 219 "size_hi %08x size_lo %08x", range, 220 pbm->vp_range[range].cspace, 221 pbm->vp_range[range].child_hi, 222 pbm->vp_range[range].child_lo, 223 pbm->vp_range[range].phys_hi, 224 pbm->vp_range[range].phys_lo, 225 pbm->vp_range[range].size_hi, 226 pbm->vp_range[range].size_lo)); 227 228 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 229 (void **)&busranges)) 230 panic("vpci: can't get bus-range"); 231 for (int range = 0; range < nranges; range++) 232 DPRINTF(VDB_PROM, ("\nvpci_attach: bus-range %d %08x", range, busranges[range])); 233 234 aprint_normal(": bus %d to %d", busranges[0], busranges[1]); 235 236 vpci_init_iommu(sc, pbm); 237 238 pbm->vp_memt = vpci_alloc_mem_tag(pbm); 239 pbm->vp_iot = vpci_alloc_io_tag(pbm); 240 pbm->vp_cfgt = vpci_alloc_config_tag(pbm); 241 pbm->vp_dmat = vpci_alloc_dma_tag(pbm); 242 pbm->vp_flags = (pbm->vp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 243 (pbm->vp_iot ? PCI_FLAGS_IO_OKAY : 0); 244 #if 0 245 FIXME 246 if (bus_space_map(pbm->vp_cfgt, 0, 0x10000000, 0, &pbm->vp_cfgh)) 247 panic("vpci: can't map config space"); 248 #endif 249 pbm->vp_pc = vpci_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 250 pbm->vp_pc->spc_busmax = busranges[1]; 251 pbm->vp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->vp_pc->spc_busnode), 252 KM_SLEEP); 253 254 #if 0 255 pbm->vp_pc->bustag = pbm->vp_cfgt; 256 pbm->vp_pc->bushandle = pbm->vp_cfgh; 257 #endif 258 259 bzero(&pba, sizeof(pba)); 260 pba.pba_bus = busranges[0]; 261 pba.pba_pc = pbm->vp_pc; 262 pba.pba_flags = pbm->vp_flags; 263 pba.pba_dmat = pbm->vp_dmat; 264 pba.pba_dmat64 = NULL; /* XXX */ 265 pba.pba_memt = pbm->vp_memt; 266 pba.pba_iot = pbm->vp_iot; 267 268 free(busranges, M_DEVBUF); 269 270 config_found(sc->sc_dev, &pba, vpci_print); 271 } 272 273 void 274 vpci_init_iommu(struct vpci_softc *sc, struct vpci_pbm *pbm) 275 { 276 struct iommu_state *is = &pbm->vp_is; 277 int *vdma = NULL; 278 int nitem; 279 int tsbsize = 0; 280 u_int32_t iobase = -1; 281 u_int32_t iolen = 0; 282 char *name; 283 284 pbm->vp_sb.sb_is = is; 285 is->is_bustag = sc->sc_bustag; 286 287 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 288 0x40000, 0x100, &is->is_iommu)) { 289 panic("vpci: unable to create iommu handle"); 290 } 291 292 /* Construct tsbsize */ 293 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 294 (void **)&vdma)) { 295 DPRINTF(VDB_BUSMAP, ("vpci_init_iommu: vdma[0]=0x%x vdma[1]=0x%x\n", 296 vdma[0], vdma[1])); 297 iobase = vdma[0]; 298 iolen = vdma[1]; 299 for (tsbsize = 8; (1 << (tsbsize+23)) > iolen;) 300 tsbsize--; 301 DPRINTF(VDB_BUSMAP, ("vpci_init_iommu: iobase=0x%x iolen = 0x%x tsbsize=0x%x\n", 302 iobase, iolen, tsbsize)); 303 free(vdma, M_DEVBUF); 304 } else 305 panic("vpci_init_iommu: getprop virtual-dma failed"); 306 307 aprint_normal(" vdma %x length %x\n", iobase, iolen); 308 aprint_naive("\n"); 309 310 /* We have no STC. */ 311 is->is_sb[0] = NULL; 312 313 name = kmem_asprintf("%s dvma", device_xname(sc->sc_dev)); 314 315 /* Tell iommu how to set the TSB size. */ 316 is->is_flags = IOMMU_TSBSIZE_IN_PTSB; 317 318 is->is_devhandle = pbm->vp_devhandle; 319 iommu_init(name, is, tsbsize, iobase); 320 } 321 322 323 int 324 vpci_print(void *aux, const char *p) 325 { 326 if (p == NULL) 327 return (UNCONF); 328 return (QUIET); 329 } 330 331 pcireg_t 332 vpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 333 { 334 struct vpci_pbm *pbm = pc->cookie; 335 uint64_t error_flag, data; 336 337 int64_t hv_rc; 338 DPRINTF(VDB_CONF_READ, ("%s: tag %lx reg %x ", __func__, (long)tag, reg)); 339 hv_rc = hv_pci_config_get(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4, 340 &error_flag, &data); 341 if (hv_rc != H_EOK) 342 panic("hv_pci_config_get() failed - rc = %" PRId64 "\n", 343 hv_rc); 344 345 pcireg_t val = error_flag ? (pcireg_t)~0 : data; 346 DPRINTF(VDB_CONF_READ, (" returning %08x\n", (u_int)val)); 347 return val; 348 } 349 350 void 351 vpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 352 { 353 354 struct vpci_pbm *pbm = pc->cookie; 355 uint64_t error_flag; 356 int64_t hv_rc; 357 DPRINTF(VDB_CONF_WRITE, ("%s: tag %lx; reg %x; data %x", __func__, 358 (long)tag, reg, (int)data)); 359 hv_rc = hv_pci_config_put(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4, 360 data, &error_flag); 361 if (hv_rc != H_EOK) 362 panic("hv_pci_config_put() failed - rc = %" PRId64 "\n", 363 hv_rc); 364 DPRINTF(VDB_CONF_WRITE, (" .. done\n")); 365 } 366 367 /* 368 * Bus-specific interrupt mapping 369 */ 370 int 371 vpci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 372 { 373 struct vpci_pbm *pbm = pa->pa_pc->cookie; 374 uint64_t devhandle = pbm->vp_devhandle; 375 uint64_t devino = INTINO(*ihp); 376 DPRINTF(VDB_INTR, ("vpci_intr_map(): devino 0x%lx\n", devino)); 377 uint64_t sysino; 378 int err; 379 380 if (*ihp != (pci_intr_handle_t)-1) { 381 err = hv_intr_devino_to_sysino(devhandle, devino, &sysino); 382 if (err != H_EOK) 383 return (-1); 384 385 KASSERT(sysino == INTVEC(sysino)); 386 *ihp = sysino; 387 DPRINTF(VDB_INTR, ("vpci_intr_map(): sysino 0x%lx\n", sysino)); 388 return (0); 389 } 390 391 return (-1); 392 } 393 394 bus_space_tag_t 395 vpci_alloc_mem_tag(struct vpci_pbm *vp) 396 { 397 return (vpci_alloc_bus_tag(vp, "mem", PCI_MEMORY_BUS_SPACE)); 398 } 399 400 bus_space_tag_t 401 vpci_alloc_io_tag(struct vpci_pbm *vp) 402 { 403 return (vpci_alloc_bus_tag(vp, "io", PCI_IO_BUS_SPACE)); 404 } 405 406 bus_space_tag_t 407 vpci_alloc_config_tag(struct vpci_pbm *vp) 408 { 409 return (vpci_alloc_bus_tag(vp, "cfg", PCI_CONFIG_BUS_SPACE)); 410 } 411 412 bus_space_tag_t 413 vpci_alloc_bus_tag(struct vpci_pbm *pbm, const char *name, int type) 414 { 415 struct vpci_softc *sc = pbm->vp_sc; 416 struct sparc_bus_space_tag *bt; 417 418 bt = kmem_zalloc(sizeof(*bt), KM_SLEEP); 419 420 #if 0 421 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 422 device_xname(sc->sc_dev), name, ss, asi); 423 #endif 424 425 bt->cookie = pbm; 426 bt->parent = sc->sc_bustag; 427 bt->type = type; 428 bt->sparc_bus_map = vpci_bus_map; 429 bt->sparc_bus_mmap = vpci_bus_mmap; 430 bt->sparc_intr_establish = vpci_intr_establish; 431 return (bt); 432 } 433 434 bus_dma_tag_t 435 vpci_alloc_dma_tag(struct vpci_pbm *pbm) 436 { 437 struct vpci_softc *sc = pbm->vp_sc; 438 bus_dma_tag_t dt, pdt = sc->sc_dmat; 439 440 dt = kmem_zalloc(sizeof(*dt), KM_SLEEP); 441 dt->_cookie = pbm; 442 dt->_parent = pdt; 443 #define PCOPY(x) dt->x = pdt->x 444 dt->_dmamap_create = vpci_dmamap_create; 445 PCOPY(_dmamap_destroy); 446 dt->_dmamap_load = iommu_dvmamap_load; 447 PCOPY(_dmamap_load_mbuf); 448 PCOPY(_dmamap_load_uio); 449 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 450 dt->_dmamap_unload = iommu_dvmamap_unload; 451 dt->_dmamap_sync = iommu_dvmamap_sync; 452 dt->_dmamem_alloc = iommu_dvmamem_alloc; 453 dt->_dmamem_free = iommu_dvmamem_free; 454 dt->_dmamem_map = iommu_dvmamem_map; 455 dt->_dmamem_unmap = iommu_dvmamem_unmap; 456 PCOPY(_dmamem_mmap); 457 #undef PCOPY 458 return (dt); 459 } 460 461 pci_chipset_tag_t 462 vpci_alloc_chipset(struct vpci_pbm *pbm, int node, pci_chipset_tag_t pc) 463 { 464 pci_chipset_tag_t npc; 465 466 npc = kmem_alloc(sizeof *npc, KM_SLEEP); 467 memcpy(npc, pc, sizeof *pc); 468 npc->cookie = pbm; 469 npc->rootnode = node; 470 npc->spc_conf_read = vpci_conf_read; 471 npc->spc_conf_write = vpci_conf_write; 472 npc->spc_intr_map = vpci_intr_map; 473 npc->spc_intr_establish = vpci_pci_intr_establish; 474 npc->spc_find_ino = NULL; 475 return (npc); 476 } 477 478 int 479 vpci_dmamap_create(bus_dma_tag_t t, bus_size_t size, 480 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 481 bus_dmamap_t *dmamp) 482 { 483 struct vpci_pbm *pbm = t->_cookie; 484 int error; 485 486 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 487 boundary, flags, dmamp); 488 if (error == 0) 489 (*dmamp)->_dm_cookie = &pbm->vp_sb; 490 return error; 491 } 492 493 int 494 vpci_bus_map(bus_space_tag_t t, bus_addr_t offset, 495 bus_size_t size, int flags, vaddr_t unused, bus_space_handle_t *hp) 496 { 497 struct vpci_pbm *pbm = t->cookie; 498 struct vpci_softc *sc = pbm->vp_sc; 499 int i, ss; 500 501 DPRINTF(VDB_BUSMAP, ("vpci_bus_map: type %d off %qx sz %qx flags %d", 502 t->type, 503 (unsigned long long)offset, 504 (unsigned long long)size, 505 flags)); 506 507 ss = sparc_pci_childspace(t->type); 508 DPRINTF(VDB_BUSMAP, (" cspace %d\n", ss)); 509 510 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 511 printf("\n_vpci_bus_map: invalid parent"); 512 return (EINVAL); 513 } 514 515 for (i = 0; i < pbm->vp_nrange; i++) { 516 bus_addr_t paddr; 517 struct vpci_range *pr = &pbm->vp_range[i]; 518 519 if (((pr->cspace >> 24) & 0x03) != ss) 520 continue; 521 522 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 523 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 524 flags, 0, hp)); 525 } 526 527 return (EINVAL); 528 } 529 530 paddr_t 531 vpci_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, 532 off_t off, int prot, int flags) 533 { 534 bus_addr_t offset = paddr; 535 struct vpci_pbm *pbm = t->cookie; 536 struct vpci_softc *sc = pbm->vp_sc; 537 int i, ss; 538 539 ss = sparc_pci_childspace(t->type); 540 541 DPRINTF(VDB_BUSMAP, ("vpci_bus_mmap: prot %d flags %d pa %qx\n", 542 prot, flags, (unsigned long long)paddr)); 543 544 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 545 printf("\n_vpci_bus_mmap: invalid parent"); 546 return (-1); 547 } 548 549 for (i = 0; i < pbm->vp_nrange; i++) { 550 struct vpci_range *pr = &pbm->vp_range[i]; 551 552 if (((pr->cspace >> 24) & 0x03) != ss) 553 continue; 554 555 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 556 return (bus_space_mmap(sc->sc_bustag, paddr, off, 557 prot, flags)); 558 } 559 560 return (-1); 561 } 562 563 void * 564 vpci_intr_establish(bus_space_tag_t t, int ihandle, int level, 565 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 566 { 567 struct intrhand *ih = NULL; 568 int ino; 569 570 ino = INTINO(ihandle); 571 DPRINTF(VDB_INTR, ("%s: ih %lx; level %d ino %#x\n", __func__, (u_long)ihandle, level, ino)); 572 573 if (level == IPL_NONE) { 574 level = INTLEV(ihandle); 575 printf(": IPL_NONE, setting IPL %d.\n", level); 576 } 577 if (level == IPL_NONE) { 578 level = 2; 579 printf(": no IPL, setting IPL 2.\n"); 580 } 581 582 ino |= INTVEC(ihandle); 583 DPRINTF(VDB_INTR, ("%s: ih %lx; level %d ino %#x\n", __func__, (u_long)ihandle, level, ino)); 584 585 ih = intrhand_alloc(); 586 587 ih->ih_ivec = ihandle; 588 ih->ih_fun = handler; 589 ih->ih_arg = arg; 590 ih->ih_pil = level; 591 ih->ih_number = ino; 592 ih->ih_pending = 0; 593 ih->ih_ack = vpci_intr_ack; 594 intr_establish(ih->ih_pil, level != IPL_VM, ih); 595 596 uint64_t sysino = INTVEC(ihandle); 597 DPRINTF(VDB_INTR, ("vpci_intr_establish(): sysino 0x%lx\n", sysino)); 598 599 int err; 600 601 err = hv_intr_settarget(sysino, cpus->ci_cpuid); 602 if (err != H_EOK) 603 printf("hv_intr_settarget(%lu, %u) failed - err = %d\n", 604 (long unsigned int)sysino, cpus->ci_cpuid, err); 605 606 /* Clear pending interrupts. */ 607 err = hv_intr_setstate(sysino, INTR_IDLE); 608 if (err != H_EOK) 609 printf("hv_intr_setstate(%lu, INTR_IDLE) failed - err = %d\n", 610 (long unsigned int)sysino, err); 611 612 err = hv_intr_setenabled(sysino, INTR_ENABLED); 613 if (err != H_EOK) 614 printf("hv_intr_setenabled(%lu) failed - err = %d\n", 615 (long unsigned int)sysino, err); 616 617 DPRINTF(VDB_INTR, ("%s() returning %p\n", __func__, ih)); 618 return (ih); 619 } 620 621 void 622 vpci_intr_ack(struct intrhand *ih) 623 { 624 int err; 625 err = hv_intr_setstate(ih->ih_number, INTR_IDLE); 626 if (err != H_EOK) 627 panic("%s(%u, INTR_IDLE) failed - err = %d\n", 628 __func__, ih->ih_number, err); 629 } 630 631 static void * 632 vpci_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 633 int (*func)(void *), void *arg) 634 { 635 void *cookie; 636 struct vpci_pbm *pbm = (struct vpci_pbm *)pc->cookie; 637 638 DPRINTF(VDB_INTR, ("%s: ih %lx; level %d\n", __func__, (u_long)ih, level)); 639 cookie = bus_intr_establish(pbm->vp_memt, ih, level, func, arg); 640 641 DPRINTF(VDB_INTR, ("%s: returning handle %p\n", __func__, cookie)); 642 return (cookie); 643 } 644
Indexes created Mon Oct 13 16:09:52 GMT 2025