zsvar.h revision 1.1.1.1.24.1
1 /* $NetBSD: zsvar.h,v 1.1.1.1.24.1 2000/07/18 16:23:21 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)zsvar.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Register layout is machine-dependent... 49 */ 50 51 struct zschan { 52 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 53 u_char zc_xxx0; 54 volatile u_char zc_data; /* data */ 55 u_char zc_xxx1; 56 }; 57 58 struct zsdevice { 59 struct zschan zs_chan[2]; 60 }; 61 62 /* 63 * Software state, per zs channel. 64 * 65 * The zs chip has insufficient buffering, so we provide a software 66 * buffer using a two-level interrupt scheme. The hardware (high priority) 67 * interrupt simply grabs the `cause' of the interrupt and stuffs it into 68 * a ring buffer. It then schedules a software interrupt; the latter 69 * empties the ring as fast as it can, hoping to avoid overflow. 70 * 71 * Interrupts can happen because of: 72 * - received data; 73 * - transmit pseudo-DMA done; and 74 * - status change. 75 * These are all stored together in the (single) ring. The size of the 76 * ring is a power of two, to make % operations fast. Since we need two 77 * bits to distinguish the interrupt type, and up to 16 for the received 78 * data plus RR1 status, we use 32 bits per ring entry. 79 * 80 * When the value is a character + RR1 status, the character is in the 81 * upper 8 bits of the RR1 status. 82 */ 83 84 /* 0 is reserved (means "no interrupt") */ 85 #define ZRING_RINT 1 /* receive data interrupt */ 86 #define ZRING_XINT 2 /* transmit done interrupt */ 87 #define ZRING_SINT 3 /* status change interrupt */ 88 89 #define ZRING_TYPE(x) ((x) & 3) 90 #define ZRING_VALUE(x) ((x) >> 8) 91 #define ZRING_MAKE(t, v) ((t) | (v) << 8) 92 93 /* forard decl */ 94 struct zs_softc; 95 96 struct zs_chanstate { 97 struct zs_chanstate *cs_next; /* linked list for zshard() */ 98 struct zs_softc *cs_sc; /* pointer to softc */ 99 volatile struct zschan *cs_zc; /* points to hardware regs */ 100 struct tty *cs_ttyp; /* ### */ 101 int cs_unit; /* unit number */ 102 103 /* 104 * We must keep a copy of the write registers as they are 105 * mostly write-only and we sometimes need to set and clear 106 * individual bits (e.g., in WR3). Not all of these are 107 * needed but 16 bytes is cheap and this makes the addressing 108 * simpler. Unfortunately, we can only write to some registers 109 * when the chip is not actually transmitting, so whenever 110 * we are expecting a `transmit done' interrupt the preg array 111 * is allowed to `get ahead' of the current values. In a 112 * few places we must change the current value of a register, 113 * rather than (or in addition to) the pending value; for these 114 * cs_creg[] contains the current value. 115 */ 116 u_char cs_creg[16]; /* current values */ 117 u_char cs_preg[16]; /* pending values */ 118 u_char cs_heldchange; /* change pending (creg != preg) */ 119 u_char cs_rr0; /* last rr0 processed */ 120 121 /* pure software data, per channel */ 122 char cs_softcar; /* software carrier */ 123 char cs_conk; /* is console keyboard, decode L1-A */ 124 char cs_brkabort; /* abort (as if via L1-A) on BREAK */ 125 char cs_kgdb; /* enter debugger on frame char */ 126 char cs_consio; /* port does /dev/console I/O */ 127 char cs_xxx; /* (spare) */ 128 int cs_speed; /* default baud rate (from ROM) */ 129 130 /* 131 * The transmit byte count and address are used for pseudo-DMA 132 * output in the hardware interrupt code. PDMA can be suspended 133 * to get pending changes done; heldtbc is used for this. It can 134 * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state. 135 */ 136 int cs_tbc; /* transmit byte count */ 137 int cs_heldtbc; /* held tbc while xmission stopped */ 138 caddr_t cs_tba; /* transmit buffer address */ 139 140 /* 141 * Printing an overrun error message often takes long enough to 142 * cause another overrun, so we only print one per second. 143 */ 144 long cs_rotime; /* time of last ring overrun */ 145 long cs_fotime; /* time of last fifo overrun */ 146 147 /* 148 * The ring buffer. 149 */ 150 u_int cs_rbget; /* ring buffer `get' index */ 151 volatile u_int cs_rbput; /* ring buffer `put' index */ 152 u_int cs_ringmask; /* mask, reflecting size of `rbuf' */ 153 int *cs_rbuf; /* type, value pairs */ 154 }; 155 156 /* 157 * N.B.: the keyboard is channel 1, the mouse channel 0; ttyb is 1, ttya 158 * is 0. In other words, the things are BACKWARDS. 159 */ 160 #define ZS_CHAN_A 1 161 #define ZS_CHAN_B 0 162 163 /* 164 * Macros to read and write individual registers (except 0) in a channel. 165 * 166 * On the SparcStation the 1.6 microsecond recovery time is 167 * handled in hardware. On the older Sun4 machine it isn't, and 168 * software must deal with the problem. 169 * 170 * However, it *is* a problem on some Sun4m's (i.e. the SS20) (XXX: why?). 171 * Thus we leave in the delay. 172 * 173 * XXX: (ABB) Think about this more. 174 */ 175 #if 0 176 177 #define ZS_READ(c, r) zs_read(c, r) 178 #define ZS_WRITE(c, r, v) zs_write(c, r, v) 179 /*#define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(1))*/ 180 #define ZS_DELAY() (delay(1)) 181 182 #else /* SUN4 */ 183 184 #define ZS_READ(c, r) ((c)->zc_csr = (r), (c)->zc_csr) 185 #define ZS_WRITE(c, r, v) ((c)->zc_csr = (r), (c)->zc_csr = (v)) 186 /* #define ZS_DELAY() (CPU_ISSUN4M ? delay(1) : 0) */ 187 #define ZS_DELAY() (0) 188 189 #endif /* SUN4 */ 190
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