cpu.h revision 1.13
1 /* $NetBSD: cpu.h,v 1.13 1999/10/11 01:57:44 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_MAXID 2 /* number of valid machdep ids */ 55 56 #define CTL_MACHDEP_NAMES { \ 57 { 0, 0 }, \ 58 { "booted_kernel", CTLTYPE_STRING }, \ 59 } 60 61 #ifdef _KERNEL 62 /* 63 * Exported definitions unique to SPARC cpu support. 64 */ 65 66 #include <machine/psl.h> 67 #include <machine/reg.h> 68 #include <machine/intr.h> 69 #include <sparc64/sparc64/intreg.h> 70 71 /* 72 * definitions of cpu-dependent requirements 73 * referenced in generic code 74 */ 75 #define cpu_swapin(p) /* nothing */ 76 #define cpu_swapout(p) /* nothing */ 77 #define cpu_wait(p) /* nothing */ 78 #define cpu_number() 0 79 80 /* 81 * Arguments to hardclock, softclock and gatherstats encapsulate the 82 * previous machine state in an opaque clockframe. The ipl is here 83 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 84 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 85 */ 86 extern int eintstack[]; 87 struct clockframe { 88 struct trapframe t; 89 }; 90 91 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 92 #define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0) 93 #define CLKF_PC(framep) ((framep)->t.tf_pc) 94 #define CLKF_INTR(framep) (((framep)->t.tf_kstack < (u_int)eintstack)&&((framep)->t.tf_kstack > (u_int)KERNBASE)) 95 96 /* 97 * Software interrupt request `register'. 98 */ 99 union sir { 100 int sir_any; 101 char sir_which[4]; 102 } sir; 103 104 #define SIR_NET 0 105 #define SIR_CLOCK 1 106 107 #define setsoftint() ienab_bis(IE_L1) 108 #define setsoftnet() (sir.sir_which[SIR_NET] = 1, setsoftint()) 109 #define setsoftclock() (sir.sir_which[SIR_CLOCK] = 1, setsoftint()) 110 111 int want_ast; 112 113 /* 114 * Preempt the current process if in interrupt from user mode, 115 * or after the current trap/syscall if in system mode. 116 */ 117 int want_resched; /* resched() was called */ 118 #define need_resched() (want_resched = 1, want_ast = 1) 119 120 /* 121 * Give a profiling tick to the current process when the user profiling 122 * buffer pages are invalid. On the sparc, request an ast to send us 123 * through trap(), marking the proc as needing a profiling tick. 124 */ 125 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 126 127 /* 128 * Notify the current process (p) that it has a signal pending, 129 * process as soon as possible. 130 */ 131 #define signotify(p) (want_ast = 1) 132 133 /* 134 * Only one process may own the FPU state. 135 * 136 * XXX this must be per-cpu (eventually) 137 */ 138 struct proc *fpproc; /* FPU owner */ 139 int foundfpu; /* true => we have an FPU */ 140 141 /* 142 * Interrupt handler chains. Interrupt handlers should return 0 for 143 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 144 * handler into the list. The handler is called with its (single) 145 * argument, or with a pointer to a clockframe if ih_arg is NULL. 146 */ 147 struct intrhand { 148 int (*ih_fun) __P((void *)); 149 void *ih_arg; 150 short ih_number; /* interrupt number the H/W provides */ 151 short ih_pil; /* interrupt priority */ 152 struct intrhand *ih_next; 153 u_int64_t *ih_map; /* Interrupt map register */ 154 u_int64_t *ih_clr; /* clear interrupt register */ 155 }; 156 extern struct intrhand *intrhand[15]; 157 extern struct intrhand *intrlev[MAXINTNUM]; 158 159 void intr_establish __P((int level, struct intrhand *)); 160 161 /* disksubr.c */ 162 struct dkbad; 163 int isbad __P((struct dkbad *bt, int, int, int)); 164 /* machdep.c */ 165 int ldcontrolb __P((caddr_t)); 166 void dumpconf __P((void)); 167 caddr_t reserve_dumppages __P((caddr_t)); 168 /* clock.c */ 169 struct timeval; 170 int tickintr __P((void *)); /* level 10 (tick) interrupt code */ 171 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 172 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 173 /* locore.s */ 174 struct fpstate; 175 void savefpstate __P((struct fpstate *)); 176 void loadfpstate __P((struct fpstate *)); 177 int probeget __P((paddr_t, int, int)); 178 int probeset __P((paddr_t, int, int, u_int64_t)); 179 #if 0 180 void write_all_windows __P((void)); 181 void write_user_windows __P((void)); 182 #else 183 #define write_all_windows() __asm __volatile("flushw" : : ) 184 #define write_user_windows() __asm __volatile("flushw" : : ) 185 #endif 186 void proc_trampoline __P((void)); 187 struct pcb; 188 void snapshot __P((struct pcb *)); 189 struct frame *getfp __P((void)); 190 int xldcontrolb __P((caddr_t, struct pcb *)); 191 void copywords __P((const void *, void *, size_t)); 192 void qcopy __P((const void *, void *, size_t)); 193 void qzero __P((void *, size_t)); 194 void switchtoctx __P((int)); 195 /* locore2.c */ 196 void remrq __P((struct proc *)); 197 /* trap.c */ 198 void kill_user_windows __P((struct proc *)); 199 int rwindow_save __P((struct proc *)); 200 void child_return __P((void *)); 201 /* amd7930intr.s */ 202 void amd7930_trap __P((void)); 203 /* cons.c */ 204 int cnrom __P((void)); 205 /* zs.c */ 206 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 207 #ifdef KGDB 208 void zs_kgdb_init __P((void)); 209 #endif 210 /* fb.c */ 211 void fb_unblank __P((void)); 212 /* kgdb_stub.c */ 213 #ifdef KGDB 214 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 215 void kgdb_connect __P((int)); 216 void kgdb_panic __P((void)); 217 #endif 218 /* emul.c */ 219 int fixalign __P((struct proc *, struct trapframe *)); 220 int emulinstr __P((vaddr_t, struct trapframe *)); 221 222 /* 223 * 224 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 225 * of the trap vector table. The next eight bits are supplied by the 226 * hardware when the trap occurs, and the bottom four bits are always 227 * zero (so that we can shove up to 16 bytes of executable code---exactly 228 * four instructions---into each trap vector). 229 * 230 * The hardware allocates half the trap vectors to hardware and half to 231 * software. 232 * 233 * Traps have priorities assigned (lower number => higher priority). 234 */ 235 236 struct trapvec { 237 int tv_instr[8]; /* the eight instructions */ 238 }; 239 extern struct trapvec *trapbase; /* the 256 vectors */ 240 241 extern void wzero __P((void *, u_int)); 242 extern void wcopy __P((const void *, void *, u_int)); 243 244 #endif /* _KERNEL */ 245 #endif /* _CPU_H_ */ 246
Indexes created Wed Sep 24 02:09:48 GMT 2025