cpu.h revision 1.15
1 /* $NetBSD: cpu.h,v 1.15 1999/12/30 16:26:18 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_MAXID 2 /* number of valid machdep ids */ 55 56 #define CTL_MACHDEP_NAMES { \ 57 { 0, 0 }, \ 58 { "booted_kernel", CTLTYPE_STRING }, \ 59 } 60 61 #ifdef _KERNEL 62 /* 63 * Exported definitions unique to SPARC cpu support. 64 */ 65 66 #include <machine/psl.h> 67 #include <machine/reg.h> 68 #include <machine/intr.h> 69 #include <sparc64/sparc64/intreg.h> 70 71 /* 72 * definitions of cpu-dependent requirements 73 * referenced in generic code 74 */ 75 #define cpu_swapin(p) /* nothing */ 76 #define cpu_swapout(p) /* nothing */ 77 #define cpu_wait(p) /* nothing */ 78 #define cpu_number() 0 79 80 /* 81 * Arguments to hardclock, softclock and gatherstats encapsulate the 82 * previous machine state in an opaque clockframe. The ipl is here 83 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 84 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 85 */ 86 extern int intstack[]; 87 extern int eintstack[]; 88 struct clockframe { 89 struct trapframe64 t; 90 }; 91 92 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 93 #define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0) 94 #define CLKF_PC(framep) ((framep)->t.tf_pc) 95 #define CLKF_INTR(framep) ((!CLKF_USERMODE(framep))&&\ 96 (((framep)->t.tf_kstack < (u_int)eintstack)&&\ 97 ((framep)->t.tf_kstack > (u_int)intstack))) 98 99 /* 100 * Software interrupt request `register'. 101 */ 102 union sir { 103 int sir_any; 104 char sir_which[4]; 105 } sir; 106 107 #define SIR_NET 0 108 #define SIR_CLOCK 1 109 110 #define setsoftint() ienab_bis(IE_L1) 111 #define setsoftnet() (sir.sir_which[SIR_NET] = 1, setsoftint()) 112 #define setsoftclock() (sir.sir_which[SIR_CLOCK] = 1, setsoftint()) 113 114 int want_ast; 115 116 /* 117 * Preempt the current process if in interrupt from user mode, 118 * or after the current trap/syscall if in system mode. 119 */ 120 int want_resched; /* resched() was called */ 121 #define need_resched() (want_resched = 1, want_ast = 1) 122 123 /* 124 * Give a profiling tick to the current process when the user profiling 125 * buffer pages are invalid. On the sparc, request an ast to send us 126 * through trap(), marking the proc as needing a profiling tick. 127 */ 128 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 129 130 /* 131 * Notify the current process (p) that it has a signal pending, 132 * process as soon as possible. 133 */ 134 #define signotify(p) (want_ast = 1) 135 136 /* 137 * Only one process may own the FPU state. 138 * 139 * XXX this must be per-cpu (eventually) 140 */ 141 struct proc *fpproc; /* FPU owner */ 142 int foundfpu; /* true => we have an FPU */ 143 144 /* 145 * Interrupt handler chains. Interrupt handlers should return 0 for 146 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 147 * handler into the list. The handler is called with its (single) 148 * argument, or with a pointer to a clockframe if ih_arg is NULL. 149 */ 150 struct intrhand { 151 int (*ih_fun) __P((void *)); 152 void *ih_arg; 153 short ih_number; /* interrupt number the H/W provides */ 154 short ih_pil; /* interrupt priority */ 155 struct intrhand *ih_next; 156 u_int64_t *ih_map; /* Interrupt map register */ 157 u_int64_t *ih_clr; /* clear interrupt register */ 158 }; 159 extern struct intrhand *intrhand[15]; 160 extern struct intrhand *intrlev[MAXINTNUM]; 161 162 void intr_establish __P((int level, struct intrhand *)); 163 164 /* disksubr.c */ 165 struct dkbad; 166 int isbad __P((struct dkbad *bt, int, int, int)); 167 /* machdep.c */ 168 int ldcontrolb __P((caddr_t)); 169 void dumpconf __P((void)); 170 caddr_t reserve_dumppages __P((caddr_t)); 171 /* clock.c */ 172 struct timeval; 173 int tickintr __P((void *)); /* level 10 (tick) interrupt code */ 174 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 175 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 176 /* locore.s */ 177 struct fpstate64; 178 void savefpstate __P((struct fpstate64 *)); 179 void loadfpstate __P((struct fpstate64 *)); 180 int probeget __P((paddr_t, int, int)); 181 int probeset __P((paddr_t, int, int, u_int64_t)); 182 #if 0 183 void write_all_windows __P((void)); 184 void write_user_windows __P((void)); 185 #else 186 #define write_all_windows() __asm __volatile("flushw" : : ) 187 #define write_user_windows() __asm __volatile("flushw" : : ) 188 #endif 189 void proc_trampoline __P((void)); 190 struct pcb; 191 void snapshot __P((struct pcb *)); 192 struct frame *getfp __P((void)); 193 int xldcontrolb __P((caddr_t, struct pcb *)); 194 void copywords __P((const void *, void *, size_t)); 195 void qcopy __P((const void *, void *, size_t)); 196 void qzero __P((void *, size_t)); 197 void switchtoctx __P((int)); 198 /* locore2.c */ 199 void remrq __P((struct proc *)); 200 /* trap.c */ 201 void kill_user_windows __P((struct proc *)); 202 int rwindow_save __P((struct proc *)); 203 void child_return __P((void *)); 204 /* amd7930intr.s */ 205 void amd7930_trap __P((void)); 206 /* cons.c */ 207 int cnrom __P((void)); 208 /* zs.c */ 209 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 210 #ifdef KGDB 211 void zs_kgdb_init __P((void)); 212 #endif 213 /* fb.c */ 214 void fb_unblank __P((void)); 215 /* kgdb_stub.c */ 216 #ifdef KGDB 217 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 218 void kgdb_connect __P((int)); 219 void kgdb_panic __P((void)); 220 #endif 221 /* emul.c */ 222 int fixalign __P((struct proc *, struct trapframe64 *)); 223 int emulinstr __P((vaddr_t, struct trapframe64 *)); 224 225 /* 226 * 227 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 228 * of the trap vector table. The next eight bits are supplied by the 229 * hardware when the trap occurs, and the bottom four bits are always 230 * zero (so that we can shove up to 16 bytes of executable code---exactly 231 * four instructions---into each trap vector). 232 * 233 * The hardware allocates half the trap vectors to hardware and half to 234 * software. 235 * 236 * Traps have priorities assigned (lower number => higher priority). 237 */ 238 239 struct trapvec { 240 int tv_instr[8]; /* the eight instructions */ 241 }; 242 extern struct trapvec *trapbase; /* the 256 vectors */ 243 244 extern void wzero __P((void *, u_int)); 245 extern void wcopy __P((const void *, void *, u_int)); 246 247 #endif /* _KERNEL */ 248 #endif /* _CPU_H_ */ 249
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