cpu.h revision 1.18
1 /* $NetBSD: cpu.h,v 1.18 2000/06/12 05:29:43 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_MAXID 2 /* number of valid machdep ids */ 55 56 #define CTL_MACHDEP_NAMES { \ 57 { 0, 0 }, \ 58 { "booted_kernel", CTLTYPE_STRING }, \ 59 } 60 61 #ifdef _KERNEL 62 /* 63 * Exported definitions unique to SPARC cpu support. 64 */ 65 66 #if !defined(_LKM) 67 #include "opt_multiprocessor.h" 68 #include "opt_lockdebug.h" 69 #endif 70 71 #include <machine/psl.h> 72 #include <machine/reg.h> 73 #include <machine/intr.h> 74 #include <sparc64/sparc64/intreg.h> 75 76 #include <sys/sched.h> 77 struct cpu_info { 78 struct schedstate_percpu ci_schedstate; /* scheduler state */ 79 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 80 u_long ci_spin_locks; /* # of spin locks held */ 81 u_long ci_simple_locks; /* # of simple locks held */ 82 #endif 83 }; 84 85 extern struct cpu_info cpu_info_store; 86 87 #define curcpu() (&cpu_info_store) 88 89 /* 90 * definitions of cpu-dependent requirements 91 * referenced in generic code 92 */ 93 #define cpu_swapin(p) /* nothing */ 94 #define cpu_swapout(p) /* nothing */ 95 #define cpu_wait(p) /* nothing */ 96 #define cpu_number() 0 97 98 /* 99 * Arguments to hardclock, softclock and gatherstats encapsulate the 100 * previous machine state in an opaque clockframe. The ipl is here 101 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 102 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 103 */ 104 extern int intstack[]; 105 extern int eintstack[]; 106 struct clockframe { 107 struct trapframe64 t; 108 }; 109 110 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 111 #define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0) 112 #define CLKF_PC(framep) ((framep)->t.tf_pc) 113 #define CLKF_INTR(framep) ((!CLKF_USERMODE(framep))&&\ 114 (((framep)->t.tf_kstack < (u_int)eintstack)&&\ 115 ((framep)->t.tf_kstack > (u_int)intstack))) 116 117 /* 118 * Software interrupt request `register'. 119 */ 120 union sir { 121 int sir_any; 122 char sir_which[4]; 123 } sir; 124 125 #define SIR_NET 0 126 #define SIR_CLOCK 1 127 128 extern struct intrhand soft01intr, soft01net, soft01clock; 129 130 #if 0 131 #define setsoftint() send_softint(-1, IPL_SOFTINT, &soft01intr) 132 #define setsoftnet() send_softint(-1, IPL_SOFTNET, &soft01net) 133 #define setsoftclock() send_softint(-1, IPL_SOFTCLOCK, &soft01clock) 134 #else 135 void setsoftint __P((void)); 136 void setsoftnet __P((void)); 137 void setsoftclock __P((void)); 138 #endif 139 140 int want_ast; 141 142 /* 143 * Preempt the current process if in interrupt from user mode, 144 * or after the current trap/syscall if in system mode. 145 */ 146 int want_resched; /* resched() was called */ 147 #define need_resched() (want_resched = 1, want_ast = 1) 148 149 /* 150 * Give a profiling tick to the current process when the user profiling 151 * buffer pages are invalid. On the sparc, request an ast to send us 152 * through trap(), marking the proc as needing a profiling tick. 153 */ 154 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 155 156 /* 157 * Notify the current process (p) that it has a signal pending, 158 * process as soon as possible. 159 */ 160 #define signotify(p) (want_ast = 1) 161 162 /* 163 * Only one process may own the FPU state. 164 * 165 * XXX this must be per-cpu (eventually) 166 */ 167 struct proc *fpproc; /* FPU owner */ 168 int foundfpu; /* true => we have an FPU */ 169 170 /* 171 * Interrupt handler chains. Interrupt handlers should return 0 for 172 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 173 * handler into the list. The handler is called with its (single) 174 * argument, or with a pointer to a clockframe if ih_arg is NULL. 175 */ 176 struct intrhand { 177 int (*ih_fun) __P((void *)); 178 void *ih_arg; 179 short ih_number; /* interrupt number */ 180 /* the H/W provides */ 181 short ih_pil; /* interrupt priority */ 182 struct intrhand *ih_next; 183 volatile u_int64_t *ih_map; /* Interrupt map reg */ 184 volatile u_int64_t *ih_clr; /* clear interrupt reg */ 185 }; 186 extern struct intrhand *intrhand[15]; 187 extern struct intrhand *intrlev[MAXINTNUM]; 188 189 void intr_establish __P((int level, struct intrhand *)); 190 191 /* disksubr.c */ 192 struct dkbad; 193 int isbad __P((struct dkbad *bt, int, int, int)); 194 /* machdep.c */ 195 int ldcontrolb __P((caddr_t)); 196 void dumpconf __P((void)); 197 caddr_t reserve_dumppages __P((caddr_t)); 198 /* clock.c */ 199 struct timeval; 200 int tickintr __P((void *)); /* level 10 (tick) interrupt code */ 201 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 202 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 203 /* locore.s */ 204 struct fpstate64; 205 void savefpstate __P((struct fpstate64 *)); 206 void loadfpstate __P((struct fpstate64 *)); 207 int probeget __P((paddr_t, int, int)); 208 int probeset __P((paddr_t, int, int, u_int64_t)); 209 #if 0 210 void write_all_windows __P((void)); 211 void write_user_windows __P((void)); 212 #else 213 #define write_all_windows() __asm __volatile("flushw" : : ) 214 #define write_user_windows() __asm __volatile("flushw" : : ) 215 #endif 216 void proc_trampoline __P((void)); 217 struct pcb; 218 void snapshot __P((struct pcb *)); 219 struct frame *getfp __P((void)); 220 int xldcontrolb __P((caddr_t, struct pcb *)); 221 void copywords __P((const void *, void *, size_t)); 222 void qcopy __P((const void *, void *, size_t)); 223 void qzero __P((void *, size_t)); 224 void switchtoctx __P((int)); 225 /* locore2.c */ 226 void remrq __P((struct proc *)); 227 /* trap.c */ 228 void kill_user_windows __P((struct proc *)); 229 int rwindow_save __P((struct proc *)); 230 void child_return __P((void *)); 231 /* amd7930intr.s */ 232 void amd7930_trap __P((void)); 233 /* cons.c */ 234 int cnrom __P((void)); 235 /* zs.c */ 236 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 237 #ifdef KGDB 238 void zs_kgdb_init __P((void)); 239 #endif 240 /* fb.c */ 241 void fb_unblank __P((void)); 242 /* kgdb_stub.c */ 243 #ifdef KGDB 244 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 245 void kgdb_connect __P((int)); 246 void kgdb_panic __P((void)); 247 #endif 248 /* emul.c */ 249 int fixalign __P((struct proc *, struct trapframe64 *)); 250 int emulinstr __P((vaddr_t, struct trapframe64 *)); 251 252 /* 253 * 254 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 255 * of the trap vector table. The next eight bits are supplied by the 256 * hardware when the trap occurs, and the bottom four bits are always 257 * zero (so that we can shove up to 16 bytes of executable code---exactly 258 * four instructions---into each trap vector). 259 * 260 * The hardware allocates half the trap vectors to hardware and half to 261 * software. 262 * 263 * Traps have priorities assigned (lower number => higher priority). 264 */ 265 266 struct trapvec { 267 int tv_instr[8]; /* the eight instructions */ 268 }; 269 extern struct trapvec *trapbase; /* the 256 vectors */ 270 271 extern void wzero __P((void *, u_int)); 272 extern void wcopy __P((const void *, void *, u_int)); 273 274 #endif /* _KERNEL */ 275 #endif /* _CPU_H_ */ 276
Indexes created Fri Sep 26 20:09:58 GMT 2025