cpu.h revision 1.26
1 /* $NetBSD: cpu.h,v 1.26 2000/09/29 17:02:38 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_MAXID 2 /* number of valid machdep ids */ 55 56 #define CTL_MACHDEP_NAMES { \ 57 { 0, 0 }, \ 58 { "booted_kernel", CTLTYPE_STRING }, \ 59 } 60 61 #ifdef _KERNEL 62 /* 63 * Exported definitions unique to SPARC cpu support. 64 */ 65 66 #if !defined(_LKM) 67 #include "opt_multiprocessor.h" 68 #include "opt_lockdebug.h" 69 #endif 70 71 #include <machine/psl.h> 72 #include <machine/reg.h> 73 #include <machine/intr.h> 74 #include <sparc64/sparc64/intreg.h> 75 76 #include <sys/sched.h> 77 /* 78 * The cpu_info structure is part of a 64KB structure mapped both the kernel 79 * pmap and a single locked TTE a CPUINFO_VA for that particular processor. 80 * Each processor's cpu_info is accessible at CPUINFO_VA only for that 81 * processor. Other processors can access that through an additional mapping 82 * in the kernel pmap. 83 * 84 * The 64KB page contains: 85 * 86 * cpu_info 87 * interrupt stack (all remaining space) 88 * idle PCB 89 * idle stack (STACKSPACE - sizeof(PCB)) 90 * 32KB TSB 91 */ 92 93 struct cpu_info { 94 /* Most important fields first */ 95 struct proc *ci_curproc; 96 struct pcb *ci_cpcb; /* also initial stack */ 97 struct cpu_info *ci_next; 98 99 struct proc *ci_fpproc; 100 int ci_number; 101 int ci_upaid; 102 struct schedstate_percpu ci_schedstate; /* scheduler state */ 103 104 /* DEBUG/DIAGNOSTIC stuff */ 105 u_long ci_spin_locks; /* # of spin locks held */ 106 u_long ci_simple_locks;/* # of simple locks held */ 107 108 /* Spinning up the CPU */ 109 void (*ci_spinup) __P((void)); /* spinup routine */ 110 void *ci_initstack; 111 paddr_t ci_paddr; /* Phys addr of this structure. */ 112 }; 113 114 extern struct cpu_info *cpus; 115 extern struct cpu_info cpu_info_store; 116 117 #if 1 118 #define curcpu() (&cpu_info_store) 119 #else 120 #define curcpu() ((struct cpu_info *)CPUINFO_VA) 121 #endif 122 123 /* 124 * definitions of cpu-dependent requirements 125 * referenced in generic code 126 */ 127 #define cpu_swapin(p) /* nothing */ 128 #define cpu_swapout(p) /* nothing */ 129 #define cpu_wait(p) /* nothing */ 130 #if 1 131 #define cpu_number() 0 132 #else 133 #define cpu_number() (curcpu()->ci_number) 134 #endif 135 136 /* 137 * Arguments to hardclock, softclock and gatherstats encapsulate the 138 * previous machine state in an opaque clockframe. The ipl is here 139 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 140 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 141 */ 142 extern int intstack[]; 143 extern int eintstack[]; 144 struct clockframe { 145 struct trapframe64 t; 146 }; 147 148 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 149 #define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0) 150 #define CLKF_PC(framep) ((framep)->t.tf_pc) 151 #define CLKF_INTR(framep) ((!CLKF_USERMODE(framep))&&\ 152 (((framep)->t.tf_kstack < (vaddr_t)EINTSTACK)&&\ 153 ((framep)->t.tf_kstack > (vaddr_t)INTSTACK))) 154 155 /* 156 * Software interrupt request `register'. 157 */ 158 #ifdef DEPRECATED 159 union sir { 160 int sir_any; 161 char sir_which[4]; 162 } sir; 163 164 #define SIR_NET 0 165 #define SIR_CLOCK 1 166 #endif 167 168 extern struct intrhand soft01intr, soft01net, soft01clock; 169 170 #if 0 171 #define setsoftint() send_softint(-1, IPL_SOFTINT, &soft01intr) 172 #define setsoftnet() send_softint(-1, IPL_SOFTNET, &soft01net) 173 #define setsoftclock() send_softint(-1, IPL_SOFTCLOCK, &soft01clock) 174 #else 175 void setsoftint __P((void)); 176 void setsoftnet __P((void)); 177 void setsoftclock __P((void)); 178 #endif 179 180 int want_ast; 181 182 /* 183 * Preempt the current process if in interrupt from user mode, 184 * or after the current trap/syscall if in system mode. 185 */ 186 int want_resched; /* resched() was called */ 187 #define need_resched(ci) (want_resched = 1, want_ast = 1) 188 189 /* 190 * Give a profiling tick to the current process when the user profiling 191 * buffer pages are invalid. On the sparc, request an ast to send us 192 * through trap(), marking the proc as needing a profiling tick. 193 */ 194 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 195 196 /* 197 * Notify the current process (p) that it has a signal pending, 198 * process as soon as possible. 199 */ 200 #define signotify(p) (want_ast = 1) 201 202 /* 203 * Only one process may own the FPU state. 204 * 205 * XXX this must be per-cpu (eventually) 206 */ 207 struct proc *fpproc; /* FPU owner */ 208 int foundfpu; /* true => we have an FPU */ 209 210 /* 211 * Interrupt handler chains. Interrupt handlers should return 0 for 212 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 213 * handler into the list. The handler is called with its (single) 214 * argument, or with a pointer to a clockframe if ih_arg is NULL. 215 */ 216 struct intrhand { 217 int (*ih_fun) __P((void *)); 218 void *ih_arg; 219 short ih_number; /* interrupt number */ 220 /* the H/W provides */ 221 char ih_pil; /* interrupt priority */ 222 struct intrhand *ih_next; /* global list */ 223 struct intrhand *ih_pending; /* interrupt queued */ 224 volatile u_int64_t *ih_map; /* Interrupt map reg */ 225 volatile u_int64_t *ih_clr; /* clear interrupt reg */ 226 }; 227 extern struct intrhand *intrhand[15]; 228 extern struct intrhand *intrlev[MAXINTNUM]; 229 230 void intr_establish __P((int level, struct intrhand *)); 231 232 /* cpu.c */ 233 paddr_t cpu_alloc __P((void)); 234 u_int64_t cpu_init __P((paddr_t, int)); 235 /* disksubr.c */ 236 struct dkbad; 237 int isbad __P((struct dkbad *bt, int, int, int)); 238 /* machdep.c */ 239 int ldcontrolb __P((caddr_t)); 240 void dumpconf __P((void)); 241 caddr_t reserve_dumppages __P((caddr_t)); 242 /* clock.c */ 243 struct timeval; 244 int tickintr __P((void *)); /* level 10 (tick) interrupt code */ 245 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 246 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 247 /* locore.s */ 248 struct fpstate64; 249 void savefpstate __P((struct fpstate64 *)); 250 void loadfpstate __P((struct fpstate64 *)); 251 u_int64_t probeget __P((paddr_t, int, int)); 252 int probeset __P((paddr_t, int, int, u_int64_t)); 253 #if 0 254 void write_all_windows __P((void)); 255 void write_user_windows __P((void)); 256 #else 257 #define write_all_windows() __asm __volatile("flushw" : : ) 258 #define write_user_windows() __asm __volatile("flushw" : : ) 259 #endif 260 void proc_trampoline __P((void)); 261 struct pcb; 262 void snapshot __P((struct pcb *)); 263 struct frame *getfp __P((void)); 264 int xldcontrolb __P((caddr_t, struct pcb *)); 265 void copywords __P((const void *, void *, size_t)); 266 void qcopy __P((const void *, void *, size_t)); 267 void qzero __P((void *, size_t)); 268 void switchtoctx __P((int)); 269 /* locore2.c */ 270 void remrq __P((struct proc *)); 271 /* trap.c */ 272 void kill_user_windows __P((struct proc *)); 273 int rwindow_save __P((struct proc *)); 274 void child_return __P((void *)); 275 /* amd7930intr.s */ 276 void amd7930_trap __P((void)); 277 /* cons.c */ 278 int cnrom __P((void)); 279 /* zs.c */ 280 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 281 #ifdef KGDB 282 void zs_kgdb_init __P((void)); 283 #endif 284 /* fb.c */ 285 void fb_unblank __P((void)); 286 /* kgdb_stub.c */ 287 #ifdef KGDB 288 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 289 void kgdb_connect __P((int)); 290 void kgdb_panic __P((void)); 291 #endif 292 /* emul.c */ 293 int fixalign __P((struct proc *, struct trapframe64 *)); 294 int emulinstr __P((vaddr_t, struct trapframe64 *)); 295 296 /* 297 * 298 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 299 * of the trap vector table. The next eight bits are supplied by the 300 * hardware when the trap occurs, and the bottom four bits are always 301 * zero (so that we can shove up to 16 bytes of executable code---exactly 302 * four instructions---into each trap vector). 303 * 304 * The hardware allocates half the trap vectors to hardware and half to 305 * software. 306 * 307 * Traps have priorities assigned (lower number => higher priority). 308 */ 309 310 struct trapvec { 311 int tv_instr[8]; /* the eight instructions */ 312 }; 313 extern struct trapvec *trapbase; /* the 256 vectors */ 314 315 extern void wzero __P((void *, u_int)); 316 extern void wcopy __P((const void *, void *, u_int)); 317 318 #endif /* _KERNEL */ 319 #endif /* _CPU_H_ */ 320
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