cpu.h revision 1.33
1 /* $NetBSD: cpu.h,v 1.33 2002/11/27 18:00:28 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 55 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 56 #define CPU_ARCH 4 /* integer: cpu architecture version */ 57 #define CPU_MAXID 5 /* number of valid machdep ids */ 58 59 #define CTL_MACHDEP_NAMES { \ 60 { 0, 0 }, \ 61 { "booted_kernel", CTLTYPE_STRING }, \ 62 { "booted_device", CTLTYPE_STRING }, \ 63 { "boot_args", CTLTYPE_STRING }, \ 64 { "cpu_arch", CTLTYPE_INT }, \ 65 } 66 67 #ifdef _KERNEL 68 /* 69 * Exported definitions unique to SPARC cpu support. 70 */ 71 72 #if !defined(_LKM) 73 #include "opt_multiprocessor.h" 74 #include "opt_lockdebug.h" 75 #endif 76 77 #include <machine/psl.h> 78 #include <machine/reg.h> 79 #include <machine/intr.h> 80 #include <sparc64/sparc64/intreg.h> 81 82 #include <sys/sched.h> 83 /* 84 * The cpu_info structure is part of a 64KB structure mapped both the kernel 85 * pmap and a single locked TTE a CPUINFO_VA for that particular processor. 86 * Each processor's cpu_info is accessible at CPUINFO_VA only for that 87 * processor. Other processors can access that through an additional mapping 88 * in the kernel pmap. 89 * 90 * The 64KB page contains: 91 * 92 * cpu_info 93 * interrupt stack (all remaining space) 94 * idle PCB 95 * idle stack (STACKSPACE - sizeof(PCB)) 96 * 32KB TSB 97 */ 98 99 struct cpu_info { 100 /* Most important fields first */ 101 struct proc *ci_curproc; 102 struct pcb *ci_cpcb; 103 struct cpu_info *ci_next; 104 105 struct proc *ci_fpproc; 106 int ci_number; 107 int ci_upaid; 108 struct schedstate_percpu ci_schedstate; 109 110 /* DEBUG/DIAGNOSTIC stuff */ 111 u_long ci_spin_locks; 112 u_long ci_simple_locks; 113 114 /* Spinning up the CPU */ 115 void (*ci_spinup) __P((void)); 116 void *ci_initstack; 117 paddr_t ci_paddr; 118 }; 119 120 extern struct cpu_info *cpus; 121 extern struct cpu_info cpu_info_store; 122 123 #if 1 124 #define curcpu() (&cpu_info_store) 125 #else 126 #define curcpu() ((struct cpu_info *)CPUINFO_VA) 127 #endif 128 129 /* 130 * definitions of cpu-dependent requirements 131 * referenced in generic code 132 */ 133 #define cpu_swapin(p) /* nothing */ 134 #define cpu_swapout(p) /* nothing */ 135 #define cpu_wait(p) /* nothing */ 136 #if 1 137 #define cpu_number() 0 138 #else 139 #define cpu_number() (curcpu()->ci_number) 140 #endif 141 142 /* 143 * Arguments to hardclock, softclock and gatherstats encapsulate the 144 * previous machine state in an opaque clockframe. The ipl is here 145 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 146 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 147 */ 148 extern int intstack[]; 149 extern int eintstack[]; 150 struct clockframe { 151 struct trapframe64 t; 152 }; 153 154 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 155 /* 156 * XXX Disable CLKF_BASEPRI() for now. If we use a counter-timer for 157 * the clock, the interrupt remains blocked until the interrupt handler 158 * returns and we write to the clear interrupt register. If we use 159 * %tick for the clock, we could get multiple interrupts, but the 160 * currently enabled INTR_INTERLOCK will prevent the interrupt from being 161 * posted twice anyway. 162 * 163 * Switching to %tick for all machines and disabling INTR_INTERLOCK 164 * in locore.s would allow us to take advantage of CLKF_BASEPRI(). 165 */ 166 #if 0 167 #define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0) 168 #else 169 #define CLKF_BASEPRI(framep) (0) 170 #endif 171 #define CLKF_PC(framep) ((framep)->t.tf_pc) 172 /* Since some files in sys/kern do not know BIAS, I'm using 0x7ff here */ 173 #define CLKF_INTR(framep) \ 174 ((!CLKF_USERMODE(framep))&& \ 175 (((framep)->t.tf_out[6] & 1 ) ? \ 176 (((vaddr_t)(framep)->t.tf_out[6] < \ 177 (vaddr_t)EINTSTACK-0x7ff) && \ 178 ((vaddr_t)(framep)->t.tf_out[6] > \ 179 (vaddr_t)INTSTACK-0x7ff)) : \ 180 (((vaddr_t)(framep)->t.tf_out[6] < \ 181 (vaddr_t)EINTSTACK) && \ 182 ((vaddr_t)(framep)->t.tf_out[6] > \ 183 (vaddr_t)INTSTACK)))) 184 185 /* 186 * Software interrupt request `register'. 187 */ 188 #ifdef DEPRECATED 189 union sir { 190 int sir_any; 191 char sir_which[4]; 192 } sir; 193 194 #define SIR_NET 0 195 #define SIR_CLOCK 1 196 #endif 197 198 extern struct intrhand soft01intr, soft01net, soft01clock; 199 200 #if 0 201 #define setsoftint() send_softint(-1, IPL_SOFTINT, &soft01intr) 202 #define setsoftnet() send_softint(-1, IPL_SOFTNET, &soft01net) 203 #else 204 void setsoftint __P((void)); 205 void setsoftnet __P((void)); 206 #endif 207 208 int want_ast; 209 210 /* 211 * Preempt the current process if in interrupt from user mode, 212 * or after the current trap/syscall if in system mode. 213 */ 214 int want_resched; /* resched() was called */ 215 #define need_resched(ci) (want_resched = 1, want_ast = 1) 216 217 /* 218 * Give a profiling tick to the current process when the user profiling 219 * buffer pages are invalid. On the sparc, request an ast to send us 220 * through trap(), marking the proc as needing a profiling tick. 221 */ 222 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 223 224 /* 225 * Notify the current process (p) that it has a signal pending, 226 * process as soon as possible. 227 */ 228 #define signotify(p) (want_ast = 1) 229 230 /* 231 * Only one process may own the FPU state. 232 * 233 * XXX this must be per-cpu (eventually) 234 */ 235 struct proc *fpproc; /* FPU owner */ 236 237 /* 238 * Interrupt handler chains. Interrupt handlers should return 0 for 239 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 240 * handler into the list. The handler is called with its (single) 241 * argument, or with a pointer to a clockframe if ih_arg is NULL. 242 */ 243 struct intrhand { 244 int (*ih_fun) __P((void *)); 245 void *ih_arg; 246 short ih_number; /* interrupt number */ 247 /* the H/W provides */ 248 char ih_pil; /* interrupt priority */ 249 struct intrhand *ih_next; /* global list */ 250 struct intrhand *ih_pending; /* interrupt queued */ 251 volatile u_int64_t *ih_map; /* Interrupt map reg */ 252 volatile u_int64_t *ih_clr; /* clear interrupt reg */ 253 }; 254 extern struct intrhand *intrhand[]; 255 extern struct intrhand *intrlev[MAXINTNUM]; 256 257 void intr_establish __P((int level, struct intrhand *)); 258 259 /* cpu.c */ 260 paddr_t cpu_alloc __P((void)); 261 u_int64_t cpu_init __P((paddr_t, int)); 262 /* disksubr.c */ 263 struct dkbad; 264 int isbad __P((struct dkbad *bt, int, int, int)); 265 /* machdep.c */ 266 int ldcontrolb __P((caddr_t)); 267 void dumpconf __P((void)); 268 caddr_t reserve_dumppages __P((caddr_t)); 269 /* clock.c */ 270 struct timeval; 271 int tickintr __P((void *)); /* level 10 (tick) interrupt code */ 272 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 273 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 274 /* locore.s */ 275 struct fpstate64; 276 void savefpstate __P((struct fpstate64 *)); 277 void loadfpstate __P((struct fpstate64 *)); 278 u_int64_t probeget __P((paddr_t, int, int)); 279 int probeset __P((paddr_t, int, int, u_int64_t)); 280 #if 0 281 void write_all_windows __P((void)); 282 void write_user_windows __P((void)); 283 #else 284 #define write_all_windows() __asm __volatile("flushw" : : ) 285 #define write_user_windows() __asm __volatile("flushw" : : ) 286 #endif 287 void proc_trampoline __P((void)); 288 struct pcb; 289 void snapshot __P((struct pcb *)); 290 struct frame *getfp __P((void)); 291 int xldcontrolb __P((caddr_t, struct pcb *)); 292 void copywords __P((const void *, void *, size_t)); 293 void qcopy __P((const void *, void *, size_t)); 294 void qzero __P((void *, size_t)); 295 void switchtoctx __P((int)); 296 /* locore2.c */ 297 void remrq __P((struct proc *)); 298 /* trap.c */ 299 void kill_user_windows __P((struct proc *)); 300 int rwindow_save __P((struct proc *)); 301 /* amd7930intr.s */ 302 void amd7930_trap __P((void)); 303 /* cons.c */ 304 int cnrom __P((void)); 305 /* zs.c */ 306 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 307 #ifdef KGDB 308 void zs_kgdb_init __P((void)); 309 #endif 310 /* fb.c */ 311 void fb_unblank __P((void)); 312 /* kgdb_stub.c */ 313 #ifdef KGDB 314 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 315 void kgdb_connect __P((int)); 316 void kgdb_panic __P((void)); 317 #endif 318 /* emul.c */ 319 int fixalign __P((struct proc *, struct trapframe64 *)); 320 int emulinstr __P((vaddr_t, struct trapframe64 *)); 321 322 /* 323 * 324 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 325 * of the trap vector table. The next eight bits are supplied by the 326 * hardware when the trap occurs, and the bottom four bits are always 327 * zero (so that we can shove up to 16 bytes of executable code---exactly 328 * four instructions---into each trap vector). 329 * 330 * The hardware allocates half the trap vectors to hardware and half to 331 * software. 332 * 333 * Traps have priorities assigned (lower number => higher priority). 334 */ 335 336 struct trapvec { 337 int tv_instr[8]; /* the eight instructions */ 338 }; 339 extern struct trapvec *trapbase; /* the 256 vectors */ 340 341 extern void wzero __P((void *, u_int)); 342 extern void wcopy __P((const void *, void *, u_int)); 343 344 #endif /* _KERNEL */ 345 #endif /* _CPU_H_ */ 346
Indexes created Mon Sep 29 18:09:42 GMT 2025