cpu.h revision 1.89
1 /* $NetBSD: cpu.h,v 1.89 2010/03/06 08:08:29 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_MAXID 5 /* number of valid machdep ids */ 54 55 #ifdef _KERNEL 56 /* 57 * Exported definitions unique to SPARC cpu support. 58 */ 59 60 #if defined(_KERNEL_OPT) 61 #include "opt_multiprocessor.h" 62 #include "opt_lockdebug.h" 63 #endif 64 65 #include <machine/psl.h> 66 #include <machine/reg.h> 67 #include <machine/pte.h> 68 #include <machine/intr.h> 69 #include <machine/cpuset.h> 70 #include <sparc64/sparc64/intreg.h> 71 72 #include <sys/cpu_data.h> 73 #include <sys/evcnt.h> 74 /* 75 * The cpu_info structure is part of a 64KB structure mapped both the kernel 76 * pmap and a single locked TTE a CPUINFO_VA for that particular processor. 77 * Each processor's cpu_info is accessible at CPUINFO_VA only for that 78 * processor. Other processors can access that through an additional mapping 79 * in the kernel pmap. 80 * 81 * The 64KB page contains: 82 * 83 * cpu_info 84 * interrupt stack (all remaining space) 85 * idle PCB 86 * idle stack (STACKSPACE - sizeof(PCB)) 87 * 32KB TSB 88 */ 89 90 struct cpu_info { 91 92 /* 93 * SPARC cpu_info structures live at two VAs: one global 94 * VA (so each CPU can access any other CPU's cpu_info) 95 * and an alias VA CPUINFO_VA which is the same on each 96 * CPU and maps to that CPU's cpu_info. Since the alias 97 * CPUINFO_VA is how we locate our cpu_info, we have to 98 * self-reference the global VA so that we can return it 99 * in the curcpu() macro. 100 */ 101 struct cpu_info * volatile ci_self; 102 103 /* Most important fields first */ 104 struct lwp *ci_curlwp; 105 struct pcb *ci_cpcb; 106 struct cpu_info *ci_next; 107 108 struct lwp *ci_fplwp; 109 110 void *ci_eintstack; 111 112 int ci_mtx_count; 113 int ci_mtx_oldspl; 114 115 /* Spinning up the CPU */ 116 void (*ci_spinup)(void); 117 paddr_t ci_paddr; 118 119 int ci_cpuid; 120 121 /* CPU PROM information. */ 122 u_int ci_node; 123 124 /* %tick and cpu frequency information */ 125 u_long ci_tick_increment; 126 uint64_t ci_cpu_clockrate[2]; 127 128 /* Interrupts */ 129 struct intrhand *ci_intrpending[16]; 130 struct intrhand *ci_tick_ih; 131 132 /* Event counters */ 133 struct evcnt ci_tick_evcnt; 134 135 /* This could be under MULTIPROCESSOR, but there's no good reason */ 136 struct evcnt ci_ipi_evcnt[IPI_EVCNT_NUM]; 137 138 int ci_flags; 139 int ci_want_ast; 140 int ci_want_resched; 141 int ci_idepth; 142 143 /* 144 * A context is simply a small number that differentiates multiple mappings 145 * of the same address. Contexts on the spitfire are 13 bits, but could 146 * be as large as 17 bits. 147 * 148 * Each context is either free or attached to a pmap. 149 * 150 * The context table is an array of pointers to psegs. Just dereference 151 * the right pointer and you get to the pmap segment tables. These are 152 * physical addresses, of course. 153 * 154 */ 155 int ci_pmap_next_ctx; 156 int ci_numctx; 157 paddr_t *ci_ctxbusy; 158 LIST_HEAD(, pmap) ci_pmap_ctxlist; 159 160 /* 161 * The TSBs are per cpu too (since MMU context differs between 162 * cpus). These are just caches for the TLBs. 163 */ 164 pte_t *ci_tsb_dmmu; 165 pte_t *ci_tsb_immu; 166 167 struct cpu_data ci_data; /* MI per-cpu data */ 168 169 volatile void *ci_ddb_regs; /* DDB regs */ 170 }; 171 172 #define CPUF_PRIMARY 1 173 174 /* 175 * CPU boot arguments. Used by secondary CPUs at the bootstrap time. 176 */ 177 struct cpu_bootargs { 178 u_int cb_node; /* PROM CPU node */ 179 volatile int cb_flags; 180 181 vaddr_t cb_ktext; 182 paddr_t cb_ktextp; 183 vaddr_t cb_ektext; 184 185 vaddr_t cb_kdata; 186 paddr_t cb_kdatap; 187 vaddr_t cb_ekdata; 188 189 paddr_t cb_cpuinfo; 190 }; 191 192 extern struct cpu_bootargs *cpu_args; 193 194 #if defined(MULTIPROCESSOR) 195 extern int sparc_ncpus; 196 #else 197 #define sparc_ncpus 1 198 #endif 199 200 extern struct cpu_info *cpus; 201 extern struct pool_cache *fpstate_cache; 202 203 #define curcpu() (((struct cpu_info *)CPUINFO_VA)->ci_self) 204 #define cpu_number() (curcpu()->ci_index) 205 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 206 207 #define CPU_INFO_ITERATOR int 208 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpus; ci != NULL; \ 209 ci = ci->ci_next 210 211 #define curlwp curcpu()->ci_curlwp 212 #define fplwp curcpu()->ci_fplwp 213 #define curpcb curcpu()->ci_cpcb 214 215 #define want_ast curcpu()->ci_want_ast 216 #define want_resched curcpu()->ci_want_resched 217 218 /* 219 * definitions of cpu-dependent requirements 220 * referenced in generic code 221 */ 222 #define cpu_wait(p) /* nothing */ 223 void cpu_proc_fork(struct proc *, struct proc *); 224 225 /* run on the cpu itself */ 226 void cpu_pmap_init(struct cpu_info *); 227 /* run upfront to prepare the cpu_info */ 228 void cpu_pmap_prepare(struct cpu_info *, bool); 229 230 #if defined(MULTIPROCESSOR) 231 extern vaddr_t cpu_spinup_trampoline; 232 233 extern char *mp_tramp_code; 234 extern u_long mp_tramp_code_len; 235 extern u_long mp_tramp_tlb_slots; 236 extern u_long mp_tramp_func; 237 extern u_long mp_tramp_ci; 238 239 void cpu_hatch(void); 240 void cpu_boot_secondary_processors(void); 241 242 /* 243 * Call a function on other cpus: 244 * multicast - send to everyone in the sparc64_cpuset_t 245 * broadcast - send to to all cpus but ourselves 246 * send - send to just this cpu 247 */ 248 typedef void (* ipifunc_t)(void *); 249 250 void sparc64_multicast_ipi(sparc64_cpuset_t, ipifunc_t, uint64_t, uint64_t); 251 void sparc64_broadcast_ipi(ipifunc_t, uint64_t, uint64_t); 252 void sparc64_send_ipi(int, ipifunc_t, uint64_t, uint64_t); 253 #endif 254 255 /* 256 * Arguments to hardclock, softclock and gatherstats encapsulate the 257 * previous machine state in an opaque clockframe. The ipl is here 258 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 259 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 260 */ 261 struct clockframe { 262 struct trapframe64 t; 263 }; 264 265 #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0) 266 #define CLKF_PC(framep) ((framep)->t.tf_pc) 267 /* Since some files in sys/kern do not know BIAS, I'm using 0x7ff here */ 268 #define CLKF_INTR(framep) \ 269 ((!CLKF_USERMODE(framep))&& \ 270 (((framep)->t.tf_out[6] & 1 ) ? \ 271 (((vaddr_t)(framep)->t.tf_out[6] < \ 272 (vaddr_t)EINTSTACK-0x7ff) && \ 273 ((vaddr_t)(framep)->t.tf_out[6] > \ 274 (vaddr_t)INTSTACK-0x7ff)) : \ 275 (((vaddr_t)(framep)->t.tf_out[6] < \ 276 (vaddr_t)EINTSTACK) && \ 277 ((vaddr_t)(framep)->t.tf_out[6] > \ 278 (vaddr_t)INTSTACK)))) 279 280 /* 281 * Give a profiling tick to the current process when the user profiling 282 * buffer pages are invalid. On the sparc, request an ast to send us 283 * through trap(), marking the proc as needing a profiling tick. 284 */ 285 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, want_ast = 1) 286 287 /* 288 * Notify an LWP that it has a signal pending, process as soon as possible. 289 */ 290 void cpu_signotify(struct lwp *); 291 292 /* 293 * Interrupt handler chains. Interrupt handlers should return 0 for 294 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 295 * handler into the list. The handler is called with its (single) 296 * argument, or with a pointer to a clockframe if ih_arg is NULL. 297 */ 298 struct intrhand { 299 int (*ih_fun)(void *); 300 void *ih_arg; 301 /* if we have to take the biglock, we interpose a wrapper 302 * and need to save the original function and arg */ 303 int (*ih_realfun)(void *); 304 void *ih_realarg; 305 short ih_number; /* interrupt number */ 306 /* the H/W provides */ 307 char ih_pil; /* interrupt priority */ 308 struct intrhand *ih_next; /* global list */ 309 struct intrhand *ih_pending; /* interrupt queued */ 310 volatile uint64_t *ih_map; /* Interrupt map reg */ 311 volatile uint64_t *ih_clr; /* clear interrupt reg */ 312 }; 313 extern struct intrhand *intrhand[]; 314 extern struct intrhand *intrlev[MAXINTNUM]; 315 316 void intr_establish(int level, bool mpsafe, struct intrhand *); 317 void *sparc_softintr_establish(int, int (*)(void *), void *); 318 void sparc_softintr_schedule(void *); 319 void sparc_softintr_disestablish(void *); 320 321 /* disksubr.c */ 322 struct dkbad; 323 int isbad(struct dkbad *bt, int, int, int); 324 /* machdep.c */ 325 void * reserve_dumppages(void *); 326 /* clock.c */ 327 struct timeval; 328 int tickintr(void *); /* level 10/14 (tick) interrupt code */ 329 int clockintr(void *); /* level 10 (clock) interrupt code */ 330 int statintr(void *); /* level 14 (statclock) interrupt code */ 331 int schedintr(void *); /* level 10 (schedclock) interrupt code */ 332 void tickintr_establish(int, int (*)(void *)); 333 /* locore.s */ 334 struct fpstate64; 335 void savefpstate(struct fpstate64 *); 336 void loadfpstate(struct fpstate64 *); 337 void clearfpstate(void); 338 uint64_t probeget(paddr_t, int, int); 339 int probeset(paddr_t, int, int, uint64_t); 340 341 #define write_all_windows() __asm volatile("flushw" : : ) 342 #define write_user_windows() __asm volatile("flushw" : : ) 343 344 struct pcb; 345 void snapshot(struct pcb *); 346 struct frame *getfp(void); 347 void switchtoctx_us(int); 348 void switchtoctx_usiii(int); 349 void next_tick(long); 350 /* trap.c */ 351 void kill_user_windows(struct lwp *); 352 int rwindow_save(struct lwp *); 353 /* cons.c */ 354 int cnrom(void); 355 /* zs.c */ 356 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int)); 357 /* fb.c */ 358 void fb_unblank(void); 359 /* kgdb_stub.c */ 360 #ifdef KGDB 361 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 362 void kgdb_connect(int); 363 void kgdb_panic(void); 364 #endif 365 /* emul.c */ 366 int fixalign(struct lwp *, struct trapframe64 *); 367 int emulinstr(vaddr_t, struct trapframe64 *); 368 369 #endif /* _KERNEL */ 370 #endif /* _CPU_H_ */ 371
Indexes created Mon Sep 29 03:10:08 GMT 2025