ctlreg.h revision 1.11
1 /* $NetBSD: ctlreg.h,v 1.11 1999/06/05 21:58:18 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 /* 27 * Sun 4u control registers. (includes address space definitions 28 * and some registers in control space). 29 */ 30 31 /* 32 * The Alternate address spaces. 33 * 34 * 0x00-0x7f are privileged 35 * 0x80-0xff can be used by users 36 */ 37 38 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 39 40 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 41 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 42 43 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 44 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 45 46 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 47 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 48 49 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 50 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 51 52 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 53 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 54 55 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 56 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 57 58 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 59 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 60 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 61 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 62 63 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 64 65 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 66 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 67 68 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 69 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 70 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 71 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 72 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 73 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 74 75 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 76 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 77 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 78 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 79 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 80 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 81 82 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 83 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 84 85 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 86 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 87 88 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 89 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 90 91 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 92 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 93 94 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 95 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 96 #define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */ 97 #define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */ 98 99 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 100 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 101 #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 102 #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 103 104 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 105 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 106 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 107 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 108 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 109 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 110 111 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 112 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 113 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 114 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 115 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 116 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 117 118 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 119 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 120 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 121 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 122 123 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 124 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 125 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 126 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 127 128 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 129 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 130 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 131 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 132 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 133 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 134 135 136 /* 137 * These are the shorter names used by Solaris 138 */ 139 140 #define ASI_N ASI_NUCLEUS 141 #define ASI_NL ASI_NUCLEUS_LITTLE 142 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 143 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 144 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 145 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 146 #define ASI_P ASI_PRIMARY 147 #define ASI_S ASI_SECONDARY 148 #define ASI_PNF ASI_PRIMARY_NO_FAULT 149 #define ASI_SNF ASI_SECONDARY_NO_FAULT 150 #define ASI_PL ASI_PRIMARY_LITTLE 151 #define ASI_SL ASI_SECONDARY_LITTLE 152 #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE 153 #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE 154 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 155 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 156 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 157 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 158 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 159 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 160 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 161 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 162 #define ASI_BLK_P ASI_BLOCK_PRIMARY 163 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 164 #define ASI_BLK_S ASI_BLOCK_SECONDARY 165 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 166 167 /* 168 * The following are 4u control registers 169 */ 170 171 /* 172 * [4u] MMU and Cache Control Register (MCCR) 173 * use ASI = 0x45 174 */ 175 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 176 #define MCCR 0x00 177 178 /* MCCR Bits and their meanings */ 179 #define MCCR_DMMU_EN 0x08 180 #define MCCR_IMMU_EN 0x04 181 #define MCCR_DCACHE_EN 0x02 182 #define MCCR_ICACHE_EN 0x01 183 184 185 /* 186 * MMU control registers 187 */ 188 189 /* Choose an MMU */ 190 #define ASI_DMMU 0x58 191 #define ASI_IMMU 0x50 192 193 /* Other assorted MMU ASIs */ 194 #define ASI_IMMU_8KPTR 0x51 195 #define ASI_IMMU_64KPTR 0x52 196 #define ASI_IMMU_DATA_IN 0x54 197 #define ASI_IMMU_TLB_DATA 0x55 198 #define ASI_IMMU_TLB_TAG 0x56 199 #define ASI_DMMU_8KPTR 0x59 200 #define ASI_DMMU_64KPTR 0x5a 201 #define ASI_DMMU_DATA_IN 0x5c 202 #define ASI_DMMU_TLB_DATA 0x5d 203 #define ASI_DMMU_TLB_TAG 0x5e 204 205 /* 206 * The following are the control registers 207 * They work on both MMUs unless noted. 208 * 209 * Register contents are defined later on individual registers. 210 */ 211 #define TSB_TAG_TARGET 0x0 212 #define TLB_DATA_IN 0x0 213 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 214 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 215 #define SFSR 0x18 216 #define SFAR 0x20 /* fault address -- DMMU only */ 217 #define TSB 0x28 218 #define TLB_TAG_ACCESS 0x30 219 #define VIRTUAL_WATCHPOINT 0x38 220 #define PHYSICAL_WATCHPOINT 0x40 221 222 /* Tag Target bits */ 223 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 224 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 225 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 226 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 227 228 /* SFSR bits for both D_SFSR and I_SFSR */ 229 #define SFSR_ASI(x) ((x)>>16) 230 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 231 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 232 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 233 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 234 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 235 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 236 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 237 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 238 #define SFSR_CTXT(x) (((x)>>4)&0x3) 239 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 240 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 241 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 242 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 243 #define SFSR_W 0x00004 /* DMMU: attempted write */ 244 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 245 #define SFSR_FV 0x00001 /* Fault is valid */ 246 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 247 248 #if 0 249 /* Old bits */ 250 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 251 #else 252 /* New bits */ 253 #define SFSR_BITS "\177\20" \ 254 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 255 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 256 #endif 257 258 /* ASFR bits */ 259 #define ASFR_ME 0x100000000LL 260 #define ASFR_PRIV 0x080000000LL 261 #define ASFR_ISAP 0x040000000LL 262 #define ASFR_ETP 0x020000000LL 263 #define ASFR_IVUE 0x010000000LL 264 #define ASFR_TO 0x008000000LL 265 #define ASFR_BERR 0x004000000LL 266 #define ASFR_LDP 0x002000000LL 267 #define ASFR_CP 0x001000000LL 268 #define ASFR_WP 0x000800000LL 269 #define ASFR_EDP 0x000400000LL 270 #define ASFR_UE 0x000200000LL 271 #define ASFR_CE 0x000100000LL 272 #define ASFR_ETS 0x0000f0000LL 273 #define ASFT_P_SYND 0x00000ffffLL 274 275 #define AFSR_BITS "\177\20" \ 276 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 277 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 278 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 279 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 280 281 /* 282 * Here's the spitfire TSB control register bits. 283 * 284 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 285 */ 286 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 287 #define TSB_SIZE_1K 0x01 288 #define TSB_SIZE_2K 0x02 289 #define TSB_SIZE_4K 0x03 290 #define TSB_SIZE_8K 0x04 291 #define TSB_SIZE_16K 0x05 292 #define TSB_SIZE_32K 0x06 293 #define TSB_SIZE_64K 0x07 294 #define TSB_SPLIT 0x1000 295 #define TSB_BASE 0xffffffffffffe000 296 297 /* TLB Tag Access bits */ 298 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 299 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 300 301 /* 302 * TLB demap registers. TTEs are defined in v9pte.h 303 * 304 * Use the address space to select between IMMU and DMMU. 305 * The address of the register selects which context register 306 * to read the ASI from. 307 * 308 * The data stored in the register is interpreted as the VA to 309 * use. The DEMAP_CTX_<> registers ignore the address and demap the 310 * entire ASI. 311 * 312 */ 313 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 314 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 315 316 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 317 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 318 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 319 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 320 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 321 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 322 323 /* 324 * Interrupt registers. This really gets hairy. 325 */ 326 327 /* IRSR -- Interrupt Receive Status Ragister */ 328 #define ASI_IRSR 0x49 329 #define IRSR 0x00 330 #define IRSR_BUSY 0x010 331 #define IRSR_MID(x) (x&0xf) 332 333 /* IRDR -- Interrupt Receive Data Registers */ 334 #define ASI_IRDR 0x7f 335 #define IRDR_0H 0x40 336 #define IRDR_0L 0x48 /* unimplemented */ 337 #define IRDR_1H 0x50 338 #define IRDR_1L 0x58 /* unimplemented */ 339 #define IRDR_2H 0x60 340 #define IRDR_2L 0x68 /* unimplemented */ 341 #define IRDR_3H 0x70 /* unimplemented */ 342 #define IRDR_3L 0x78 /* unimplemented */ 343 344 /* SOFTINT ASRs */ 345 #define SET_SOFTINT %asr20 /* Sets these bits */ 346 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 347 #define SOFTINT %asr22 /* Reads the register */ 348 #define TICK_CMPR %asr23 349 350 #define TICK_INT 0x01 /* level-14 clock tick */ 351 #define SOFTINT1 (0x1<<1) 352 #define SOFTINT2 (0x1<<2) 353 #define SOFTINT3 (0x1<<3) 354 #define SOFTINT4 (0x1<<4) 355 #define SOFTINT5 (0x1<<5) 356 #define SOFTINT6 (0x1<<6) 357 #define SOFTINT7 (0x1<<7) 358 #define SOFTINT8 (0x1<<8) 359 #define SOFTINT9 (0x1<<9) 360 #define SOFTINT10 (0x1<<10) 361 #define SOFTINT11 (0x1<<11) 362 #define SOFTINT12 (0x1<<12) 363 #define SOFTINT13 (0x1<<13) 364 #define SOFTINT14 (0x1<<14) 365 #define SOFTINT15 (0x1<<15) 366 367 /* Interrupt Dispatch -- usually reserved for cross-calls */ 368 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 369 #define IDSR 0x00 370 #define IDSR_NACK 0x02 371 #define IDSR_BUSY 0x01 372 373 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 374 #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */ 375 #define IDDR_0H 0x40 /* Store data to send in these regs */ 376 #define IDDR_0L 0x48 /* unimplemented */ 377 #define IDDR_1H 0x50 378 #define IDDR_1L 0x58 /* unimplemented */ 379 #define IDDR_2H 0x60 380 #define IDDR_2L 0x68 /* unimplemented */ 381 #define IDDR_3H 0x70 /* unimplemented */ 382 #define IDDR_3L 0x78 /* unimplemented */ 383 384 /* 385 * Error registers 386 */ 387 388 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 389 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 390 #define AFAR 0x00 391 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 392 #define AFSR 0x00 393 394 #define ASI_P_EER 0x4b /* Error enable register */ 395 #define P_EER 0x00 396 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 397 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 398 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 399 400 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 401 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 402 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 403 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 404 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 405 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 406 407 408 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 409 410 /* 411 * GCC __asm constructs for doing assembly stuff. 412 */ 413 414 /* 415 * ``Routines'' to load and store from/to alternate address space. 416 * The location can be a variable, the asi value (address space indicator) 417 * must be a constant. 418 * 419 * N.B.: You can put as many special functions here as you like, since 420 * they cost no kernel space or time if they are not used. 421 * 422 * These were static inline functions, but gcc screws up the constraints 423 * on the address space identifiers (the "n"umeric value part) because 424 * it inlines too late, so we have to use the funny valued-macro syntax. 425 */ 426 427 /* DCACHE_BUG forces a flush of the D$ line on every ASI load */ 428 #define DCACHE_BUG 429 430 #ifdef __arch64__ 431 /* load byte from alternate address space */ 432 #ifdef DCACHE_BUG 433 #define lduba(loc, asi) ({ \ 434 register int _lduba_v; \ 435 if (asi == ASI_PHYS_CACHED) { \ 436 __asm __volatile("wr %2,%%g0,%%asi; " \ 437 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 438 " lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \ 439 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 440 } else { \ 441 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \ 442 "r" ((long)(loc)), "r" (asi)); \ 443 } \ 444 _lduba_v; \ 445 }) 446 #else 447 #define lduba(loc, asi) ({ \ 448 register int _lduba_v; \ 449 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \ 450 "r" ((long)(loc)), "r" (asi)); \ 451 _lduba_v; \ 452 }) 453 #endif 454 #else 455 /* load byte from alternate address space */ 456 #ifdef DCACHE_BUG 457 #define lduba(loc, asi) ({ \ 458 register int _lduba_v, _loc_hi; \ 459 _loc_hi = (((u_int64_t)loc)>>32); \ 460 if (asi == ASI_PHYS_CACHED) { \ 461 __asm __volatile("wr %3,%%g0,%%asi; " \ 462 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ 463 " sllx %2,32,%0; or %0,%1,%0; membar #Sync; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 464 "r" ((long)(loc)), "r" (_loc_hi), \ 465 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 466 } else { \ 467 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 468 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 469 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 470 } \ 471 _lduba_v; \ 472 }) 473 #else 474 #define lduba(loc, asi) ({ \ 475 register int _lduba_v, _loc_hi; \ 476 _loc_hi = (((u_int64_t)loc)>>32); \ 477 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 478 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 479 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 480 _lduba_v; \ 481 }) 482 #endif 483 #endif 484 485 #ifdef __arch64__ 486 /* load half-word from alternate address space */ 487 #ifdef DCACHE_BUG 488 #define lduha(loc, asi) ({ \ 489 register int _lduha_v; \ 490 if (asi == ASI_PHYS_CACHED) { \ 491 __asm __volatile("wr %2,%%g0,%%asi; " \ 492 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 493 " lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \ 494 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 495 } else { \ 496 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 497 "r" ((long)(loc)), "r" (asi)); \ 498 } \ 499 _lduha_v; \ 500 }) 501 #else 502 #define lduha(loc, asi) ({ \ 503 register int _lduha_v; \ 504 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 505 "r" ((long)(loc)), "r" (asi)); \ 506 _lduha_v; \ 507 }) 508 #endif 509 #else 510 /* load half-word from alternate address space */ 511 #ifdef DCACHE_BUG 512 #define lduha(loc, asi) ({ \ 513 register int _lduha_v, _loc_hi; \ 514 _loc_hi = (((u_int64_t)loc)>>32); \ 515 if (asi == ASI_PHYS_CACHED) { \ 516 __asm __volatile("wr %3,%%g0,%%asi; " \ 517 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ 518 " sllx %2,32,%0; or %0,%1,%0; membar #Sync; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 519 "r" ((long)(loc)), "r" (_loc_hi), \ 520 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 521 } else { \ 522 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 523 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 524 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 525 } \ 526 _lduha_v; \ 527 }) 528 #else 529 #define lduha(loc, asi) ({ \ 530 register int _lduha_v, _loc_hi; \ 531 _loc_hi = (((u_int64_t)loc)>>32); \ 532 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 533 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 534 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 535 _lduha_v; \ 536 }) 537 #endif 538 #endif 539 540 #ifdef __arch64__ 541 /* load unsigned int from alternate address space */ 542 #ifdef DCACHE_BUG 543 #define lda(loc, asi) ({ \ 544 register int _lda_v; \ 545 if (asi == ASI_PHYS_CACHED) { \ 546 __asm __volatile("wr %2,%%g0,%%asi; " \ 547 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 548 " lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 549 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 550 } else { \ 551 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 552 "r" ((long)(loc)), "r" (asi)); \ 553 } \ 554 _lda_v; \ 555 }) 556 557 /* load signed int from alternate address space */ 558 #define ldswa(loc, asi) ({ \ 559 register int _lda_v; \ 560 if (asi == ASI_PHYS_CACHED) { \ 561 __asm __volatile("wr %2,%%g0,%%asi; " \ 562 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 563 " ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 564 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 565 } else { \ 566 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 567 "r" ((long)(loc)), "r" (asi)); \ 568 } \ 569 _lda_v; \ 570 }) 571 #else 572 #define lda(loc, asi) ({ \ 573 register int _lda_v; \ 574 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 575 "r" ((long)(loc)), "r" (asi)); \ 576 _lda_v; \ 577 }) 578 579 #define ldswa(loc, asi) ({ \ 580 register int _lda_v; \ 581 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 582 "r" ((long)(loc)), "r" (asi)); \ 583 _lda_v; \ 584 }) 585 #endif 586 #else /* __arch64__ */ 587 /* load unsigned int from alternate address space */ 588 #ifdef DCACHE_BUG 589 #define lda(loc, asi) ({ \ 590 register int _lda_v, _loc_hi; \ 591 _loc_hi = (((u_int64_t)loc)>>32); \ 592 if (asi == ASI_PHYS_CACHED) { \ 593 __asm __volatile("wr %3,%%g0,%%asi; " \ 594 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ 595 " sllx %2,32,%0; or %0,%1,%0; membar #Sync; lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 596 "r" ((long)(loc)), "r" (_loc_hi), \ 597 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 598 } else { \ 599 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 600 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 601 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 602 } \ 603 _lda_v; \ 604 }) 605 606 /* load signed int from alternate address space */ 607 #define ldswa(loc, asi) ({ \ 608 register int _lda_v, _loc_hi; \ 609 _loc_hi = (((u_int64_t)loc)>>32); \ 610 if (asi == ASI_PHYS_CACHED) { \ 611 __asm __volatile("wr %3,%%g0,%%asi; " \ 612 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ 613 " sllx %2,32,%0; or %0,%1,%0; membar #Sync; ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 614 "r" ((long)(loc)), "r" (_loc_hi), \ 615 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 616 } else { \ 617 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 618 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ 619 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 620 } \ 621 _lda_v; \ 622 }) 623 #else 624 #define lda(loc, asi) ({ \ 625 register int _lda_v, _loc_hi; \ 626 _loc_hi = (((u_int64_t)loc)>>32); \ 627 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 628 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 629 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 630 _lda_v; \ 631 }) 632 633 #define ldswa(loc, asi) ({ \ 634 register int _lda_v, _loc_hi; \ 635 _loc_hi = (((u_int64_t)loc)>>32); \ 636 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 637 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ 638 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 639 _lda_v; \ 640 }) 641 #endif 642 #endif /* __arch64__ */ 643 644 #ifdef DCACHE_BUG 645 646 #ifdef __arch64__ 647 /* load 64-bit int from alternate address space */ 648 #define ldda(loc, asi) ({ \ 649 register long long _lda_v; \ 650 if (asi == ASI_PHYS_CACHED) { \ 651 __asm __volatile("wr %2,%%g0,%%asi; " \ 652 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 653 " ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 654 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 655 } else { \ 656 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 657 "r" ((long)(loc)), "r" (asi)); \ 658 } \ 659 _lda_v; \ 660 }) 661 #else 662 /* load 64-bit int from alternate address space */ 663 #define ldda(loc, asi) ({ \ 664 register long long _lda_v, _loc_hi; \ 665 _loc_hi = (((u_int64_t)loc)>>32); \ 666 if (asi == ASI_PHYS_CACHED) { \ 667 __asm __volatile("wr %3,%%g0,%%asi; " \ 668 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; " \ 669 " sllx %2,32,%0; or %0,%1,%0; membar #Sync; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 670 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 671 } else { \ 672 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 673 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 674 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 675 } \ 676 _lda_v; \ 677 }) 678 #endif 679 680 #ifdef __arch64__ 681 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 682 #define ldxa(loc, asi) ({ \ 683 register long _lda_v; \ 684 if (asi == ASI_PHYS_CACHED) { \ 685 __asm __volatile("wr %2,%%g0,%%asi; "\ 686 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 687 " ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 688 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 689 } else { \ 690 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 691 "r" ((long)(loc)), "r" (asi)); \ 692 } \ 693 _lda_v; \ 694 }) 695 #else 696 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 697 #define ldxa(loc, asi) ({ \ 698 register long _ldxa_lo, _ldxa_hi, _loc_hi; \ 699 _loc_hi = (((u_int64_t)loc)>>32); \ 700 if (asi == ASI_PHYS_CACHED) { \ 701 __asm __volatile("wr %4,%%g0,%%asi; " \ 702 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; " \ 703 " sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \ 704 " srlx %0,32,%1; srl %0,0,%0" : \ 705 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 706 "r" ((long)(loc)), "r" (_loc_hi), \ 707 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 708 } else { \ 709 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 710 " or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 711 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 712 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 713 } \ 714 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 715 }) 716 #endif 717 718 #else 719 720 #ifdef __arch64__ 721 /* load 64-bit int from alternate address space */ 722 #define ldda(loc, asi) ({ \ 723 register long long _lda_v; \ 724 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 725 "r" ((long)(loc)), "r" (asi)); \ 726 _lda_v; \ 727 }) 728 #else 729 #define ldda(loc, asi) ({ \ 730 register long long _lda_v, _loc_hi; \ 731 _loc_hi = (((u_int64_t)loc)>>32); \ 732 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 733 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 734 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 735 _lda_v; \ 736 }) 737 #endif 738 739 #ifdef __arch64__ 740 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 741 #define ldxa(loc, asi) ({ \ 742 register long _lda_v; \ 743 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 744 "r" ((long)(loc)), "r" (asi)); \ 745 _lda_v; \ 746 }) 747 #else 748 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 749 #define ldxa(loc, asi) ({ \ 750 register long _ldxa_lo, _ldxa_hi, _loc_hi; \ 751 _loc_hi = (((u_int64_t)loc)>>32); \ 752 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \ 753 " or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 754 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 755 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 756 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 757 }) 758 #endif 759 #endif 760 761 762 /* store byte to alternate address space */ 763 #ifdef __arch64__ 764 #define stba(loc, asi, value) ({ \ 765 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \ 766 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 767 }) 768 #else 769 #define stba(loc, asi, value) ({ \ 770 register int _loc_hi; \ 771 _loc_hi = (((u_int64_t)loc)>>32); \ 772 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 773 " or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 774 "r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 775 }) 776 #endif 777 778 /* store half-word to alternate address space */ 779 #ifdef __arch64__ 780 #define stha(loc, asi, value) ({ \ 781 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \ 782 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 783 }) 784 #else 785 #define stha(loc, asi, value) ({ \ 786 register int _loc_hi; \ 787 _loc_hi = (((u_int64_t)loc)>>32); \ 788 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 789 " or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 790 "r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 791 }) 792 #endif 793 794 /* store int to alternate address space */ 795 #ifdef __arch64__ 796 #define sta(loc, asi, value) ({ \ 797 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \ 798 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 799 }) 800 #else 801 #define sta(loc, asi, value) ({ \ 802 register int _loc_hi; \ 803 _loc_hi = (((u_int64_t)loc)>>32); \ 804 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 805 " or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 806 "r" ((int)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ 807 }) 808 #endif 809 810 /* store 64-bit int to alternate address space */ 811 #ifdef __arch64__ 812 #define stda(loc, asi, value) ({ \ 813 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \ 814 "r" ((long long)(value)), "r" ((long)(loc)), "r" (asi)); \ 815 }) 816 #else 817 #define stda(loc, asi, value) ({ \ 818 register int _loc_hi; \ 819 _loc_hi = (((u_int64_t)loc)>>32); \ 820 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 821 " or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 822 "r" ((long long)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ 823 }) 824 #endif 825 826 #ifdef __arch64__ 827 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 828 #define stxa(loc, asi, value) ({ \ 829 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : \ 830 "r" ((long)(value)), "r" ((long)(loc)), "r" (asi)); \ 831 }) 832 #else 833 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 834 #define stxa(loc, asi, value) ({ \ 835 int _stxa_lo, _stxa_hi, _loc_hi; \ 836 _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \ 837 _loc_hi = (((u_int64_t)(long)loc)>>32); \ 838 __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \ 839 " or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \ 840 "=&r" (_loc_hi), "=&r" (_stxa_hi) : \ 841 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 842 "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ 843 }) 844 #endif 845 846 /* flush address from data cache */ 847 #define flush(loc) ({ \ 848 __asm __volatile("flush %0" : : \ 849 "r" ((long)(loc))); \ 850 }) 851 852 /* Flush a D$ line */ 853 #if 0 854 #define flushline(loc) ({ \ 855 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 856 membar_sync(); \ 857 }) 858 #else 859 #define flushline(loc) 860 #endif 861 862 /* The following two enable or disable the dcache in the LSU control register */ 863 #define dcenable() ({ \ 864 int res; \ 865 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 866 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 867 }) 868 #define dcdisable() ({ \ 869 int res; \ 870 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 871 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 872 }) 873 874 /* 875 * SPARC V9 memory barrier instructions. 876 */ 877 /* Make all stores complete before next store */ 878 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 879 /* Make all loads complete before next store */ 880 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 881 /* Make all stores complete before next load */ 882 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 883 /* Make all loads complete before next load */ 884 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 885 /* Complete all outstanding memory operations and exceptions */ 886 #define membar_sync() __asm __volatile("membar #Sync" : :) 887 /* Complete all outstanding memory operations */ 888 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 889 /* Complete all outstanding stores before any new loads */ 890 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 891 892 #ifdef __arch64__ 893 /* read 64-bit %tick register */ 894 #define tick() ({ \ 895 register u_long _tick_tmp; \ 896 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 897 _tick_tmp; \ 898 }) 899 #else 900 /* read 64-bit %tick register on 32-bit system */ 901 #define tick() ({ \ 902 register int _tick_hi = 0, _tick_lo = 0; \ 903 __asm __volatile("rdpr %%tick, %1; srlx %0,32,%2; srl %0,0,%0 " \ 904 : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ 905 (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ 906 }) 907 #endif 908 909 #ifndef _LOCORE 910 extern next_tick __P((long)); 911 #endif 912
Indexes created Mon Sep 29 21:09:56 GMT 2025