ctlreg.h revision 1.16
1 /* $NetBSD: ctlreg.h,v 1.16 2000/06/08 17:43:24 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 /* 27 * Sun 4u control registers. (includes address space definitions 28 * and some registers in control space). 29 */ 30 31 /* 32 * The Alternate address spaces. 33 * 34 * 0x00-0x7f are privileged 35 * 0x80-0xff can be used by users 36 */ 37 38 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 39 40 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 41 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 42 43 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 44 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 45 46 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 47 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 48 49 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 50 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 51 52 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 53 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 54 55 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 56 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 57 58 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 59 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 60 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 61 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 62 63 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 64 65 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 66 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 67 68 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 69 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 70 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 71 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 72 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 73 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 74 75 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 76 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 77 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 78 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 79 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 80 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 81 82 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 83 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 84 85 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 86 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 87 88 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 89 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 90 91 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 92 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 93 94 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 95 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 96 #define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */ 97 #define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */ 98 99 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 100 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 101 #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 102 #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 103 104 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 105 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 106 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 107 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 108 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 109 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 110 111 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 112 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 113 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 114 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 115 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 116 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 117 118 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 119 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 120 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 121 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 122 123 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 124 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 125 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 126 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 127 128 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 129 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 130 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 131 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 132 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 133 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 134 135 136 /* 137 * These are the shorter names used by Solaris 138 */ 139 140 #define ASI_N ASI_NUCLEUS 141 #define ASI_NL ASI_NUCLEUS_LITTLE 142 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 143 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 144 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 145 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 146 #define ASI_P ASI_PRIMARY 147 #define ASI_S ASI_SECONDARY 148 #define ASI_PNF ASI_PRIMARY_NO_FAULT 149 #define ASI_SNF ASI_SECONDARY_NO_FAULT 150 #define ASI_PL ASI_PRIMARY_LITTLE 151 #define ASI_SL ASI_SECONDARY_LITTLE 152 #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE 153 #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE 154 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 155 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 156 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 157 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 158 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 159 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 160 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 161 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 162 #define ASI_BLK_P ASI_BLOCK_PRIMARY 163 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 164 #define ASI_BLK_S ASI_BLOCK_SECONDARY 165 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 166 167 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 168 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 169 170 /* 171 * The following are 4u control registers 172 */ 173 174 /* 175 * [4u] MMU and Cache Control Register (MCCR) 176 * use ASI = 0x45 177 */ 178 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 179 #define MCCR 0x00 180 181 /* MCCR Bits and their meanings */ 182 #define MCCR_DMMU_EN 0x08 183 #define MCCR_IMMU_EN 0x04 184 #define MCCR_DCACHE_EN 0x02 185 #define MCCR_ICACHE_EN 0x01 186 187 188 /* 189 * MMU control registers 190 */ 191 192 /* Choose an MMU */ 193 #define ASI_DMMU 0x58 194 #define ASI_IMMU 0x50 195 196 /* Other assorted MMU ASIs */ 197 #define ASI_IMMU_8KPTR 0x51 198 #define ASI_IMMU_64KPTR 0x52 199 #define ASI_IMMU_DATA_IN 0x54 200 #define ASI_IMMU_TLB_DATA 0x55 201 #define ASI_IMMU_TLB_TAG 0x56 202 #define ASI_DMMU_8KPTR 0x59 203 #define ASI_DMMU_64KPTR 0x5a 204 #define ASI_DMMU_DATA_IN 0x5c 205 #define ASI_DMMU_TLB_DATA 0x5d 206 #define ASI_DMMU_TLB_TAG 0x5e 207 208 /* 209 * The following are the control registers 210 * They work on both MMUs unless noted. 211 * 212 * Register contents are defined later on individual registers. 213 */ 214 #define TSB_TAG_TARGET 0x0 215 #define TLB_DATA_IN 0x0 216 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 217 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 218 #define SFSR 0x18 219 #define SFAR 0x20 /* fault address -- DMMU only */ 220 #define TSB 0x28 221 #define TLB_TAG_ACCESS 0x30 222 #define VIRTUAL_WATCHPOINT 0x38 223 #define PHYSICAL_WATCHPOINT 0x40 224 225 /* Tag Target bits */ 226 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 227 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 228 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 229 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 230 231 /* SFSR bits for both D_SFSR and I_SFSR */ 232 #define SFSR_ASI(x) ((x)>>16) 233 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 234 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 235 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 236 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 237 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 238 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 239 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 240 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 241 #define SFSR_CTXT(x) (((x)>>4)&0x3) 242 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 243 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 244 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 245 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 246 #define SFSR_W 0x00004 /* DMMU: attempted write */ 247 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 248 #define SFSR_FV 0x00001 /* Fault is valid */ 249 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 250 251 #if 0 252 /* Old bits */ 253 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 254 #else 255 /* New bits */ 256 #define SFSR_BITS "\177\20" \ 257 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 258 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 259 #endif 260 261 /* ASFR bits */ 262 #define ASFR_ME 0x100000000LL 263 #define ASFR_PRIV 0x080000000LL 264 #define ASFR_ISAP 0x040000000LL 265 #define ASFR_ETP 0x020000000LL 266 #define ASFR_IVUE 0x010000000LL 267 #define ASFR_TO 0x008000000LL 268 #define ASFR_BERR 0x004000000LL 269 #define ASFR_LDP 0x002000000LL 270 #define ASFR_CP 0x001000000LL 271 #define ASFR_WP 0x000800000LL 272 #define ASFR_EDP 0x000400000LL 273 #define ASFR_UE 0x000200000LL 274 #define ASFR_CE 0x000100000LL 275 #define ASFR_ETS 0x0000f0000LL 276 #define ASFT_P_SYND 0x00000ffffLL 277 278 #define AFSR_BITS "\177\20" \ 279 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 280 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 281 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 282 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 283 284 /* 285 * Here's the spitfire TSB control register bits. 286 * 287 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 288 */ 289 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 290 #define TSB_SIZE_1K 0x01 291 #define TSB_SIZE_2K 0x02 292 #define TSB_SIZE_4K 0x03 293 #define TSB_SIZE_8K 0x04 294 #define TSB_SIZE_16K 0x05 295 #define TSB_SIZE_32K 0x06 296 #define TSB_SIZE_64K 0x07 297 #define TSB_SPLIT 0x1000 298 #define TSB_BASE 0xffffffffffffe000 299 300 /* TLB Tag Access bits */ 301 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 302 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 303 304 /* 305 * TLB demap registers. TTEs are defined in v9pte.h 306 * 307 * Use the address space to select between IMMU and DMMU. 308 * The address of the register selects which context register 309 * to read the ASI from. 310 * 311 * The data stored in the register is interpreted as the VA to 312 * use. The DEMAP_CTX_<> registers ignore the address and demap the 313 * entire ASI. 314 * 315 */ 316 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 317 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 318 319 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 320 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 321 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 322 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 323 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 324 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 325 326 /* 327 * Interrupt registers. This really gets hairy. 328 */ 329 330 /* IRSR -- Interrupt Receive Status Ragister */ 331 #define ASI_IRSR 0x49 332 #define IRSR 0x00 333 #define IRSR_BUSY 0x020 334 #define IRSR_MID(x) (x&0x1f) 335 336 /* IRDR -- Interrupt Receive Data Registers */ 337 #define ASI_IRDR 0x7f 338 #define IRDR_0H 0x40 339 #define IRDR_0L 0x48 /* unimplemented */ 340 #define IRDR_1H 0x50 341 #define IRDR_1L 0x58 /* unimplemented */ 342 #define IRDR_2H 0x60 343 #define IRDR_2L 0x68 /* unimplemented */ 344 #define IRDR_3H 0x70 /* unimplemented */ 345 #define IRDR_3L 0x78 /* unimplemented */ 346 347 /* SOFTINT ASRs */ 348 #define SET_SOFTINT %asr20 /* Sets these bits */ 349 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 350 #define SOFTINT %asr22 /* Reads the register */ 351 #define TICK_CMPR %asr23 352 353 #define TICK_INT 0x01 /* level-14 clock tick */ 354 #define SOFTINT1 (0x1<<1) 355 #define SOFTINT2 (0x1<<2) 356 #define SOFTINT3 (0x1<<3) 357 #define SOFTINT4 (0x1<<4) 358 #define SOFTINT5 (0x1<<5) 359 #define SOFTINT6 (0x1<<6) 360 #define SOFTINT7 (0x1<<7) 361 #define SOFTINT8 (0x1<<8) 362 #define SOFTINT9 (0x1<<9) 363 #define SOFTINT10 (0x1<<10) 364 #define SOFTINT11 (0x1<<11) 365 #define SOFTINT12 (0x1<<12) 366 #define SOFTINT13 (0x1<<13) 367 #define SOFTINT14 (0x1<<14) 368 #define SOFTINT15 (0x1<<15) 369 370 /* Interrupt Dispatch -- usually reserved for cross-calls */ 371 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 372 #define IDSR 0x00 373 #define IDSR_NACK 0x02 374 #define IDSR_BUSY 0x01 375 376 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 377 #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */ 378 #define IDDR_0H 0x40 /* Store data to send in these regs */ 379 #define IDDR_0L 0x48 /* unimplemented */ 380 #define IDDR_1H 0x50 381 #define IDDR_1L 0x58 /* unimplemented */ 382 #define IDDR_2H 0x60 383 #define IDDR_2L 0x68 /* unimplemented */ 384 #define IDDR_3H 0x70 /* unimplemented */ 385 #define IDDR_3L 0x78 /* unimplemented */ 386 387 /* 388 * Error registers 389 */ 390 391 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 392 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 393 #define AFAR 0x00 394 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 395 #define AFSR 0x00 396 397 #define ASI_P_EER 0x4b /* Error enable register */ 398 #define P_EER 0x00 399 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 400 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 401 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 402 403 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 404 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 405 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 406 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 407 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 408 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 409 410 411 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 412 413 /* 414 * GCC __asm constructs for doing assembly stuff. 415 */ 416 417 /* 418 * ``Routines'' to load and store from/to alternate address space. 419 * The location can be a variable, the asi value (address space indicator) 420 * must be a constant. 421 * 422 * N.B.: You can put as many special functions here as you like, since 423 * they cost no kernel space or time if they are not used. 424 * 425 * These were static inline functions, but gcc screws up the constraints 426 * on the address space identifiers (the "n"umeric value part) because 427 * it inlines too late, so we have to use the funny valued-macro syntax. 428 */ 429 430 /* DCACHE_BUG forces a flush of the D$ line on every ASI load */ 431 #define DCACHE_BUG 432 433 #ifdef __arch64__ 434 /* load byte from alternate address space */ 435 #ifdef DCACHE_BUG 436 #define lduba(loc, asi) ({ \ 437 register unsigned int _lduba_v; \ 438 if (PHYS_ASI(asi)) { \ 439 __asm __volatile("wr %2,%%g0,%%asi; " \ 440 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 441 " lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \ 442 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 443 } else { \ 444 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 445 "=r" (_lduba_v) : \ 446 "r" ((unsigned long)(loc)), "r" (asi)); \ 447 } \ 448 _lduba_v; \ 449 }) 450 #else 451 #define lduba(loc, asi) ({ \ 452 register unsigned int _lduba_v; \ 453 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 454 "=r" (_lduba_v) : \ 455 "r" ((unsigned long)(loc)), "r" (asi)); \ 456 _lduba_v; \ 457 }) 458 #endif 459 #else 460 /* load byte from alternate address space */ 461 #ifdef DCACHE_BUG 462 #define lduba(loc, asi) ({ \ 463 register unsigned int _lduba_v, _loc_hi, _pstate; \ 464 _loc_hi = (((u_int64_t)loc)>>32); \ 465 if (PHYS_ASI(asi)) { \ 466 __asm __volatile("wr %4,%%g0,%%asi; " \ 467 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " \ 468 " sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " \ 469 " membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 470 "=&r" (_lduba_v), "=&r" (_pstate) : \ 471 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 472 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 473 } else { \ 474 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 475 " rdpr %%pstate,%1; wrpr %1,8,%%pstate; " \ 476 " or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 477 "=&r" (_lduba_v), "=&r" (_pstate) : \ 478 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 479 } \ 480 _lduba_v; \ 481 }) 482 #else 483 #define lduba(loc, asi) ({ \ 484 register unsigned int _lduba_v, _loc_hi, _pstate; \ 485 _loc_hi = (((u_int64_t)loc)>>32); \ 486 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; sllx %3,32,%0; " \ 487 " wrpr %1,8,%%pstate; or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 488 "=&r" (_lduba_v), "=&r" (_pstate) : \ 489 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 490 _lduba_v; \ 491 }) 492 #endif 493 #endif 494 495 #ifdef __arch64__ 496 /* load half-word from alternate address space */ 497 #ifdef DCACHE_BUG 498 #define lduha(loc, asi) ({ \ 499 register unsigned int _lduha_v; \ 500 if (PHYS_ASI(asi)) { \ 501 __asm __volatile("wr %2,%%g0,%%asi; " \ 502 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 503 " lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \ 504 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 505 } else { \ 506 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 507 "r" ((unsigned long)(loc)), "r" (asi)); \ 508 } \ 509 _lduha_v; \ 510 }) 511 #else 512 #define lduha(loc, asi) ({ \ 513 register unsigned int _lduha_v; \ 514 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 515 "r" ((unsigned long)(loc)), "r" (asi)); \ 516 _lduha_v; \ 517 }) 518 #endif 519 #else 520 /* load half-word from alternate address space */ 521 #ifdef DCACHE_BUG 522 #define lduha(loc, asi) ({ \ 523 register unsigned int _lduha_v, _loc_hi, _pstate; \ 524 _loc_hi = (((u_int64_t)loc)>>32); \ 525 if (PHYS_ASI(asi)) { \ 526 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \ 527 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " \ 528 " or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 529 "=&r" (_lduha_v), "=&r" (_pstate) : \ 530 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 531 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 532 } else { \ 533 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \ 534 " sllx %3,32,%0; wrpr %1,8,%%pstate; " \ 535 " or %0,%2,%0; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 536 "=&r" (_lduha_v), "=&r" (_pstate) : \ 537 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 538 } \ 539 _lduha_v; \ 540 }) 541 #else 542 #define lduha(loc, asi) ({ \ 543 register unsigned int _lduha_v, _loc_hi, _pstate; \ 544 _loc_hi = (((u_int64_t)loc)>>32); \ 545 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1; " \ 546 " or %0,%2,%0; wrpr %1,8,%%pstate; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 547 "=&r" (_lduha_v), "=&r" (_pstate) : \ 548 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 549 _lduha_v; \ 550 }) 551 #endif 552 #endif 553 554 #ifdef __arch64__ 555 /* load unsigned int from alternate address space */ 556 #ifdef DCACHE_BUG 557 #define lda(loc, asi) ({ \ 558 register int _lda_v; \ 559 if (PHYS_ASI(asi)) { \ 560 __asm __volatile("wr %2,%%g0,%%asi; " \ 561 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 562 " lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 563 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 564 } else { \ 565 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 566 "r" ((unsigned long)(loc)), "r" (asi)); \ 567 } \ 568 _lda_v; \ 569 }) 570 571 /* load signed int from alternate address space */ 572 #define ldswa(loc, asi) ({ \ 573 register int _lda_v; \ 574 if (PHYS_ASI(asi)) { \ 575 __asm __volatile("wr %2,%%g0,%%asi; " \ 576 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 577 " ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 578 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 579 } else { \ 580 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 581 "r" ((unsigned long)(loc)), "r" (asi)); \ 582 } \ 583 _lda_v; \ 584 }) 585 #else 586 #define lda(loc, asi) ({ \ 587 register int _lda_v; \ 588 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 589 "r" ((unsigned long)(loc)), "r" (asi)); \ 590 _lda_v; \ 591 }) 592 593 #define ldswa(loc, asi) ({ \ 594 register int _lda_v; \ 595 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 596 "r" ((unsigned long)(loc)), "r" (asi)); \ 597 _lda_v; \ 598 }) 599 #endif 600 #else /* __arch64__ */ 601 /* load unsigned int from alternate address space */ 602 #ifdef DCACHE_BUG 603 #define lda(loc, asi) ({ \ 604 register int _lda_v, _loc_hi, _pstate; \ 605 _loc_hi = (((u_int64_t)loc)>>32); \ 606 if (PHYS_ASI(asi)) { \ 607 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 608 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " \ 609 " sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " \ 610 " wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \ 611 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 612 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 613 } else { \ 614 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 615 " sllx %3,32,%0; wrpr %1,8,%%pstate;" \ 616 " or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 617 "=&r" (_lda_v), "=&r" (_pstate) : \ 618 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 619 } \ 620 _lda_v; \ 621 }) 622 623 /* load signed int from alternate address space */ 624 #define ldswa(loc, asi) ({ \ 625 register int _lda_v, _loc_hi, _pstate; \ 626 _loc_hi = (((u_int64_t)loc)>>32); \ 627 if (PHYS_ASI(asi)) { \ 628 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 629 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" \ 630 " or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 631 "=&r" (_lda_v), "=&r" (_pstate) : \ 632 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 633 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 634 } else { \ 635 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0;" \ 636 " rdpr %%pstate,%1; wrpr %1,8,%%pstate;" \ 637 " or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 638 "=&r" (_lda_v), "=&r" (_pstate) : \ 639 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 640 } \ 641 _lda_v; \ 642 }) 643 #else 644 #define lda(loc, asi) ({ \ 645 register int _lda_v, _loc_hi, _pstate; \ 646 _loc_hi = (((u_int64_t)loc)>>32); \ 647 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 648 " wrpr %1,8,%%pstate; or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 649 "=&r" (_lda_v), "=&r" (_pstate) : \ 650 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 651 _lda_v; \ 652 }) 653 654 #define ldswa(loc, asi) ({ \ 655 register int _lda_v, _loc_hi, _pstate;; \ 656 _loc_hi = (((u_int64_t)loc)>>32); \ 657 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 658 " wrpr %1,8,%%pstate; or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%pstate" : \ 659 "=&r" (_lda_v), "=&r" (_pstate) : \ 660 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 661 _lda_v; \ 662 }) 663 #endif 664 #endif /* __arch64__ */ 665 666 #ifdef DCACHE_BUG 667 668 #ifdef __arch64__ 669 /* load 64-bit int from alternate address space */ 670 #define ldda(loc, asi) ({ \ 671 register long long _lda_v; \ 672 if (PHYS_ASI(asi)) { \ 673 __asm __volatile("wr %2,%%g0,%%asi; " \ 674 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 675 " ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 676 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 677 } else { \ 678 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 679 "r" ((unsigned long)(loc)), "r" (asi)); \ 680 } \ 681 _lda_v; \ 682 }) 683 #else 684 /* load 64-bit int from alternate address space */ 685 #define ldda(loc, asi) ({ \ 686 register long long _lda_v, _loc_hi, _pstate; \ 687 _loc_hi = (((u_int64_t)loc)>>32); \ 688 if (PHYS_ASI(asi)) { \ 689 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 690 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" \ 691 " sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" :\ 692 "=&r" (_lda_v), "=&r" (_pstate) : \ 693 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 694 } else { \ 695 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 696 " rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0;" \ 697 " wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \ 698 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 699 } \ 700 _lda_v; \ 701 }) 702 #endif 703 704 #ifdef __arch64__ 705 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 706 #define ldxa(loc, asi) ({ \ 707 register unsigned long _lda_v; \ 708 if (PHYS_ASI(asi)) { \ 709 __asm __volatile("wr %2,%%g0,%%asi; "\ 710 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 711 " ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 712 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 713 } else { \ 714 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 715 "r" ((unsigned long)(loc)), "r" (asi)); \ 716 } \ 717 _lda_v; \ 718 }) 719 #else 720 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 721 #define ldxa(loc, asi) ({ \ 722 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \ 723 _loc_hi = (((u_int64_t)loc)>>32); \ 724 if (PHYS_ASI(asi)) { \ 725 __asm __volatile("wr %4,%%g0,%%asi; " \ 726 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " \ 727 " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \ 728 " wrpr %1,0,%%pstate; srlx %0,32,%1; srl %0,0,%0" : \ 729 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 730 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 731 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 732 } else { \ 733 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 734 " or %0,%2,%0; ldxa [%0]%%asi,%0; " \ 735 " srlx %0,32,%1; srl %0,0,%0;" : \ 736 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 737 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 738 } \ 739 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 740 }) 741 #endif 742 743 #else 744 745 #ifdef __arch64__ 746 /* load 64-bit int from alternate address space */ 747 #define ldda(loc, asi) ({ \ 748 register long long _lda_v; \ 749 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 750 "r" ((unsigned long)(loc)), "r" (asi)); \ 751 _lda_v; \ 752 }) 753 #else 754 #define ldda(loc, asi) ({ \ 755 register long long _lda_v, _loc_hi, _pstate; \ 756 _loc_hi = (((u_int64_t)loc)>>32); \ 757 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 758 " or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 759 "=&r" (_lda_v), "=&r" (_pstate) : \ 760 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 761 _lda_v; \ 762 }) 763 #endif 764 765 #ifdef __arch64__ 766 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 767 #define ldxa(loc, asi) ({ \ 768 register long _lda_v; \ 769 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 770 "r" ((unsigned long)(loc)), "r" (asi)); \ 771 _lda_v; \ 772 }) 773 #else 774 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 775 #define ldxa(loc, asi) ({ \ 776 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \ 777 _loc_hi = (((u_int64_t)loc)>>32); \ 778 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1;" \ 779 " or %0,%1,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate;" \ 780 " srlx %0,32,%1; srl %0,0,%0;" : \ 781 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 782 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 783 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 784 }) 785 #endif 786 #endif 787 788 789 /* store byte to alternate address space */ 790 #ifdef __arch64__ 791 #define stba(loc, asi, value) ({ \ 792 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \ 793 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 794 }) 795 #else 796 #define stba(loc, asi, value) ({ \ 797 register int _loc_hi, _pstate; \ 798 _loc_hi = (((u_int64_t)loc)>>32); \ 799 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 800 " or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 801 "=&r" (_loc_hi), "=&r" (_pstate) : \ 802 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 803 }) 804 #endif 805 806 /* store half-word to alternate address space */ 807 #ifdef __arch64__ 808 #define stha(loc, asi, value) ({ \ 809 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \ 810 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 811 }) 812 #else 813 #define stha(loc, asi, value) ({ \ 814 register int _loc_hi, _pstate; \ 815 _loc_hi = (((u_int64_t)loc)>>32); \ 816 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 817 " or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 818 "=&r" (_loc_hi), "=&r" (_pstate) : \ 819 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 820 }) 821 #endif 822 823 /* store int to alternate address space */ 824 #ifdef __arch64__ 825 #define sta(loc, asi, value) ({ \ 826 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \ 827 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 828 }) 829 #else 830 #define sta(loc, asi, value) ({ \ 831 register int _loc_hi, _pstate; \ 832 _loc_hi = (((u_int64_t)loc)>>32); \ 833 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 834 " or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 835 "=&r" (_loc_hi), "=&r" (_pstate) : \ 836 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 837 }) 838 #endif 839 840 /* store 64-bit int to alternate address space */ 841 #ifdef __arch64__ 842 #define stda(loc, asi, value) ({ \ 843 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \ 844 "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 845 }) 846 #else 847 #define stda(loc, asi, value) ({ \ 848 register int _loc_hi, _pstate; \ 849 _loc_hi = (((u_int64_t)loc)>>32); \ 850 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \ 851 " or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 852 "=&r" (_loc_hi), "=&r" (_pstate) : \ 853 "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 854 }) 855 #endif 856 857 #ifdef __arch64__ 858 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 859 #define stxa(loc, asi, value) ({ \ 860 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : \ 861 "r" ((unsigned long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 862 }) 863 #else 864 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 865 #define stxa(loc, asi, value) ({ \ 866 int _stxa_lo, _stxa_hi, _loc_hi; \ 867 _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \ 868 _loc_hi = (((u_int64_t)(u_long)loc)>>32); \ 869 __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \ 870 " or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \ 871 " stxa %1,[%0]%%asi; wrpr %3,0,%%pstate" : \ 872 "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \ 873 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 874 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 875 }) 876 #endif 877 878 /* flush address from data cache */ 879 #define flush(loc) ({ \ 880 __asm __volatile("flush %0" : : \ 881 "r" ((unsigned long)(loc))); \ 882 }) 883 884 /* Flush a D$ line */ 885 #if 0 886 #define flushline(loc) ({ \ 887 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 888 membar_sync(); \ 889 }) 890 #else 891 #define flushline(loc) 892 #endif 893 894 /* The following two enable or disable the dcache in the LSU control register */ 895 #define dcenable() ({ \ 896 int res; \ 897 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 898 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 899 }) 900 #define dcdisable() ({ \ 901 int res; \ 902 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 903 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 904 }) 905 906 /* 907 * SPARC V9 memory barrier instructions. 908 */ 909 /* Make all stores complete before next store */ 910 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 911 /* Make all loads complete before next store */ 912 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 913 /* Make all stores complete before next load */ 914 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 915 /* Make all loads complete before next load */ 916 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 917 /* Complete all outstanding memory operations and exceptions */ 918 #define membar_sync() __asm __volatile("membar #Sync" : :) 919 /* Complete all outstanding memory operations */ 920 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 921 /* Complete all outstanding stores before any new loads */ 922 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 923 924 #ifdef __arch64__ 925 /* read 64-bit %tick register */ 926 #define tick() ({ \ 927 register u_long _tick_tmp; \ 928 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 929 _tick_tmp; \ 930 }) 931 #else 932 /* read 64-bit %tick register on 32-bit system */ 933 #define tick() ({ \ 934 register int _tick_hi = 0, _tick_lo = 0; \ 935 __asm __volatile("rdpr %%tick, %1; srlx %0,32,%2; srl %0,0,%0 " \ 936 : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ 937 (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ 938 }) 939 #endif 940 941 #ifndef _LOCORE 942 extern void next_tick __P((long)); 943 #endif 944
Indexes created Tue Sep 30 07:10:03 GMT 2025