ctlreg.h revision 1.17
1 /* $NetBSD: ctlreg.h,v 1.17 2000/06/10 20:51:43 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 /* 27 * Sun 4u control registers. (includes address space definitions 28 * and some registers in control space). 29 */ 30 31 /* 32 * The Alternate address spaces. 33 * 34 * 0x00-0x7f are privileged 35 * 0x80-0xff can be used by users 36 */ 37 38 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 39 40 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 41 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 42 43 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 44 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 45 46 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 47 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 48 49 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 50 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 51 52 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 53 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 54 55 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 56 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 57 58 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 59 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 60 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 61 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 62 63 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 64 65 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 66 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 67 68 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 69 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 70 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 71 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 72 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 73 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 74 75 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 76 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 77 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 78 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 79 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 80 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 81 82 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 83 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 84 85 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 86 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 87 88 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 89 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 90 91 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 92 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 93 94 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 95 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 96 #define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */ 97 #define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */ 98 99 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 100 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 101 #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 102 #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 103 104 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 105 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 106 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 107 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 108 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 109 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 110 111 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 112 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 113 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 114 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 115 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 116 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 117 118 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 119 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 120 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 121 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 122 123 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 124 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 125 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 126 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 127 128 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 129 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 130 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 131 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 132 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 133 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 134 135 136 /* 137 * These are the shorter names used by Solaris 138 */ 139 140 #define ASI_N ASI_NUCLEUS 141 #define ASI_NL ASI_NUCLEUS_LITTLE 142 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 143 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 144 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 145 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 146 #define ASI_P ASI_PRIMARY 147 #define ASI_S ASI_SECONDARY 148 #define ASI_PNF ASI_PRIMARY_NO_FAULT 149 #define ASI_SNF ASI_SECONDARY_NO_FAULT 150 #define ASI_PL ASI_PRIMARY_LITTLE 151 #define ASI_SL ASI_SECONDARY_LITTLE 152 #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE 153 #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE 154 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 155 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 156 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 157 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 158 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 159 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 160 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 161 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 162 #define ASI_BLK_P ASI_BLOCK_PRIMARY 163 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 164 #define ASI_BLK_S ASI_BLOCK_SECONDARY 165 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 166 167 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 168 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 169 170 /* 171 * The following are 4u control registers 172 */ 173 174 /* 175 * [4u] MMU and Cache Control Register (MCCR) 176 * use ASI = 0x45 177 */ 178 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 179 #define MCCR 0x00 180 181 /* MCCR Bits and their meanings */ 182 #define MCCR_DMMU_EN 0x08 183 #define MCCR_IMMU_EN 0x04 184 #define MCCR_DCACHE_EN 0x02 185 #define MCCR_ICACHE_EN 0x01 186 187 188 /* 189 * MMU control registers 190 */ 191 192 /* Choose an MMU */ 193 #define ASI_DMMU 0x58 194 #define ASI_IMMU 0x50 195 196 /* Other assorted MMU ASIs */ 197 #define ASI_IMMU_8KPTR 0x51 198 #define ASI_IMMU_64KPTR 0x52 199 #define ASI_IMMU_DATA_IN 0x54 200 #define ASI_IMMU_TLB_DATA 0x55 201 #define ASI_IMMU_TLB_TAG 0x56 202 #define ASI_DMMU_8KPTR 0x59 203 #define ASI_DMMU_64KPTR 0x5a 204 #define ASI_DMMU_DATA_IN 0x5c 205 #define ASI_DMMU_TLB_DATA 0x5d 206 #define ASI_DMMU_TLB_TAG 0x5e 207 208 /* 209 * The following are the control registers 210 * They work on both MMUs unless noted. 211 * 212 * Register contents are defined later on individual registers. 213 */ 214 #define TSB_TAG_TARGET 0x0 215 #define TLB_DATA_IN 0x0 216 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 217 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 218 #define SFSR 0x18 219 #define SFAR 0x20 /* fault address -- DMMU only */ 220 #define TSB 0x28 221 #define TLB_TAG_ACCESS 0x30 222 #define VIRTUAL_WATCHPOINT 0x38 223 #define PHYSICAL_WATCHPOINT 0x40 224 225 /* Tag Target bits */ 226 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 227 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 228 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 229 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 230 231 /* SFSR bits for both D_SFSR and I_SFSR */ 232 #define SFSR_ASI(x) ((x)>>16) 233 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 234 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 235 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 236 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 237 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 238 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 239 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 240 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 241 #define SFSR_CTXT(x) (((x)>>4)&0x3) 242 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 243 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 244 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 245 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 246 #define SFSR_W 0x00004 /* DMMU: attempted write */ 247 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 248 #define SFSR_FV 0x00001 /* Fault is valid */ 249 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 250 251 #if 0 252 /* Old bits */ 253 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 254 #else 255 /* New bits */ 256 #define SFSR_BITS "\177\20" \ 257 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 258 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 259 #endif 260 261 /* ASFR bits */ 262 #define ASFR_ME 0x100000000LL 263 #define ASFR_PRIV 0x080000000LL 264 #define ASFR_ISAP 0x040000000LL 265 #define ASFR_ETP 0x020000000LL 266 #define ASFR_IVUE 0x010000000LL 267 #define ASFR_TO 0x008000000LL 268 #define ASFR_BERR 0x004000000LL 269 #define ASFR_LDP 0x002000000LL 270 #define ASFR_CP 0x001000000LL 271 #define ASFR_WP 0x000800000LL 272 #define ASFR_EDP 0x000400000LL 273 #define ASFR_UE 0x000200000LL 274 #define ASFR_CE 0x000100000LL 275 #define ASFR_ETS 0x0000f0000LL 276 #define ASFT_P_SYND 0x00000ffffLL 277 278 #define AFSR_BITS "\177\20" \ 279 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 280 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 281 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 282 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 283 284 /* 285 * Here's the spitfire TSB control register bits. 286 * 287 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 288 */ 289 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 290 #define TSB_SIZE_1K 0x01 291 #define TSB_SIZE_2K 0x02 292 #define TSB_SIZE_4K 0x03 293 #define TSB_SIZE_8K 0x04 294 #define TSB_SIZE_16K 0x05 295 #define TSB_SIZE_32K 0x06 296 #define TSB_SIZE_64K 0x07 297 #define TSB_SPLIT 0x1000 298 #define TSB_BASE 0xffffffffffffe000 299 300 /* TLB Tag Access bits */ 301 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 302 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 303 304 /* 305 * TLB demap registers. TTEs are defined in v9pte.h 306 * 307 * Use the address space to select between IMMU and DMMU. 308 * The address of the register selects which context register 309 * to read the ASI from. 310 * 311 * The data stored in the register is interpreted as the VA to 312 * use. The DEMAP_CTX_<> registers ignore the address and demap the 313 * entire ASI. 314 * 315 */ 316 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 317 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 318 319 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 320 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 321 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 322 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 323 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 324 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 325 326 /* 327 * Interrupt registers. This really gets hairy. 328 */ 329 330 /* IRSR -- Interrupt Receive Status Ragister */ 331 #define ASI_IRSR 0x49 332 #define IRSR 0x00 333 #define IRSR_BUSY 0x020 334 #define IRSR_MID(x) (x&0x1f) 335 336 /* IRDR -- Interrupt Receive Data Registers */ 337 #define ASI_IRDR 0x7f 338 #define IRDR_0H 0x40 339 #define IRDR_0L 0x48 /* unimplemented */ 340 #define IRDR_1H 0x50 341 #define IRDR_1L 0x58 /* unimplemented */ 342 #define IRDR_2H 0x60 343 #define IRDR_2L 0x68 /* unimplemented */ 344 #define IRDR_3H 0x70 /* unimplemented */ 345 #define IRDR_3L 0x78 /* unimplemented */ 346 347 /* SOFTINT ASRs */ 348 #define SET_SOFTINT %asr20 /* Sets these bits */ 349 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 350 #define SOFTINT %asr22 /* Reads the register */ 351 #define TICK_CMPR %asr23 352 353 #define TICK_INT 0x01 /* level-14 clock tick */ 354 #define SOFTINT1 (0x1<<1) 355 #define SOFTINT2 (0x1<<2) 356 #define SOFTINT3 (0x1<<3) 357 #define SOFTINT4 (0x1<<4) 358 #define SOFTINT5 (0x1<<5) 359 #define SOFTINT6 (0x1<<6) 360 #define SOFTINT7 (0x1<<7) 361 #define SOFTINT8 (0x1<<8) 362 #define SOFTINT9 (0x1<<9) 363 #define SOFTINT10 (0x1<<10) 364 #define SOFTINT11 (0x1<<11) 365 #define SOFTINT12 (0x1<<12) 366 #define SOFTINT13 (0x1<<13) 367 #define SOFTINT14 (0x1<<14) 368 #define SOFTINT15 (0x1<<15) 369 370 /* Interrupt Dispatch -- usually reserved for cross-calls */ 371 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 372 #define IDSR 0x00 373 #define IDSR_NACK 0x02 374 #define IDSR_BUSY 0x01 375 376 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 377 #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */ 378 #define IDDR_0H 0x40 /* Store data to send in these regs */ 379 #define IDDR_0L 0x48 /* unimplemented */ 380 #define IDDR_1H 0x50 381 #define IDDR_1L 0x58 /* unimplemented */ 382 #define IDDR_2H 0x60 383 #define IDDR_2L 0x68 /* unimplemented */ 384 #define IDDR_3H 0x70 /* unimplemented */ 385 #define IDDR_3L 0x78 /* unimplemented */ 386 387 /* 388 * Error registers 389 */ 390 391 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 392 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 393 #define AFAR 0x00 394 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 395 #define AFSR 0x00 396 397 #define ASI_P_EER 0x4b /* Error enable register */ 398 #define P_EER 0x00 399 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 400 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 401 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 402 403 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 404 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 405 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 406 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 407 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 408 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 409 410 411 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 412 413 /* 414 * GCC __asm constructs for doing assembly stuff. 415 */ 416 417 /* 418 * ``Routines'' to load and store from/to alternate address space. 419 * The location can be a variable, the asi value (address space indicator) 420 * must be a constant. 421 * 422 * N.B.: You can put as many special functions here as you like, since 423 * they cost no kernel space or time if they are not used. 424 * 425 * These were static inline functions, but gcc screws up the constraints 426 * on the address space identifiers (the "n"umeric value part) because 427 * it inlines too late, so we have to use the funny valued-macro syntax. 428 */ 429 430 /* DCACHE_BUG forces a flush of the D$ line on every ASI load */ 431 #define DCACHE_BUG 432 433 #ifdef __arch64__ 434 /* load byte from alternate address space */ 435 #ifdef DCACHE_BUG 436 #define lduba(loc, asi) ({ \ 437 register unsigned int _lduba_v; \ 438 if (PHYS_ASI(asi)) { \ 439 __asm __volatile("wr %2,%%g0,%%asi; " \ 440 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 441 " lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \ 442 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 443 } else { \ 444 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 445 "=r" (_lduba_v) : \ 446 "r" ((unsigned long)(loc)), "r" (asi)); \ 447 } \ 448 _lduba_v; \ 449 }) 450 #else 451 #define lduba(loc, asi) ({ \ 452 register unsigned int _lduba_v; \ 453 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 454 "=r" (_lduba_v) : \ 455 "r" ((unsigned long)(loc)), "r" (asi)); \ 456 _lduba_v; \ 457 }) 458 #endif 459 #else 460 /* load byte from alternate address space */ 461 #ifdef DCACHE_BUG 462 #define lduba(loc, asi) ({ \ 463 register unsigned int _lduba_v, _loc_hi, _pstate; \ 464 _loc_hi = (((u_int64_t)loc)>>32); \ 465 if (PHYS_ASI(asi)) { \ 466 __asm __volatile("wr %4,%%g0,%%asi; " \ 467 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " \ 468 " sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " \ 469 " membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 470 "=&r" (_lduba_v), "=&r" (_pstate) : \ 471 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 472 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 473 } else { \ 474 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 475 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 476 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 477 } \ 478 _lduba_v; \ 479 }) 480 #else 481 #define lduba(loc, asi) ({ \ 482 register unsigned int _lduba_v, _loc_hi, _pstate; \ 483 _loc_hi = (((u_int64_t)loc)>>32); \ 484 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; sllx %3,32,%0; " \ 485 " wrpr %1,8,%%pstate; or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 486 "=&r" (_lduba_v), "=&r" (_pstate) : \ 487 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 488 _lduba_v; \ 489 }) 490 #endif 491 #endif 492 493 #ifdef __arch64__ 494 /* load half-word from alternate address space */ 495 #ifdef DCACHE_BUG 496 #define lduha(loc, asi) ({ \ 497 register unsigned int _lduha_v; \ 498 if (PHYS_ASI(asi)) { \ 499 __asm __volatile("wr %2,%%g0,%%asi; " \ 500 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 501 " lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \ 502 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 503 } else { \ 504 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 505 "r" ((unsigned long)(loc)), "r" (asi)); \ 506 } \ 507 _lduha_v; \ 508 }) 509 #else 510 #define lduha(loc, asi) ({ \ 511 register unsigned int _lduha_v; \ 512 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 513 "r" ((unsigned long)(loc)), "r" (asi)); \ 514 _lduha_v; \ 515 }) 516 #endif 517 #else 518 /* load half-word from alternate address space */ 519 #ifdef DCACHE_BUG 520 #define lduha(loc, asi) ({ \ 521 register unsigned int _lduha_v, _loc_hi, _pstate; \ 522 _loc_hi = (((u_int64_t)loc)>>32); \ 523 if (PHYS_ASI(asi)) { \ 524 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \ 525 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " \ 526 " or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 527 "=&r" (_lduha_v), "=&r" (_pstate) : \ 528 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 529 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 530 } else { \ 531 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 532 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 533 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 534 } \ 535 _lduha_v; \ 536 }) 537 #else 538 #define lduha(loc, asi) ({ \ 539 register unsigned int _lduha_v, _loc_hi, _pstate; \ 540 _loc_hi = (((u_int64_t)loc)>>32); \ 541 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1; " \ 542 " or %0,%2,%0; wrpr %1,8,%%pstate; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 543 "=&r" (_lduha_v), "=&r" (_pstate) : \ 544 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 545 _lduha_v; \ 546 }) 547 #endif 548 #endif 549 550 #ifdef __arch64__ 551 /* load unsigned int from alternate address space */ 552 #ifdef DCACHE_BUG 553 #define lda(loc, asi) ({ \ 554 register int _lda_v; \ 555 if (PHYS_ASI(asi)) { \ 556 __asm __volatile("wr %2,%%g0,%%asi; " \ 557 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 558 " lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 559 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 560 } else { \ 561 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 562 "r" ((unsigned long)(loc)), "r" (asi)); \ 563 } \ 564 _lda_v; \ 565 }) 566 567 /* load signed int from alternate address space */ 568 #define ldswa(loc, asi) ({ \ 569 register int _lda_v; \ 570 if (PHYS_ASI(asi)) { \ 571 __asm __volatile("wr %2,%%g0,%%asi; " \ 572 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 573 " ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 574 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 575 } else { \ 576 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 577 "r" ((unsigned long)(loc)), "r" (asi)); \ 578 } \ 579 _lda_v; \ 580 }) 581 #else 582 #define lda(loc, asi) ({ \ 583 register int _lda_v; \ 584 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 585 "r" ((unsigned long)(loc)), "r" (asi)); \ 586 _lda_v; \ 587 }) 588 589 #define ldswa(loc, asi) ({ \ 590 register int _lda_v; \ 591 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 592 "r" ((unsigned long)(loc)), "r" (asi)); \ 593 _lda_v; \ 594 }) 595 #endif 596 #else /* __arch64__ */ 597 /* load unsigned int from alternate address space */ 598 #ifdef DCACHE_BUG 599 #define lda(loc, asi) ({ \ 600 register int _lda_v, _loc_hi, _pstate; \ 601 _loc_hi = (((u_int64_t)loc)>>32); \ 602 if (PHYS_ASI(asi)) { \ 603 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 604 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " \ 605 " sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " \ 606 " wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \ 607 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 608 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 609 } else { \ 610 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 611 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 612 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 613 } \ 614 _lda_v; \ 615 }) 616 617 /* load signed int from alternate address space */ 618 #define ldswa(loc, asi) ({ \ 619 register int _lda_v, _loc_hi, _pstate; \ 620 _loc_hi = (((u_int64_t)loc)>>32); \ 621 if (PHYS_ASI(asi)) { \ 622 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 623 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" \ 624 " or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 625 "=&r" (_lda_v), "=&r" (_pstate) : \ 626 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 627 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 628 } else { \ 629 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 630 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ 631 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 632 } \ 633 _lda_v; \ 634 }) 635 #else 636 #define lda(loc, asi) ({ \ 637 register int _lda_v, _loc_hi, _pstate; \ 638 _loc_hi = (((u_int64_t)loc)>>32); \ 639 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 640 " wrpr %1,8,%%pstate; or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 641 "=&r" (_lda_v), "=&r" (_pstate) : \ 642 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 643 _lda_v; \ 644 }) 645 646 #define ldswa(loc, asi) ({ \ 647 register int _lda_v, _loc_hi, _pstate;; \ 648 _loc_hi = (((u_int64_t)loc)>>32); \ 649 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 650 " wrpr %1,8,%%pstate; or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%pstate" : \ 651 "=&r" (_lda_v), "=&r" (_pstate) : \ 652 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 653 _lda_v; \ 654 }) 655 #endif 656 #endif /* __arch64__ */ 657 658 #ifdef DCACHE_BUG 659 660 #ifdef __arch64__ 661 /* load 64-bit int from alternate address space */ 662 #define ldda(loc, asi) ({ \ 663 register long long _lda_v; \ 664 if (PHYS_ASI(asi)) { \ 665 __asm __volatile("wr %2,%%g0,%%asi; " \ 666 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 667 " ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 668 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 669 } else { \ 670 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 671 "r" ((unsigned long)(loc)), "r" (asi)); \ 672 } \ 673 _lda_v; \ 674 }) 675 #else 676 /* load 64-bit int from alternate address space */ 677 #define ldda(loc, asi) ({ \ 678 register long long _lda_v, _loc_hi, _pstate; \ 679 _loc_hi = (((u_int64_t)loc)>>32); \ 680 if (PHYS_ASI(asi)) { \ 681 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 682 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" \ 683 " sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" :\ 684 "=&r" (_lda_v), "=&r" (_pstate) : \ 685 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 686 } else { \ 687 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 688 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 689 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 690 } \ 691 _lda_v; \ 692 }) 693 #endif 694 695 #ifdef __arch64__ 696 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 697 #define ldxa(loc, asi) ({ \ 698 register unsigned long _lda_v; \ 699 if (PHYS_ASI(asi)) { \ 700 __asm __volatile("wr %2,%%g0,%%asi; "\ 701 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 702 " ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 703 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 704 } else { \ 705 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 706 "r" ((unsigned long)(loc)), "r" (asi)); \ 707 } \ 708 _lda_v; \ 709 }) 710 #else 711 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 712 #define ldxa(loc, asi) ({ \ 713 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \ 714 _loc_hi = (((u_int64_t)loc)>>32); \ 715 if (PHYS_ASI(asi)) { \ 716 __asm __volatile("wr %4,%%g0,%%asi; " \ 717 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " \ 718 " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \ 719 " wrpr %1,0,%%pstate; srlx %0,32,%1; srl %0,0,%0" : \ 720 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 721 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 722 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 723 } else { \ 724 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 725 " or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 726 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 727 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 728 } \ 729 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 730 }) 731 #endif 732 733 #else 734 735 #ifdef __arch64__ 736 /* load 64-bit int from alternate address space */ 737 #define ldda(loc, asi) ({ \ 738 register long long _lda_v; \ 739 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 740 "r" ((unsigned long)(loc)), "r" (asi)); \ 741 _lda_v; \ 742 }) 743 #else 744 #define ldda(loc, asi) ({ \ 745 register long long _lda_v, _loc_hi, _pstate; \ 746 _loc_hi = (((u_int64_t)loc)>>32); \ 747 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 748 " or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 749 "=&r" (_lda_v), "=&r" (_pstate) : \ 750 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 751 _lda_v; \ 752 }) 753 #endif 754 755 #ifdef __arch64__ 756 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 757 #define ldxa(loc, asi) ({ \ 758 register long _lda_v; \ 759 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 760 "r" ((unsigned long)(loc)), "r" (asi)); \ 761 _lda_v; \ 762 }) 763 #else 764 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 765 #define ldxa(loc, asi) ({ \ 766 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \ 767 _loc_hi = (((u_int64_t)loc)>>32); \ 768 if (PHYS_ASI(asi)) { \ 769 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1;" \ 770 " or %0,%1,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate;" \ 771 " srlx %0,32,%1; srl %0,0,%0;" : \ 772 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 773 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 774 } else { \ 775 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \ 776 " or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 777 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 778 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 779 } \ 780 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 781 }) 782 #endif 783 #endif 784 785 786 /* store byte to alternate address space */ 787 #ifdef __arch64__ 788 #define stba(loc, asi, value) ({ \ 789 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \ 790 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 791 }) 792 #else 793 #define stba(loc, asi, value) ({ \ 794 register int _loc_hi, _pstate; \ 795 _loc_hi = (((u_int64_t)loc)>>32); \ 796 if (PHYS_ASI(asi)) { \ 797 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 798 " or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 799 "=&r" (_loc_hi), "=&r" (_pstate) : \ 800 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 801 "r" (_loc_hi), "r" (asi)); \ 802 } else { \ 803 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 804 " or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 805 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 806 "r" (_loc_hi), "r" (asi)); \ 807 } \ 808 }) 809 #endif 810 811 /* store half-word to alternate address space */ 812 #ifdef __arch64__ 813 #define stha(loc, asi, value) ({ \ 814 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \ 815 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 816 }) 817 #else 818 #define stha(loc, asi, value) ({ \ 819 register int _loc_hi, _pstate; \ 820 _loc_hi = (((u_int64_t)loc)>>32); \ 821 if (PHYS_ASI(asi)) { \ 822 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 823 " or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 824 "=&r" (_loc_hi), "=&r" (_pstate) : \ 825 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 826 "r" (_loc_hi), "r" (asi)); \ 827 } else { \ 828 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 829 " or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 830 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 831 "r" (_loc_hi), "r" (asi)); \ 832 } \ 833 }) 834 #endif 835 836 /* store int to alternate address space */ 837 #ifdef __arch64__ 838 #define sta(loc, asi, value) ({ \ 839 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \ 840 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 841 }) 842 #else 843 #define sta(loc, asi, value) ({ \ 844 register int _loc_hi, _pstate; \ 845 _loc_hi = (((u_int64_t)loc)>>32); \ 846 if (PHYS_ASI(asi)) { \ 847 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 848 " or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 849 "=&r" (_loc_hi), "=&r" (_pstate) : \ 850 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 851 "r" (_loc_hi), "r" (asi)); \ 852 } else { \ 853 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 854 " or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 855 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 856 "r" (_loc_hi), "r" (asi)); \ 857 } \ 858 }) 859 #endif 860 861 /* store 64-bit int to alternate address space */ 862 #ifdef __arch64__ 863 #define stda(loc, asi, value) ({ \ 864 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \ 865 "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 866 }) 867 #else 868 #define stda(loc, asi, value) ({ \ 869 register int _loc_hi, _pstate; \ 870 _loc_hi = (((u_int64_t)loc)>>32); \ 871 if (PHYS_ASI(asi)) { \ 872 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \ 873 " or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 874 "=&r" (_loc_hi), "=&r" (_pstate) : \ 875 "r" ((long long)(value)), "r" ((unsigned long)(loc)), \ 876 "r" (_loc_hi), "r" (asi)); \ 877 } else { \ 878 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 879 " or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 880 "r" ((long long)(value)), "r" ((unsigned long)(loc)), \ 881 "r" (_loc_hi), "r" (asi)); \ 882 } \ 883 }) 884 #endif 885 886 #ifdef __arch64__ 887 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 888 #define stxa(loc, asi, value) ({ \ 889 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : \ 890 "r" ((unsigned long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 891 }) 892 #else 893 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 894 #define stxa(loc, asi, value) ({ \ 895 int _stxa_lo, _stxa_hi, _loc_hi; \ 896 _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \ 897 _loc_hi = (((u_int64_t)(u_long)loc)>>32); \ 898 if (PHYS_ASI(asi)) { \ 899 __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \ 900 " or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \ 901 " stxa %1,[%0]%%asi; wrpr %3,0,%%pstate" : \ 902 "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \ 903 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 904 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 905 } else { \ 906 __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \ 907 " or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \ 908 "=&r" (_loc_hi), "=&r" (_stxa_hi) : \ 909 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 910 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 911 } \ 912 }) 913 #endif 914 915 /* flush address from data cache */ 916 #define flush(loc) ({ \ 917 __asm __volatile("flush %0" : : \ 918 "r" ((unsigned long)(loc))); \ 919 }) 920 921 /* Flush a D$ line */ 922 #if 0 923 #define flushline(loc) ({ \ 924 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 925 membar_sync(); \ 926 }) 927 #else 928 #define flushline(loc) 929 #endif 930 931 /* The following two enable or disable the dcache in the LSU control register */ 932 #define dcenable() ({ \ 933 int res; \ 934 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 935 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 936 }) 937 #define dcdisable() ({ \ 938 int res; \ 939 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 940 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 941 }) 942 943 /* 944 * SPARC V9 memory barrier instructions. 945 */ 946 /* Make all stores complete before next store */ 947 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 948 /* Make all loads complete before next store */ 949 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 950 /* Make all stores complete before next load */ 951 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 952 /* Make all loads complete before next load */ 953 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 954 /* Complete all outstanding memory operations and exceptions */ 955 #define membar_sync() __asm __volatile("membar #Sync" : :) 956 /* Complete all outstanding memory operations */ 957 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 958 /* Complete all outstanding stores before any new loads */ 959 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 960 961 #ifdef __arch64__ 962 /* read 64-bit %tick register */ 963 #define tick() ({ \ 964 register u_long _tick_tmp; \ 965 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 966 _tick_tmp; \ 967 }) 968 #else 969 /* read 64-bit %tick register on 32-bit system */ 970 #define tick() ({ \ 971 register int _tick_hi = 0, _tick_lo = 0; \ 972 __asm __volatile("rdpr %%tick, %1; srlx %0,32,%2; srl %0,0,%0 " \ 973 : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ 974 (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ 975 }) 976 #endif 977 978 #ifndef _LOCORE 979 extern void next_tick __P((long)); 980 #endif 981
Indexes created Mon Sep 29 21:09:56 GMT 2025