ctlreg.h revision 1.18.2.1
1 /* $NetBSD: ctlreg.h,v 1.18.2.1 2000/07/18 16:23:22 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 /* 27 * Sun 4u control registers. (includes address space definitions 28 * and some registers in control space). 29 */ 30 31 /* 32 * The Alternate address spaces. 33 * 34 * 0x00-0x7f are privileged 35 * 0x80-0xff can be used by users 36 */ 37 38 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 39 40 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 41 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 42 43 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 44 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 45 46 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 47 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 48 49 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 50 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 51 52 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 53 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 54 55 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 56 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 57 58 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 59 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 60 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 61 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 62 63 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 64 65 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 66 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 67 68 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 69 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 70 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 71 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 72 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 73 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 74 75 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 76 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 77 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 78 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 79 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 80 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 81 82 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 83 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 84 85 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 86 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 87 88 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 89 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 90 91 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 92 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 93 94 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 95 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 96 #define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */ 97 #define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */ 98 99 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 100 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 101 #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 102 #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 103 104 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 105 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 106 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 107 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 108 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 109 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 110 111 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 112 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 113 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 114 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 115 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 116 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 117 118 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 119 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 120 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 121 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 122 123 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 124 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 125 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 126 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 127 128 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 129 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 130 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 131 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 132 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 133 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 134 135 136 /* 137 * These are the shorter names used by Solaris 138 */ 139 140 #define ASI_N ASI_NUCLEUS 141 #define ASI_NL ASI_NUCLEUS_LITTLE 142 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 143 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 144 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 145 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 146 #define ASI_P ASI_PRIMARY 147 #define ASI_S ASI_SECONDARY 148 #define ASI_PNF ASI_PRIMARY_NO_FAULT 149 #define ASI_SNF ASI_SECONDARY_NO_FAULT 150 #define ASI_PL ASI_PRIMARY_LITTLE 151 #define ASI_SL ASI_SECONDARY_LITTLE 152 #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE 153 #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE 154 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 155 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 156 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 157 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 158 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 159 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 160 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 161 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 162 #define ASI_BLK_P ASI_BLOCK_PRIMARY 163 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 164 #define ASI_BLK_S ASI_BLOCK_SECONDARY 165 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 166 167 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 168 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 169 170 /* 171 * The following are 4u control registers 172 */ 173 174 175 /* Get the CPU's UPAID */ 176 #define UPA_CR_MID(x) (((x)>>17)&0x1f) 177 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 178 179 /* 180 * [4u] MMU and Cache Control Register (MCCR) 181 * use ASI = 0x45 182 */ 183 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 184 #define MCCR 0x00 185 186 /* MCCR Bits and their meanings */ 187 #define MCCR_DMMU_EN 0x08 188 #define MCCR_IMMU_EN 0x04 189 #define MCCR_DCACHE_EN 0x02 190 #define MCCR_ICACHE_EN 0x01 191 192 193 /* 194 * MMU control registers 195 */ 196 197 /* Choose an MMU */ 198 #define ASI_DMMU 0x58 199 #define ASI_IMMU 0x50 200 201 /* Other assorted MMU ASIs */ 202 #define ASI_IMMU_8KPTR 0x51 203 #define ASI_IMMU_64KPTR 0x52 204 #define ASI_IMMU_DATA_IN 0x54 205 #define ASI_IMMU_TLB_DATA 0x55 206 #define ASI_IMMU_TLB_TAG 0x56 207 #define ASI_DMMU_8KPTR 0x59 208 #define ASI_DMMU_64KPTR 0x5a 209 #define ASI_DMMU_DATA_IN 0x5c 210 #define ASI_DMMU_TLB_DATA 0x5d 211 #define ASI_DMMU_TLB_TAG 0x5e 212 213 /* 214 * The following are the control registers 215 * They work on both MMUs unless noted. 216 * 217 * Register contents are defined later on individual registers. 218 */ 219 #define TSB_TAG_TARGET 0x0 220 #define TLB_DATA_IN 0x0 221 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 222 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 223 #define SFSR 0x18 224 #define SFAR 0x20 /* fault address -- DMMU only */ 225 #define TSB 0x28 226 #define TLB_TAG_ACCESS 0x30 227 #define VIRTUAL_WATCHPOINT 0x38 228 #define PHYSICAL_WATCHPOINT 0x40 229 230 /* Tag Target bits */ 231 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 232 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 233 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 234 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 235 236 /* SFSR bits for both D_SFSR and I_SFSR */ 237 #define SFSR_ASI(x) ((x)>>16) 238 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 239 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 240 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 241 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 242 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 243 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 244 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 245 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 246 #define SFSR_CTXT(x) (((x)>>4)&0x3) 247 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 248 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 249 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 250 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 251 #define SFSR_W 0x00004 /* DMMU: attempted write */ 252 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 253 #define SFSR_FV 0x00001 /* Fault is valid */ 254 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 255 256 #if 0 257 /* Old bits */ 258 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 259 #else 260 /* New bits */ 261 #define SFSR_BITS "\177\20" \ 262 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 263 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 264 #endif 265 266 /* ASFR bits */ 267 #define ASFR_ME 0x100000000LL 268 #define ASFR_PRIV 0x080000000LL 269 #define ASFR_ISAP 0x040000000LL 270 #define ASFR_ETP 0x020000000LL 271 #define ASFR_IVUE 0x010000000LL 272 #define ASFR_TO 0x008000000LL 273 #define ASFR_BERR 0x004000000LL 274 #define ASFR_LDP 0x002000000LL 275 #define ASFR_CP 0x001000000LL 276 #define ASFR_WP 0x000800000LL 277 #define ASFR_EDP 0x000400000LL 278 #define ASFR_UE 0x000200000LL 279 #define ASFR_CE 0x000100000LL 280 #define ASFR_ETS 0x0000f0000LL 281 #define ASFT_P_SYND 0x00000ffffLL 282 283 #define AFSR_BITS "\177\20" \ 284 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 285 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 286 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 287 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 288 289 /* 290 * Here's the spitfire TSB control register bits. 291 * 292 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 293 */ 294 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 295 #define TSB_SIZE_1K 0x01 296 #define TSB_SIZE_2K 0x02 297 #define TSB_SIZE_4K 0x03 298 #define TSB_SIZE_8K 0x04 299 #define TSB_SIZE_16K 0x05 300 #define TSB_SIZE_32K 0x06 301 #define TSB_SIZE_64K 0x07 302 #define TSB_SPLIT 0x1000 303 #define TSB_BASE 0xffffffffffffe000 304 305 /* TLB Tag Access bits */ 306 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 307 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 308 309 /* 310 * TLB demap registers. TTEs are defined in v9pte.h 311 * 312 * Use the address space to select between IMMU and DMMU. 313 * The address of the register selects which context register 314 * to read the ASI from. 315 * 316 * The data stored in the register is interpreted as the VA to 317 * use. The DEMAP_CTX_<> registers ignore the address and demap the 318 * entire ASI. 319 * 320 */ 321 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 322 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 323 324 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 325 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 326 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 327 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 328 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 329 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 330 331 /* 332 * Interrupt registers. This really gets hairy. 333 */ 334 335 /* IRSR -- Interrupt Receive Status Ragister */ 336 #define ASI_IRSR 0x49 337 #define IRSR 0x00 338 #define IRSR_BUSY 0x020 339 #define IRSR_MID(x) (x&0x1f) 340 341 /* IRDR -- Interrupt Receive Data Registers */ 342 #define ASI_IRDR 0x7f 343 #define IRDR_0H 0x40 344 #define IRDR_0L 0x48 /* unimplemented */ 345 #define IRDR_1H 0x50 346 #define IRDR_1L 0x58 /* unimplemented */ 347 #define IRDR_2H 0x60 348 #define IRDR_2L 0x68 /* unimplemented */ 349 #define IRDR_3H 0x70 /* unimplemented */ 350 #define IRDR_3L 0x78 /* unimplemented */ 351 352 /* SOFTINT ASRs */ 353 #define SET_SOFTINT %asr20 /* Sets these bits */ 354 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 355 #define SOFTINT %asr22 /* Reads the register */ 356 #define TICK_CMPR %asr23 357 358 #define TICK_INT 0x01 /* level-14 clock tick */ 359 #define SOFTINT1 (0x1<<1) 360 #define SOFTINT2 (0x1<<2) 361 #define SOFTINT3 (0x1<<3) 362 #define SOFTINT4 (0x1<<4) 363 #define SOFTINT5 (0x1<<5) 364 #define SOFTINT6 (0x1<<6) 365 #define SOFTINT7 (0x1<<7) 366 #define SOFTINT8 (0x1<<8) 367 #define SOFTINT9 (0x1<<9) 368 #define SOFTINT10 (0x1<<10) 369 #define SOFTINT11 (0x1<<11) 370 #define SOFTINT12 (0x1<<12) 371 #define SOFTINT13 (0x1<<13) 372 #define SOFTINT14 (0x1<<14) 373 #define SOFTINT15 (0x1<<15) 374 375 /* Interrupt Dispatch -- usually reserved for cross-calls */ 376 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 377 #define IDSR 0x00 378 #define IDSR_NACK 0x02 379 #define IDSR_BUSY 0x01 380 381 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 382 #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */ 383 #define IDDR_0H 0x40 /* Store data to send in these regs */ 384 #define IDDR_0L 0x48 /* unimplemented */ 385 #define IDDR_1H 0x50 386 #define IDDR_1L 0x58 /* unimplemented */ 387 #define IDDR_2H 0x60 388 #define IDDR_2L 0x68 /* unimplemented */ 389 #define IDDR_3H 0x70 /* unimplemented */ 390 #define IDDR_3L 0x78 /* unimplemented */ 391 392 /* 393 * Error registers 394 */ 395 396 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 397 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 398 #define AFAR 0x00 399 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 400 #define AFSR 0x00 401 402 #define ASI_P_EER 0x4b /* Error enable register */ 403 #define P_EER 0x00 404 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 405 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 406 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 407 408 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 409 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 410 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 411 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 412 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 413 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 414 415 416 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 417 418 #ifndef _LOCORE 419 /* 420 * GCC __asm constructs for doing assembly stuff. 421 */ 422 423 /* 424 * ``Routines'' to load and store from/to alternate address space. 425 * The location can be a variable, the asi value (address space indicator) 426 * must be a constant. 427 * 428 * N.B.: You can put as many special functions here as you like, since 429 * they cost no kernel space or time if they are not used. 430 * 431 * These were static inline functions, but gcc screws up the constraints 432 * on the address space identifiers (the "n"umeric value part) because 433 * it inlines too late, so we have to use the funny valued-macro syntax. 434 */ 435 436 /* 437 * Apparently the definition of bypass ASIs is that they all use the 438 * D$ so we need to flush the D$ to make sure we don't get data pollution. 439 */ 440 441 static __inline__ u_char lduba __P((paddr_t loc, int asi)); 442 static __inline__ u_short lduha __P((paddr_t loc, int asi)); 443 static __inline__ u_int lda __P((paddr_t loc, int asi)); 444 static __inline__ int ldswa __P((paddr_t loc, int asi)); 445 static __inline__ u_int64_t ldxa __P((paddr_t loc, int asi)); 446 static __inline__ u_int64_t ldda __P((paddr_t loc, int asi)); 447 448 static __inline__ void stba __P((paddr_t loc, int asi, u_char value)); 449 static __inline__ void stha __P((paddr_t loc, int asi, u_short value)); 450 static __inline__ void sta __P((paddr_t loc, int asi, u_int value)); 451 static __inline__ void stxa __P((paddr_t loc, int asi, u_int64_t value)); 452 static __inline__ void stda __P((paddr_t loc, int asi, u_int64_t value)); 453 454 #ifdef __arch64__ 455 static __inline__ u_char 456 lduba(paddr_t loc, int asi) 457 { 458 register unsigned int _lduba_v; 459 460 if (PHYS_ASI(asi)) { 461 __asm __volatile("wr %3,%%g0,%%asi; " 462 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " 463 " lduba [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " 464 " stxa %%g0,[%1] %4; membar #Sync" : 465 "=&r" (_lduba_v), "=r" (loc): 466 "r" ((unsigned long)(loc)), 467 "r" (asi), "n" (ASI_DCACHE_TAG)); 468 } else { 469 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : 470 "=r" (_lduba_v) : 471 "r" ((unsigned long)(loc)), "r" (asi)); 472 } 473 return (_lduba_v); 474 } 475 #else 476 static __inline__ u_char 477 lduba(paddr_t loc, int asi) 478 { 479 register unsigned int _lduba_v, _loc_hi, _pstate; 480 481 _loc_hi = (((u_int64_t)loc)>>32); 482 if (PHYS_ASI(asi)) { 483 __asm __volatile("wr %4,%%g0,%%asi; " 484 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " 485 " sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " 486 " membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; " 487 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : 488 "=&r" (_lduba_v), "=&r" (_pstate) : 489 "r" ((unsigned long)(loc)), "r" (_loc_hi), 490 "r" (asi), "n" (ASI_DCACHE_TAG)); 491 } else { 492 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 493 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : 494 "r" ((unsigned long)(loc)), 495 "r" (_loc_hi), "r" (asi)); 496 } 497 return (_lduba_v); 498 } 499 #endif 500 501 #ifdef __arch64__ 502 /* load half-word from alternate address space */ 503 static __inline__ u_short 504 lduha(paddr_t loc, int asi) 505 { 506 register unsigned int _lduha_v; 507 508 if (PHYS_ASI(asi)) { 509 __asm __volatile("wr %3,%%g0,%%asi; " 510 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " 511 " lduha [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " 512 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lduha_v), "=r" (loc) : 513 "r" ((unsigned long)(loc)), 514 "r" (asi), "n" (ASI_DCACHE_TAG)); 515 } else { 516 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : 517 "=r" (_lduha_v) : 518 "r" ((unsigned long)(loc)), "r" (asi)); 519 } 520 return (_lduha_v); 521 } 522 #else 523 /* load half-word from alternate address space */ 524 static __inline__ u_short 525 lduha(paddr_t loc, int asi) { 526 register unsigned int _lduha_v, _loc_hi, _pstate; 527 528 _loc_hi = (((u_int64_t)loc)>>32); 529 530 if (PHYS_ASI(asi)) { 531 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " 532 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " 533 " or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; " 534 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : 535 "=&r" (_lduha_v), "=&r" (_pstate) : 536 "r" ((unsigned long)(loc)), "r" (_loc_hi), 537 "r" (asi), "n" (ASI_DCACHE_TAG)); 538 } else { 539 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 540 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : 541 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 542 } 543 return (_lduha_v); 544 } 545 #endif 546 547 548 #ifdef __arch64__ 549 /* load unsigned int from alternate address space */ 550 static __inline__ u_int 551 lda(paddr_t loc, int asi) 552 { 553 register unsigned int _lda_v; 554 555 if (PHYS_ASI(asi)) { 556 __asm __volatile("wr %3,%%g0,%%asi; " 557 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " 558 " lda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " 559 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) : 560 "r" ((unsigned long)(loc)), 561 "r" (asi), "n" (ASI_DCACHE_TAG)); 562 } else { 563 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : 564 "=r" (_lda_v) : 565 "r" ((unsigned long)(loc)), "r" (asi)); 566 } 567 return (_lda_v); 568 } 569 570 /* load signed int from alternate address space */ 571 static __inline__ int 572 ldswa(paddr_t loc, int asi) 573 { 574 register int _lda_v; 575 576 if (PHYS_ASI(asi)) { 577 __asm __volatile("wr %3,%%g0,%%asi; " 578 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " 579 " ldswa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " 580 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) : 581 "r" ((unsigned long)(loc)), 582 "r" (asi), "n" (ASI_DCACHE_TAG)); 583 } else { 584 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : 585 "=r" (_lda_v) : 586 "r" ((unsigned long)(loc)), "r" (asi)); 587 } 588 return (_lda_v); 589 } 590 #else /* __arch64__ */ 591 /* load unsigned int from alternate address space */ 592 static __inline__ u_int 593 lda(paddr_t loc, int asi) 594 { 595 register unsigned int _lda_v, _loc_hi, _pstate; 596 597 _loc_hi = (((u_int64_t)loc)>>32); 598 if (PHYS_ASI(asi)) { 599 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" 600 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " 601 " sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " 602 " wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; " 603 " stxa %%g0,[%1] %5; membar #Sync" : "=&r" (_lda_v), "=&r" (_pstate) : 604 "r" ((unsigned long)(loc)), "r" (_loc_hi), 605 "r" (asi), "n" (ASI_DCACHE_TAG)); 606 } else { 607 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 608 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : 609 "r" ((unsigned long)(loc)), 610 "r" (_loc_hi), "r" (asi)); 611 } 612 return (_lda_v); 613 } 614 615 /* load signed int from alternate address space */ 616 static __inline__ int 617 ldswa(paddr_t loc, int asi) 618 { 619 register int _lda_v, _loc_hi, _pstate; 620 621 _loc_hi = (((u_int64_t)loc)>>32); 622 if (PHYS_ASI(asi)) { 623 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" 624 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" 625 " or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; " 626 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : 627 "=&r" (_lda_v), "=&r" (_pstate) : 628 "r" ((unsigned long)(loc)), "r" (_loc_hi), 629 "r" (asi), "n" (ASI_DCACHE_TAG)); 630 } else { 631 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 632 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : 633 "r" ((unsigned long)(loc)), 634 "r" (_loc_hi), "r" (asi)); 635 } 636 return (_lda_v); 637 } 638 #endif /* __arch64__ */ 639 640 #ifdef __arch64__ 641 /* load 64-bit int from alternate address space -- these should never be used */ 642 static __inline__ u_int64_t 643 ldda(paddr_t loc, int asi) 644 { 645 register long long _lda_v; 646 647 if (PHYS_ASI(asi)) { 648 __asm __volatile("wr %3,%%g0,%%asi; " 649 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " 650 " ldda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " 651 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=&r" (loc) : 652 "r" ((unsigned long)(loc)), 653 "r" (asi), "n" (ASI_DCACHE_TAG)); 654 } else { 655 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : 656 "=r" (_lda_v) : 657 "r" ((unsigned long)(loc)), "r" (asi)); 658 } 659 return (_lda_v); 660 } 661 #else 662 /* load 64-bit int from alternate address space */ 663 static __inline__ u_int64_t 664 ldda(paddr_t loc, int asi) 665 { 666 register long long _lda_v, _loc_hi, _pstate; 667 668 _loc_hi = (((u_int64_t)loc)>>32); 669 if (PHYS_ASI(asi)) { 670 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" 671 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" 672 " sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; " 673 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : 674 "=&r" (_lda_v), "=&r" (_pstate) : 675 "r" ((unsigned long)(loc)), "r" (_loc_hi), 676 "r" (asi), "n" (ASI_DCACHE_TAG)); 677 } else { 678 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 679 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : 680 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 681 } 682 return (_lda_v); 683 } 684 #endif 685 686 687 #ifdef __arch64__ 688 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 689 static __inline__ u_int64_t 690 ldxa(paddr_t loc, int asi) 691 { 692 register unsigned long _lda_v; 693 694 if (PHYS_ASI(asi)) { 695 __asm __volatile("wr %3,%%g0,%%asi; " 696 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " 697 " ldxa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " 698 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) : 699 "r" ((unsigned long)(loc)), 700 "r" (asi), "n" (ASI_DCACHE_TAG)); 701 } else { 702 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : 703 "=r" (_lda_v) : 704 "r" ((unsigned long)(loc)), "r" (asi)); 705 } 706 return (_lda_v); 707 } 708 #else 709 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 710 static __inline__ u_int64_t 711 ldxa(paddr_t loc, int asi) 712 { 713 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; 714 715 _loc_hi = (((u_int64_t)loc)>>32); 716 if (PHYS_ASI(asi)) { 717 __asm __volatile("wr %4,%%g0,%%asi; " 718 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " 719 " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " 720 " wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; " 721 " srlx %0,32,%1; srl %0,0,%0" : 722 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : 723 "r" ((unsigned long)(loc)), "r" (_loc_hi), 724 "r" (asi), "n" (ASI_DCACHE_TAG)); 725 } else { 726 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 727 " or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : 728 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : 729 "r" ((unsigned long)(loc)), "r" (_loc_hi), 730 "r" (asi)); 731 } 732 return ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); 733 } 734 #endif 735 736 /* store byte to alternate address space */ 737 #ifdef __arch64__ 738 static __inline__ void 739 stba(paddr_t loc, int asi, u_char value) 740 { 741 if (PHYS_ASI(asi)) { 742 __asm __volatile("wr %3,%%g0,%%asi; stba %1,[%2]%%asi;" 743 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : 744 "r" ((int)(value)), "r" ((unsigned long)(loc)), 745 "r" (asi), "n" (ASI_DCACHE_TAG)); 746 } else { 747 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : 748 "r" ((int)(value)), "r" ((unsigned long)(loc)), 749 "r" (asi)); 750 } 751 } 752 #else 753 static __inline__ void 754 stba(paddr_t loc, int asi, u_char value) 755 { 756 register int _loc_hi, _pstate; 757 758 _loc_hi = (((u_int64_t)loc)>>32); 759 if (PHYS_ASI(asi)) { 760 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" 761 " or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate; " 762 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : 763 "=&r" (_loc_hi), "=&r" (_pstate) : 764 "r" ((int)(value)), "r" ((unsigned long)(loc)), 765 "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); 766 } else { 767 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 768 " or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : 769 "r" ((int)(value)), "r" ((unsigned long)(loc)), 770 "r" (_loc_hi), "r" (asi)); 771 } 772 } 773 #endif 774 775 /* store half-word to alternate address space */ 776 #ifdef __arch64__ 777 static __inline__ void 778 stha(paddr_t loc, int asi, u_short value) 779 { 780 if (PHYS_ASI(asi)) { 781 __asm __volatile("wr %3,%%g0,%%asi; stha %1,[%2]%%asi;" 782 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : 783 "r" ((int)(value)), "r" ((unsigned long)(loc)), 784 "r" (asi), "n" (ASI_DCACHE_TAG) : "memory"); 785 } else { 786 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : 787 "r" ((int)(value)), "r" ((unsigned long)(loc)), 788 "r" (asi) : "memory"); 789 } 790 } 791 #else 792 static __inline__ void 793 stha(paddr_t loc, int asi, u_short value) 794 { 795 register int _loc_hi, _pstate; 796 797 _loc_hi = (((u_int64_t)loc)>>32); 798 if (PHYS_ASI(asi)) { 799 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" 800 " or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate; " 801 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : 802 "=&r" (_loc_hi), "=&r" (_pstate) : 803 "r" ((int)(value)), "r" ((unsigned long)(loc)), 804 "r" (_loc_hi), "r" (asi), 805 "n" (ASI_DCACHE_TAG) : "memory"); 806 } else { 807 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 808 " or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : 809 "r" ((int)(value)), "r" ((unsigned long)(loc)), 810 "r" (_loc_hi), "r" (asi) : "memory"); 811 } 812 } 813 #endif 814 815 816 /* store int to alternate address space */ 817 #ifdef __arch64__ 818 static __inline__ void 819 sta(paddr_t loc, int asi, u_int value) 820 { 821 if (PHYS_ASI(asi)) { 822 __asm __volatile("wr %3,%%g0,%%asi; sta %1,[%2]%%asi;" 823 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : 824 "r" ((int)(value)), "r" ((unsigned long)(loc)), 825 "r" (asi), "n" (ASI_DCACHE_TAG) : "memory"); 826 } else { 827 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : 828 "r" ((int)(value)), "r" ((unsigned long)(loc)), 829 "r" (asi) : "memory"); 830 } 831 } 832 #else 833 static __inline__ void 834 sta(paddr_t loc, int asi, u_int value) 835 { 836 register int _loc_hi, _pstate; 837 838 _loc_hi = (((u_int64_t)loc)>>32); 839 if (PHYS_ASI(asi)) { 840 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" 841 " or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate; " 842 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : 843 "=&r" (_loc_hi), "=&r" (_pstate) : 844 "r" ((int)(value)), "r" ((unsigned long)(loc)), 845 "r" (_loc_hi), "r" (asi), 846 "n" (ASI_DCACHE_TAG) : "memory"); 847 } else { 848 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 849 " or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : 850 "r" ((int)(value)), "r" ((unsigned long)(loc)), 851 "r" (_loc_hi), "r" (asi) : "memory"); 852 } 853 } 854 #endif 855 856 /* store 64-bit int to alternate address space */ 857 #ifdef __arch64__ 858 static __inline__ void 859 stda(paddr_t loc, int asi, u_int64_t value) 860 { 861 if (PHYS_ASI(asi)) { 862 __asm __volatile("wr %3,%%g0,%%asi; stda %1,[%2]%%asi;" 863 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : 864 "r" ((int)(value)), "r" ((unsigned long)(loc)), 865 "r" (asi), "n" (ASI_DCACHE_TAG) : "memory"); 866 } else { 867 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : 868 "r" ((long long)(value)), "r" ((unsigned long)(loc)), 869 "r" (asi) : "memory"); 870 } 871 } 872 #else 873 static __inline__ void 874 stda(paddr_t loc, int asi, u_int64_t value) 875 { 876 register int _loc_hi, _pstate; 877 878 _loc_hi = (((u_int64_t)loc)>>32); 879 if (PHYS_ASI(asi)) { 880 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " 881 " or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate;" 882 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : 883 "=&r" (_loc_hi), "=&r" (_pstate) : 884 "r" ((long long)(value)), "r" ((unsigned long)(loc)), 885 "r" (_loc_hi), "r" (asi), 886 "n" (ASI_DCACHE_TAG) : "memory"); 887 } else { 888 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 889 " or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : 890 "r" ((long long)(value)), "r" ((unsigned long)(loc)), 891 "r" (_loc_hi), "r" (asi) : "memory"); 892 } 893 } 894 #endif 895 896 #ifdef __arch64__ 897 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 898 static __inline__ void 899 stxa(paddr_t loc, int asi, u_int64_t value) 900 { 901 if (PHYS_ASI(asi)) { 902 __asm __volatile("wr %3,%%g0,%%asi; stxa %1,[%2]%%asi;" 903 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : 904 "r" ((int)(value)), "r" ((unsigned long)(loc)), 905 "r" (asi), "n" (ASI_DCACHE_TAG) : "memory"); 906 } else { 907 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : 908 "r" ((unsigned long)(value)), 909 "r" ((unsigned long)(loc)), "r" (asi) : "memory"); 910 } 911 } 912 #else 913 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 914 static __inline__ void 915 stxa(paddr_t loc, int asi, u_int64_t value) 916 { 917 int _stxa_lo, _stxa_hi, _loc_hi; 918 919 _stxa_lo = value; 920 _stxa_hi = ((u_int64_t)value)>>32; 921 _loc_hi = (((u_int64_t)(u_long)loc)>>32); 922 923 if (PHYS_ASI(asi)) { 924 __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " 925 " or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " 926 " stxa %1,[%0]%%asi; wrpr %3,0,%%pstate; " 927 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %8; membar #Sync" : 928 "=&r" (_loc_hi), "=&r" (_stxa_hi), 929 "=&r" ((int)(_stxa_lo)) : 930 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 931 "r" ((unsigned long)(loc)), "r" (_loc_hi), 932 "r" (asi), "n" (ASI_DCACHE_TAG) : "memory"); 933 } else { 934 __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " 935 " or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : 936 "=&r" (_loc_hi), "=&r" (_stxa_hi) : 937 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 938 "r" ((unsigned long)(loc)), "r" (_loc_hi), 939 "r" (asi) : "memory"); 940 } 941 } 942 #endif 943 944 #if 0 945 #ifdef __arch64__ 946 /* load byte from alternate address space */ 947 #define lduba(loc, asi) ({ \ 948 register unsigned int _lduba_v; \ 949 if (PHYS_ASI(asi)) { \ 950 __asm __volatile("wr %3,%%g0,%%asi; " \ 951 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 952 " lduba [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " \ 953 " stxa %%g0,[%1] %4; membar #Sync" : \ 954 "=&r" (_lduba_v), "=r" (loc): \ 955 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 956 } else { \ 957 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 958 "=r" (_lduba_v) : \ 959 "r" ((unsigned long)(loc)), "r" (asi)); \ 960 } \ 961 _lduba_v; \ 962 }) 963 #else 964 /* load byte from alternate address space */ 965 #define lduba(loc, asi) ({ \ 966 register unsigned int _lduba_v, _loc_hi, _pstate; \ 967 _loc_hi = (((u_int64_t)loc)>>32); \ 968 if (PHYS_ASI(asi)) { \ 969 __asm __volatile("wr %4,%%g0,%%asi; " \ 970 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " \ 971 " sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " \ 972 " membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; " \ 973 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : \ 974 "=&r" (_lduba_v), "=&r" (_pstate) : \ 975 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 976 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 977 } else { \ 978 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 979 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 980 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 981 } \ 982 _lduba_v; \ 983 }) 984 #endif 985 986 #ifdef __arch64__ 987 /* load half-word from alternate address space */ 988 #define lduha(loc, asi) ({ \ 989 register unsigned int _lduha_v; \ 990 if (PHYS_ASI(asi)) { \ 991 __asm __volatile("wr %3,%%g0,%%asi; " \ 992 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 993 " lduha [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " \ 994 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lduha_v), "=r" (loc) : \ 995 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 996 } else { \ 997 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 998 "r" ((unsigned long)(loc)), "r" (asi)); \ 999 } \ 1000 _lduha_v; \ 1001 }) 1002 #else 1003 /* load half-word from alternate address space */ 1004 #define lduha(loc, asi) ({ \ 1005 register unsigned int _lduha_v, _loc_hi, _pstate; \ 1006 _loc_hi = (((u_int64_t)loc)>>32); \ 1007 if (PHYS_ASI(asi)) { \ 1008 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \ 1009 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " \ 1010 " or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; " \ 1011 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : \ 1012 "=&r" (_lduha_v), "=&r" (_pstate) : \ 1013 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 1014 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1015 } else { \ 1016 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 1017 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 1018 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 1019 } \ 1020 _lduha_v; \ 1021 }) 1022 #endif 1023 1024 #ifdef __arch64__ 1025 /* load unsigned int from alternate address space */ 1026 #define lda(loc, asi) ({ \ 1027 register unsigned int _lda_v; \ 1028 if (PHYS_ASI(asi)) { \ 1029 __asm __volatile("wr %3,%%g0,%%asi; " \ 1030 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 1031 " lda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " \ 1032 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) : \ 1033 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1034 } else { \ 1035 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 1036 "r" ((unsigned long)(loc)), "r" (asi)); \ 1037 } \ 1038 _lda_v; \ 1039 }) 1040 1041 /* load signed int from alternate address space */ 1042 #define ldswa(loc, asi) ({ \ 1043 register int _lda_v; \ 1044 if (PHYS_ASI(asi)) { \ 1045 __asm __volatile("wr %3,%%g0,%%asi; " \ 1046 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 1047 " ldswa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " \ 1048 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) : \ 1049 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1050 } else { \ 1051 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 1052 "r" ((unsigned long)(loc)), "r" (asi)); \ 1053 } \ 1054 _lda_v; \ 1055 }) 1056 #else /* __arch64__ */ 1057 /* load unsigned int from alternate address space */ 1058 #define lda(loc, asi) ({ \ 1059 register unsigned int _lda_v, _loc_hi, _pstate; \ 1060 _loc_hi = (((u_int64_t)loc)>>32); \ 1061 if (PHYS_ASI(asi)) { \ 1062 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 1063 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " \ 1064 " sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " \ 1065 " wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; " \ 1066 " stxa %%g0,[%1] %5; membar #Sync" : "=&r" (_lda_v), "=&r" (_pstate) : \ 1067 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 1068 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1069 } else { \ 1070 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 1071 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 1072 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 1073 } \ 1074 _lda_v; \ 1075 }) 1076 1077 /* load signed int from alternate address space */ 1078 #define ldswa(loc, asi) ({ \ 1079 register int _lda_v, _loc_hi, _pstate; \ 1080 _loc_hi = (((u_int64_t)loc)>>32); \ 1081 if (PHYS_ASI(asi)) { \ 1082 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 1083 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" \ 1084 " or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; " \ 1085 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : \ 1086 "=&r" (_lda_v), "=&r" (_pstate) : \ 1087 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 1088 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1089 } else { \ 1090 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 1091 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ 1092 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 1093 } \ 1094 _lda_v; \ 1095 }) 1096 #endif /* __arch64__ */ 1097 1098 #ifdef __arch64__ 1099 /* load 64-bit int from alternate address space -- these should never be used */ 1100 #define ldda(loc, asi) ({ \ 1101 register long long _lda_v; \ 1102 if (PHYS_ASI(asi)) { \ 1103 __asm __volatile("wr %3,%%g0,%%asi; " \ 1104 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 1105 " ldda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " \ 1106 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=&r" (loc) : \ 1107 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1108 } else { \ 1109 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 1110 "r" ((unsigned long)(loc)), "r" (asi)); \ 1111 } \ 1112 _lda_v; \ 1113 }) 1114 #else 1115 /* load 64-bit int from alternate address space */ 1116 #define ldda(loc, asi) ({ \ 1117 register long long _lda_v, _loc_hi, _pstate; \ 1118 _loc_hi = (((u_int64_t)loc)>>32); \ 1119 if (PHYS_ASI(asi)) { \ 1120 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 1121 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" \ 1122 " sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; " \ 1123 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" : \ 1124 "=&r" (_lda_v), "=&r" (_pstate) : \ 1125 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1126 } else { \ 1127 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 1128 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 1129 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 1130 } \ 1131 _lda_v; \ 1132 }) 1133 #endif 1134 1135 #ifdef __arch64__ 1136 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 1137 #define ldxa(loc, asi) ({ \ 1138 register unsigned long _lda_v; \ 1139 if (PHYS_ASI(asi)) { \ 1140 __asm __volatile("wr %3,%%g0,%%asi; "\ 1141 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 1142 " ldxa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; " \ 1143 " stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) : \ 1144 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1145 } else { \ 1146 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 1147 "r" ((unsigned long)(loc)), "r" (asi)); \ 1148 } \ 1149 _lda_v; \ 1150 }) 1151 #else 1152 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 1153 #define ldxa(loc, asi) ({ \ 1154 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \ 1155 _loc_hi = (((u_int64_t)loc)>>32); \ 1156 if (PHYS_ASI(asi)) { \ 1157 __asm __volatile("wr %4,%%g0,%%asi; " \ 1158 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " \ 1159 " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \ 1160 " wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; " \ 1161 " srlx %0,32,%1; srl %0,0,%0" : \ 1162 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 1163 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 1164 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1165 } else { \ 1166 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 1167 " or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 1168 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 1169 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 1170 } \ 1171 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 1172 }) 1173 #endif 1174 1175 1176 /* store byte to alternate address space */ 1177 #ifdef __arch64__ 1178 #define stba(loc, asi, value) ({ \ 1179 if (PHYS_ASI(asi)) { \ 1180 __asm __volatile("wr %3,%%g0,%%asi; stba %1,[%2]%%asi;" \ 1181 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : \ 1182 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1183 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1184 } else { \ 1185 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \ 1186 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 1187 } \ 1188 }) 1189 #else 1190 #define stba(loc, asi, value) ({ \ 1191 register int _loc_hi, _pstate; \ 1192 _loc_hi = (((u_int64_t)loc)>>32); \ 1193 if (PHYS_ASI(asi)) { \ 1194 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 1195 " or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate; " \ 1196 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : \ 1197 "=&r" (_loc_hi), "=&r" (_pstate) : \ 1198 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1199 "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1200 } else { \ 1201 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 1202 " or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 1203 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1204 "r" (_loc_hi), "r" (asi)); \ 1205 } \ 1206 }) 1207 #endif 1208 1209 /* store half-word to alternate address space */ 1210 #ifdef __arch64__ 1211 #define stha(loc, asi, value) ({ \ 1212 if (PHYS_ASI(asi)) { \ 1213 __asm __volatile("wr %3,%%g0,%%asi; stha %1,[%2]%%asi;" \ 1214 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : \ 1215 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1216 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1217 } else { \ 1218 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \ 1219 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 1220 } \ 1221 }) 1222 #else 1223 #define stha(loc, asi, value) ({ \ 1224 register int _loc_hi, _pstate; \ 1225 _loc_hi = (((u_int64_t)loc)>>32); \ 1226 if (PHYS_ASI(asi)) { \ 1227 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 1228 " or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate; " \ 1229 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : \ 1230 "=&r" (_loc_hi), "=&r" (_pstate) : \ 1231 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1232 "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1233 } else { \ 1234 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 1235 " or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 1236 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1237 "r" (_loc_hi), "r" (asi)); \ 1238 } \ 1239 }) 1240 #endif 1241 1242 /* store int to alternate address space */ 1243 #ifdef __arch64__ 1244 #define sta(loc, asi, value) ({ \ 1245 if (PHYS_ASI(asi)) { \ 1246 __asm __volatile("wr %3,%%g0,%%asi; sta %1,[%2]%%asi;" \ 1247 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : \ 1248 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1249 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1250 } else { \ 1251 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \ 1252 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 1253 } \ 1254 }) 1255 #else 1256 #define sta(loc, asi, value) ({ \ 1257 register int _loc_hi, _pstate; \ 1258 _loc_hi = (((u_int64_t)loc)>>32); \ 1259 if (PHYS_ASI(asi)) { \ 1260 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 1261 " or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate; " \ 1262 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : \ 1263 "=&r" (_loc_hi), "=&r" (_pstate) : \ 1264 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1265 "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1266 } else { \ 1267 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 1268 " or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 1269 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1270 "r" (_loc_hi), "r" (asi)); \ 1271 } \ 1272 }) 1273 #endif 1274 1275 /* store 64-bit int to alternate address space */ 1276 #ifdef __arch64__ 1277 #define stda(loc, asi, value) ({ \ 1278 if (PHYS_ASI(asi)) { \ 1279 __asm __volatile("wr %3,%%g0,%%asi; stda %1,[%2]%%asi;" \ 1280 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : \ 1281 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1282 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1283 } else { \ 1284 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \ 1285 "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 1286 } \ 1287 }) 1288 #else 1289 #define stda(loc, asi, value) ({ \ 1290 register int _loc_hi, _pstate; \ 1291 _loc_hi = (((u_int64_t)loc)>>32); \ 1292 if (PHYS_ASI(asi)) { \ 1293 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \ 1294 " or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate;" \ 1295 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" : \ 1296 "=&r" (_loc_hi), "=&r" (_pstate) : \ 1297 "r" ((long long)(value)), "r" ((unsigned long)(loc)), \ 1298 "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1299 } else { \ 1300 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 1301 " or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 1302 "r" ((long long)(value)), "r" ((unsigned long)(loc)), \ 1303 "r" (_loc_hi), "r" (asi)); \ 1304 } \ 1305 }) 1306 #endif 1307 1308 #ifdef __arch64__ 1309 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 1310 #define stxa(loc, asi, value) ({ \ 1311 if (PHYS_ASI(asi)) { \ 1312 __asm __volatile("wr %3,%%g0,%%asi; stxa %1,[%2]%%asi;" \ 1313 " andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %4; membar #Sync" : "=&r" (loc) : \ 1314 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 1315 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1316 } else { \ 1317 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : \ 1318 "r" ((unsigned long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 1319 }) 1320 #else 1321 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 1322 #define stxa(loc, asi, value) ({ \ 1323 int _stxa_lo, _stxa_hi, _loc_hi; \ 1324 _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \ 1325 _loc_hi = (((u_int64_t)(u_long)loc)>>32); \ 1326 if (PHYS_ASI(asi)) { \ 1327 __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \ 1328 " or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \ 1329 " stxa %1,[%0]%%asi; wrpr %3,0,%%pstate; " \ 1330 " andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %8; membar #Sync": \ 1331 "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \ 1332 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 1333 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 1334 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 1335 } else { \ 1336 __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \ 1337 " or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \ 1338 "=&r" (_loc_hi), "=&r" (_stxa_hi) : \ 1339 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 1340 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 1341 } \ 1342 }) 1343 #endif 1344 #endif 1345 1346 /* flush address from data cache */ 1347 #define flush(loc) ({ \ 1348 __asm __volatile("flush %0" : : \ 1349 "r" ((unsigned long)(loc))); \ 1350 }) 1351 1352 /* Flush a D$ line */ 1353 #if 0 1354 #define flushline(loc) ({ \ 1355 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 1356 membar_sync(); \ 1357 }) 1358 #else 1359 #define flushline(loc) 1360 #endif 1361 1362 /* The following two enable or disable the dcache in the LSU control register */ 1363 #define dcenable() ({ \ 1364 int res; \ 1365 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 1366 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 1367 }) 1368 #define dcdisable() ({ \ 1369 int res; \ 1370 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 1371 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 1372 }) 1373 1374 /* 1375 * SPARC V9 memory barrier instructions. 1376 */ 1377 /* Make all stores complete before next store */ 1378 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 1379 /* Make all loads complete before next store */ 1380 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 1381 /* Make all stores complete before next load */ 1382 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 1383 /* Make all loads complete before next load */ 1384 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 1385 /* Complete all outstanding memory operations and exceptions */ 1386 #define membar_sync() __asm __volatile("membar #Sync" : :) 1387 /* Complete all outstanding memory operations */ 1388 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 1389 /* Complete all outstanding stores before any new loads */ 1390 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 1391 1392 #ifdef __arch64__ 1393 /* read 64-bit %tick register */ 1394 #define tick() ({ \ 1395 register u_long _tick_tmp; \ 1396 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 1397 _tick_tmp; \ 1398 }) 1399 #else 1400 /* read 64-bit %tick register on 32-bit system */ 1401 #define tick() ({ \ 1402 register int _tick_hi = 0, _tick_lo = 0; \ 1403 __asm __volatile("rdpr %%tick, %1; srlx %0,32,%2; srl %0,0,%0 " \ 1404 : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ 1405 (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ 1406 }) 1407 #endif 1408 1409 extern void next_tick __P((long)); 1410 #endif 1411
Indexes created Sat Oct 25 16:10:12 GMT 2025