ctlreg.h revision 1.19
1 /* $NetBSD: ctlreg.h,v 1.19 2000/06/20 18:06:12 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 /* 27 * Sun 4u control registers. (includes address space definitions 28 * and some registers in control space). 29 */ 30 31 /* 32 * The Alternate address spaces. 33 * 34 * 0x00-0x7f are privileged 35 * 0x80-0xff can be used by users 36 */ 37 38 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 39 40 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 41 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 42 43 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 44 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 45 46 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 47 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 48 49 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 50 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 51 52 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 53 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 54 55 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 56 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 57 58 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 59 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 60 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 61 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 62 63 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 64 65 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 66 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 67 68 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 69 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 70 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 71 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 72 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 73 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 74 75 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 76 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 77 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 78 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 79 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 80 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 81 82 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 83 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 84 85 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 86 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 87 88 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 89 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 90 91 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 92 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 93 94 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 95 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 96 #define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */ 97 #define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */ 98 99 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 100 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 101 #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 102 #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 103 104 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 105 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 106 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 107 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 108 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 109 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 110 111 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 112 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 113 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 114 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 115 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 116 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 117 118 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 119 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 120 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 121 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 122 123 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 124 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 125 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 126 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 127 128 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 129 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 130 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 131 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 132 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 133 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 134 135 136 /* 137 * These are the shorter names used by Solaris 138 */ 139 140 #define ASI_N ASI_NUCLEUS 141 #define ASI_NL ASI_NUCLEUS_LITTLE 142 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 143 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 144 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 145 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 146 #define ASI_P ASI_PRIMARY 147 #define ASI_S ASI_SECONDARY 148 #define ASI_PNF ASI_PRIMARY_NO_FAULT 149 #define ASI_SNF ASI_SECONDARY_NO_FAULT 150 #define ASI_PL ASI_PRIMARY_LITTLE 151 #define ASI_SL ASI_SECONDARY_LITTLE 152 #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE 153 #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE 154 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 155 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 156 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 157 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 158 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 159 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 160 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 161 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 162 #define ASI_BLK_P ASI_BLOCK_PRIMARY 163 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 164 #define ASI_BLK_S ASI_BLOCK_SECONDARY 165 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 166 167 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 168 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 169 170 /* 171 * The following are 4u control registers 172 */ 173 174 175 /* Get the CPU's UPAID */ 176 #define UPA_CR_MID(x) (((x)>>17)&0x1f) 177 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 178 179 /* 180 * [4u] MMU and Cache Control Register (MCCR) 181 * use ASI = 0x45 182 */ 183 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 184 #define MCCR 0x00 185 186 /* MCCR Bits and their meanings */ 187 #define MCCR_DMMU_EN 0x08 188 #define MCCR_IMMU_EN 0x04 189 #define MCCR_DCACHE_EN 0x02 190 #define MCCR_ICACHE_EN 0x01 191 192 193 /* 194 * MMU control registers 195 */ 196 197 /* Choose an MMU */ 198 #define ASI_DMMU 0x58 199 #define ASI_IMMU 0x50 200 201 /* Other assorted MMU ASIs */ 202 #define ASI_IMMU_8KPTR 0x51 203 #define ASI_IMMU_64KPTR 0x52 204 #define ASI_IMMU_DATA_IN 0x54 205 #define ASI_IMMU_TLB_DATA 0x55 206 #define ASI_IMMU_TLB_TAG 0x56 207 #define ASI_DMMU_8KPTR 0x59 208 #define ASI_DMMU_64KPTR 0x5a 209 #define ASI_DMMU_DATA_IN 0x5c 210 #define ASI_DMMU_TLB_DATA 0x5d 211 #define ASI_DMMU_TLB_TAG 0x5e 212 213 /* 214 * The following are the control registers 215 * They work on both MMUs unless noted. 216 * 217 * Register contents are defined later on individual registers. 218 */ 219 #define TSB_TAG_TARGET 0x0 220 #define TLB_DATA_IN 0x0 221 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 222 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 223 #define SFSR 0x18 224 #define SFAR 0x20 /* fault address -- DMMU only */ 225 #define TSB 0x28 226 #define TLB_TAG_ACCESS 0x30 227 #define VIRTUAL_WATCHPOINT 0x38 228 #define PHYSICAL_WATCHPOINT 0x40 229 230 /* Tag Target bits */ 231 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 232 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 233 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 234 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 235 236 /* SFSR bits for both D_SFSR and I_SFSR */ 237 #define SFSR_ASI(x) ((x)>>16) 238 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 239 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 240 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 241 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 242 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 243 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 244 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 245 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 246 #define SFSR_CTXT(x) (((x)>>4)&0x3) 247 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 248 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 249 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 250 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 251 #define SFSR_W 0x00004 /* DMMU: attempted write */ 252 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 253 #define SFSR_FV 0x00001 /* Fault is valid */ 254 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 255 256 #if 0 257 /* Old bits */ 258 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 259 #else 260 /* New bits */ 261 #define SFSR_BITS "\177\20" \ 262 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 263 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 264 #endif 265 266 /* ASFR bits */ 267 #define ASFR_ME 0x100000000LL 268 #define ASFR_PRIV 0x080000000LL 269 #define ASFR_ISAP 0x040000000LL 270 #define ASFR_ETP 0x020000000LL 271 #define ASFR_IVUE 0x010000000LL 272 #define ASFR_TO 0x008000000LL 273 #define ASFR_BERR 0x004000000LL 274 #define ASFR_LDP 0x002000000LL 275 #define ASFR_CP 0x001000000LL 276 #define ASFR_WP 0x000800000LL 277 #define ASFR_EDP 0x000400000LL 278 #define ASFR_UE 0x000200000LL 279 #define ASFR_CE 0x000100000LL 280 #define ASFR_ETS 0x0000f0000LL 281 #define ASFT_P_SYND 0x00000ffffLL 282 283 #define AFSR_BITS "\177\20" \ 284 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 285 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 286 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 287 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 288 289 /* 290 * Here's the spitfire TSB control register bits. 291 * 292 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 293 */ 294 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 295 #define TSB_SIZE_1K 0x01 296 #define TSB_SIZE_2K 0x02 297 #define TSB_SIZE_4K 0x03 298 #define TSB_SIZE_8K 0x04 299 #define TSB_SIZE_16K 0x05 300 #define TSB_SIZE_32K 0x06 301 #define TSB_SIZE_64K 0x07 302 #define TSB_SPLIT 0x1000 303 #define TSB_BASE 0xffffffffffffe000 304 305 /* TLB Tag Access bits */ 306 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 307 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 308 309 /* 310 * TLB demap registers. TTEs are defined in v9pte.h 311 * 312 * Use the address space to select between IMMU and DMMU. 313 * The address of the register selects which context register 314 * to read the ASI from. 315 * 316 * The data stored in the register is interpreted as the VA to 317 * use. The DEMAP_CTX_<> registers ignore the address and demap the 318 * entire ASI. 319 * 320 */ 321 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 322 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 323 324 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 325 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 326 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 327 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 328 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 329 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 330 331 /* 332 * Interrupt registers. This really gets hairy. 333 */ 334 335 /* IRSR -- Interrupt Receive Status Ragister */ 336 #define ASI_IRSR 0x49 337 #define IRSR 0x00 338 #define IRSR_BUSY 0x020 339 #define IRSR_MID(x) (x&0x1f) 340 341 /* IRDR -- Interrupt Receive Data Registers */ 342 #define ASI_IRDR 0x7f 343 #define IRDR_0H 0x40 344 #define IRDR_0L 0x48 /* unimplemented */ 345 #define IRDR_1H 0x50 346 #define IRDR_1L 0x58 /* unimplemented */ 347 #define IRDR_2H 0x60 348 #define IRDR_2L 0x68 /* unimplemented */ 349 #define IRDR_3H 0x70 /* unimplemented */ 350 #define IRDR_3L 0x78 /* unimplemented */ 351 352 /* SOFTINT ASRs */ 353 #define SET_SOFTINT %asr20 /* Sets these bits */ 354 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 355 #define SOFTINT %asr22 /* Reads the register */ 356 #define TICK_CMPR %asr23 357 358 #define TICK_INT 0x01 /* level-14 clock tick */ 359 #define SOFTINT1 (0x1<<1) 360 #define SOFTINT2 (0x1<<2) 361 #define SOFTINT3 (0x1<<3) 362 #define SOFTINT4 (0x1<<4) 363 #define SOFTINT5 (0x1<<5) 364 #define SOFTINT6 (0x1<<6) 365 #define SOFTINT7 (0x1<<7) 366 #define SOFTINT8 (0x1<<8) 367 #define SOFTINT9 (0x1<<9) 368 #define SOFTINT10 (0x1<<10) 369 #define SOFTINT11 (0x1<<11) 370 #define SOFTINT12 (0x1<<12) 371 #define SOFTINT13 (0x1<<13) 372 #define SOFTINT14 (0x1<<14) 373 #define SOFTINT15 (0x1<<15) 374 375 /* Interrupt Dispatch -- usually reserved for cross-calls */ 376 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 377 #define IDSR 0x00 378 #define IDSR_NACK 0x02 379 #define IDSR_BUSY 0x01 380 381 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 382 #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */ 383 #define IDDR_0H 0x40 /* Store data to send in these regs */ 384 #define IDDR_0L 0x48 /* unimplemented */ 385 #define IDDR_1H 0x50 386 #define IDDR_1L 0x58 /* unimplemented */ 387 #define IDDR_2H 0x60 388 #define IDDR_2L 0x68 /* unimplemented */ 389 #define IDDR_3H 0x70 /* unimplemented */ 390 #define IDDR_3L 0x78 /* unimplemented */ 391 392 /* 393 * Error registers 394 */ 395 396 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 397 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 398 #define AFAR 0x00 399 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 400 #define AFSR 0x00 401 402 #define ASI_P_EER 0x4b /* Error enable register */ 403 #define P_EER 0x00 404 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 405 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 406 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 407 408 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 409 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 410 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 411 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 412 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 413 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 414 415 416 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 417 418 /* 419 * GCC __asm constructs for doing assembly stuff. 420 */ 421 422 /* 423 * ``Routines'' to load and store from/to alternate address space. 424 * The location can be a variable, the asi value (address space indicator) 425 * must be a constant. 426 * 427 * N.B.: You can put as many special functions here as you like, since 428 * they cost no kernel space or time if they are not used. 429 * 430 * These were static inline functions, but gcc screws up the constraints 431 * on the address space identifiers (the "n"umeric value part) because 432 * it inlines too late, so we have to use the funny valued-macro syntax. 433 */ 434 435 /* DCACHE_BUG forces a flush of the D$ line on every ASI load */ 436 #define DCACHE_BUG 437 438 #ifdef __arch64__ 439 /* load byte from alternate address space */ 440 #ifdef DCACHE_BUG 441 #define lduba(loc, asi) ({ \ 442 register unsigned int _lduba_v; \ 443 if (PHYS_ASI(asi)) { \ 444 __asm __volatile("wr %2,%%g0,%%asi; " \ 445 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 446 " lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \ 447 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 448 } else { \ 449 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 450 "=r" (_lduba_v) : \ 451 "r" ((unsigned long)(loc)), "r" (asi)); \ 452 } \ 453 _lduba_v; \ 454 }) 455 #else 456 #define lduba(loc, asi) ({ \ 457 register unsigned int _lduba_v; \ 458 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 459 "=r" (_lduba_v) : \ 460 "r" ((unsigned long)(loc)), "r" (asi)); \ 461 _lduba_v; \ 462 }) 463 #endif 464 #else 465 /* load byte from alternate address space */ 466 #ifdef DCACHE_BUG 467 #define lduba(loc, asi) ({ \ 468 register unsigned int _lduba_v, _loc_hi, _pstate; \ 469 _loc_hi = (((u_int64_t)loc)>>32); \ 470 if (PHYS_ASI(asi)) { \ 471 __asm __volatile("wr %4,%%g0,%%asi; " \ 472 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; " \ 473 " sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; " \ 474 " membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 475 "=&r" (_lduba_v), "=&r" (_pstate) : \ 476 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 477 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 478 } else { \ 479 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 480 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 481 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 482 } \ 483 _lduba_v; \ 484 }) 485 #else 486 #define lduba(loc, asi) ({ \ 487 register unsigned int _lduba_v, _loc_hi, _pstate; \ 488 _loc_hi = (((u_int64_t)loc)>>32); \ 489 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; sllx %3,32,%0; " \ 490 " wrpr %1,8,%%pstate; or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 491 "=&r" (_lduba_v), "=&r" (_pstate) : \ 492 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 493 _lduba_v; \ 494 }) 495 #endif 496 #endif 497 498 #ifdef __arch64__ 499 /* load half-word from alternate address space */ 500 #ifdef DCACHE_BUG 501 #define lduha(loc, asi) ({ \ 502 register unsigned int _lduha_v; \ 503 if (PHYS_ASI(asi)) { \ 504 __asm __volatile("wr %2,%%g0,%%asi; " \ 505 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 506 " lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \ 507 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 508 } else { \ 509 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 510 "r" ((unsigned long)(loc)), "r" (asi)); \ 511 } \ 512 _lduha_v; \ 513 }) 514 #else 515 #define lduha(loc, asi) ({ \ 516 register unsigned int _lduha_v; \ 517 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 518 "r" ((unsigned long)(loc)), "r" (asi)); \ 519 _lduha_v; \ 520 }) 521 #endif 522 #else 523 /* load half-word from alternate address space */ 524 #ifdef DCACHE_BUG 525 #define lduha(loc, asi) ({ \ 526 register unsigned int _lduha_v, _loc_hi, _pstate; \ 527 _loc_hi = (((u_int64_t)loc)>>32); \ 528 if (PHYS_ASI(asi)) { \ 529 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \ 530 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; " \ 531 " or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 532 "=&r" (_lduha_v), "=&r" (_pstate) : \ 533 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 534 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 535 } else { \ 536 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 537 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 538 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 539 } \ 540 _lduha_v; \ 541 }) 542 #else 543 #define lduha(loc, asi) ({ \ 544 register unsigned int _lduha_v, _loc_hi, _pstate; \ 545 _loc_hi = (((u_int64_t)loc)>>32); \ 546 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1; " \ 547 " or %0,%2,%0; wrpr %1,8,%%pstate; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 548 "=&r" (_lduha_v), "=&r" (_pstate) : \ 549 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 550 _lduha_v; \ 551 }) 552 #endif 553 #endif 554 555 #ifdef __arch64__ 556 /* load unsigned int from alternate address space */ 557 #ifdef DCACHE_BUG 558 #define lda(loc, asi) ({ \ 559 register unsigned int _lda_v; \ 560 if (PHYS_ASI(asi)) { \ 561 __asm __volatile("wr %2,%%g0,%%asi; " \ 562 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 563 " lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 564 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 565 } else { \ 566 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 567 "r" ((unsigned long)(loc)), "r" (asi)); \ 568 } \ 569 _lda_v; \ 570 }) 571 572 /* load signed int from alternate address space */ 573 #define ldswa(loc, asi) ({ \ 574 register int _lda_v; \ 575 if (PHYS_ASI(asi)) { \ 576 __asm __volatile("wr %2,%%g0,%%asi; " \ 577 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 578 " ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 579 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 580 } else { \ 581 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 582 "r" ((unsigned long)(loc)), "r" (asi)); \ 583 } \ 584 _lda_v; \ 585 }) 586 #else 587 #define lda(loc, asi) ({ \ 588 register unsigned int _lda_v; \ 589 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 590 "r" ((unsigned long)(loc)), "r" (asi)); \ 591 _lda_v; \ 592 }) 593 594 #define ldswa(loc, asi) ({ \ 595 register int _lda_v; \ 596 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 597 "r" ((unsigned long)(loc)), "r" (asi)); \ 598 _lda_v; \ 599 }) 600 #endif 601 #else /* __arch64__ */ 602 /* load unsigned int from alternate address space */ 603 #ifdef DCACHE_BUG 604 #define lda(loc, asi) ({ \ 605 register unsigned int _lda_v, _loc_hi, _pstate; \ 606 _loc_hi = (((u_int64_t)loc)>>32); \ 607 if (PHYS_ASI(asi)) { \ 608 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 609 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; " \ 610 " sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; " \ 611 " wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \ 612 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 613 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 614 } else { \ 615 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 616 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 617 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 618 } \ 619 _lda_v; \ 620 }) 621 622 /* load signed int from alternate address space */ 623 #define ldswa(loc, asi) ({ \ 624 register int _lda_v, _loc_hi, _pstate; \ 625 _loc_hi = (((u_int64_t)loc)>>32); \ 626 if (PHYS_ASI(asi)) { \ 627 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 628 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;" \ 629 " or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 630 "=&r" (_lda_v), "=&r" (_pstate) : \ 631 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 632 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 633 } else { \ 634 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 635 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ 636 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 637 } \ 638 _lda_v; \ 639 }) 640 #else 641 #define lda(loc, asi) ({ \ 642 register unsigned int _lda_v, _loc_hi, _pstate; \ 643 _loc_hi = (((u_int64_t)loc)>>32); \ 644 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 645 " wrpr %1,8,%%pstate; or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 646 "=&r" (_lda_v), "=&r" (_pstate) : \ 647 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 648 _lda_v; \ 649 }) 650 651 #define ldswa(loc, asi) ({ \ 652 register int _lda_v, _loc_hi, _pstate;; \ 653 _loc_hi = (((u_int64_t)loc)>>32); \ 654 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 655 " wrpr %1,8,%%pstate; or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%pstate" : \ 656 "=&r" (_lda_v), "=&r" (_pstate) : \ 657 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 658 _lda_v; \ 659 }) 660 #endif 661 #endif /* __arch64__ */ 662 663 #ifdef DCACHE_BUG 664 665 #ifdef __arch64__ 666 /* load 64-bit int from alternate address space */ 667 #define ldda(loc, asi) ({ \ 668 register long long _lda_v; \ 669 if (PHYS_ASI(asi)) { \ 670 __asm __volatile("wr %2,%%g0,%%asi; " \ 671 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 672 " ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 673 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 674 } else { \ 675 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 676 "r" ((unsigned long)(loc)), "r" (asi)); \ 677 } \ 678 _lda_v; \ 679 }) 680 #else 681 /* load 64-bit int from alternate address space */ 682 #define ldda(loc, asi) ({ \ 683 register long long _lda_v, _loc_hi, _pstate; \ 684 _loc_hi = (((u_int64_t)loc)>>32); \ 685 if (PHYS_ASI(asi)) { \ 686 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \ 687 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;" \ 688 " sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" :\ 689 "=&r" (_lda_v), "=&r" (_pstate) : \ 690 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 691 } else { \ 692 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 693 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 694 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 695 } \ 696 _lda_v; \ 697 }) 698 #endif 699 700 #ifdef __arch64__ 701 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 702 #define ldxa(loc, asi) ({ \ 703 register unsigned long _lda_v; \ 704 if (PHYS_ASI(asi)) { \ 705 __asm __volatile("wr %2,%%g0,%%asi; "\ 706 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 707 " ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 708 "r" ((unsigned long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 709 } else { \ 710 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 711 "r" ((unsigned long)(loc)), "r" (asi)); \ 712 } \ 713 _lda_v; \ 714 }) 715 #else 716 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 717 #define ldxa(loc, asi) ({ \ 718 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \ 719 _loc_hi = (((u_int64_t)loc)>>32); \ 720 if (PHYS_ASI(asi)) { \ 721 __asm __volatile("wr %4,%%g0,%%asi; " \ 722 " andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; " \ 723 " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; " \ 724 " wrpr %1,0,%%pstate; srlx %0,32,%1; srl %0,0,%0" : \ 725 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 726 "r" ((unsigned long)(loc)), "r" (_loc_hi), \ 727 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 728 } else { \ 729 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 730 " or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 731 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 732 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 733 } \ 734 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 735 }) 736 #endif 737 738 #else 739 740 #ifdef __arch64__ 741 /* load 64-bit int from alternate address space */ 742 #define ldda(loc, asi) ({ \ 743 register long long _lda_v; \ 744 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 745 "r" ((unsigned long)(loc)), "r" (asi)); \ 746 _lda_v; \ 747 }) 748 #else 749 #define ldda(loc, asi) ({ \ 750 register long long _lda_v, _loc_hi, _pstate; \ 751 _loc_hi = (((u_int64_t)loc)>>32); \ 752 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; rdpr %%pstate,%1;" \ 753 " or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \ 754 "=&r" (_lda_v), "=&r" (_pstate) : \ 755 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 756 _lda_v; \ 757 }) 758 #endif 759 760 #ifdef __arch64__ 761 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 762 #define ldxa(loc, asi) ({ \ 763 register long _lda_v; \ 764 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 765 "r" ((unsigned long)(loc)), "r" (asi)); \ 766 _lda_v; \ 767 }) 768 #else 769 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 770 #define ldxa(loc, asi) ({ \ 771 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \ 772 _loc_hi = (((u_int64_t)loc)>>32); \ 773 if (PHYS_ASI(asi)) { \ 774 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1;" \ 775 " or %0,%1,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate;" \ 776 " srlx %0,32,%1; srl %0,0,%0;" : \ 777 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 778 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 779 } else { \ 780 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \ 781 " or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 782 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 783 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 784 } \ 785 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 786 }) 787 #endif 788 #endif 789 790 791 /* store byte to alternate address space */ 792 #ifdef __arch64__ 793 #define stba(loc, asi, value) ({ \ 794 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \ 795 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 796 }) 797 #else 798 #define stba(loc, asi, value) ({ \ 799 register int _loc_hi, _pstate; \ 800 _loc_hi = (((u_int64_t)loc)>>32); \ 801 if (PHYS_ASI(asi)) { \ 802 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 803 " or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 804 "=&r" (_loc_hi), "=&r" (_pstate) : \ 805 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 806 "r" (_loc_hi), "r" (asi)); \ 807 } else { \ 808 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 809 " or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 810 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 811 "r" (_loc_hi), "r" (asi)); \ 812 } \ 813 }) 814 #endif 815 816 /* store half-word to alternate address space */ 817 #ifdef __arch64__ 818 #define stha(loc, asi, value) ({ \ 819 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \ 820 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 821 }) 822 #else 823 #define stha(loc, asi, value) ({ \ 824 register int _loc_hi, _pstate; \ 825 _loc_hi = (((u_int64_t)loc)>>32); \ 826 if (PHYS_ASI(asi)) { \ 827 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 828 " or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 829 "=&r" (_loc_hi), "=&r" (_pstate) : \ 830 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 831 "r" (_loc_hi), "r" (asi)); \ 832 } else { \ 833 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 834 " or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 835 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 836 "r" (_loc_hi), "r" (asi)); \ 837 } \ 838 }) 839 #endif 840 841 /* store int to alternate address space */ 842 #ifdef __arch64__ 843 #define sta(loc, asi, value) ({ \ 844 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \ 845 "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 846 }) 847 #else 848 #define sta(loc, asi, value) ({ \ 849 register int _loc_hi, _pstate; \ 850 _loc_hi = (((u_int64_t)loc)>>32); \ 851 if (PHYS_ASI(asi)) { \ 852 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \ 853 " or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 854 "=&r" (_loc_hi), "=&r" (_pstate) : \ 855 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 856 "r" (_loc_hi), "r" (asi)); \ 857 } else { \ 858 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 859 " or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 860 "r" ((int)(value)), "r" ((unsigned long)(loc)), \ 861 "r" (_loc_hi), "r" (asi)); \ 862 } \ 863 }) 864 #endif 865 866 /* store 64-bit int to alternate address space */ 867 #ifdef __arch64__ 868 #define stda(loc, asi, value) ({ \ 869 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \ 870 "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 871 }) 872 #else 873 #define stda(loc, asi, value) ({ \ 874 register int _loc_hi, _pstate; \ 875 _loc_hi = (((u_int64_t)loc)>>32); \ 876 if (PHYS_ASI(asi)) { \ 877 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \ 878 " or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate" : \ 879 "=&r" (_loc_hi), "=&r" (_pstate) : \ 880 "r" ((long long)(value)), "r" ((unsigned long)(loc)), \ 881 "r" (_loc_hi), "r" (asi)); \ 882 } else { \ 883 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 884 " or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 885 "r" ((long long)(value)), "r" ((unsigned long)(loc)), \ 886 "r" (_loc_hi), "r" (asi)); \ 887 } \ 888 }) 889 #endif 890 891 #ifdef __arch64__ 892 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 893 #define stxa(loc, asi, value) ({ \ 894 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : \ 895 "r" ((unsigned long)(value)), "r" ((unsigned long)(loc)), "r" (asi)); \ 896 }) 897 #else 898 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 899 #define stxa(loc, asi, value) ({ \ 900 int _stxa_lo, _stxa_hi, _loc_hi; \ 901 _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \ 902 _loc_hi = (((u_int64_t)(u_long)loc)>>32); \ 903 if (PHYS_ASI(asi)) { \ 904 __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \ 905 " or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \ 906 " stxa %1,[%0]%%asi; wrpr %3,0,%%pstate" : \ 907 "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \ 908 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 909 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 910 } else { \ 911 __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \ 912 " or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \ 913 "=&r" (_loc_hi), "=&r" (_stxa_hi) : \ 914 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 915 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \ 916 } \ 917 }) 918 #endif 919 920 /* flush address from data cache */ 921 #define flush(loc) ({ \ 922 __asm __volatile("flush %0" : : \ 923 "r" ((unsigned long)(loc))); \ 924 }) 925 926 /* Flush a D$ line */ 927 #if 0 928 #define flushline(loc) ({ \ 929 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 930 membar_sync(); \ 931 }) 932 #else 933 #define flushline(loc) 934 #endif 935 936 /* The following two enable or disable the dcache in the LSU control register */ 937 #define dcenable() ({ \ 938 int res; \ 939 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 940 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 941 }) 942 #define dcdisable() ({ \ 943 int res; \ 944 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 945 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 946 }) 947 948 /* 949 * SPARC V9 memory barrier instructions. 950 */ 951 /* Make all stores complete before next store */ 952 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 953 /* Make all loads complete before next store */ 954 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 955 /* Make all stores complete before next load */ 956 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 957 /* Make all loads complete before next load */ 958 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 959 /* Complete all outstanding memory operations and exceptions */ 960 #define membar_sync() __asm __volatile("membar #Sync" : :) 961 /* Complete all outstanding memory operations */ 962 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 963 /* Complete all outstanding stores before any new loads */ 964 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 965 966 #ifdef __arch64__ 967 /* read 64-bit %tick register */ 968 #define tick() ({ \ 969 register u_long _tick_tmp; \ 970 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 971 _tick_tmp; \ 972 }) 973 #else 974 /* read 64-bit %tick register on 32-bit system */ 975 #define tick() ({ \ 976 register int _tick_hi = 0, _tick_lo = 0; \ 977 __asm __volatile("rdpr %%tick, %1; srlx %0,32,%2; srl %0,0,%0 " \ 978 : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ 979 (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ 980 }) 981 #endif 982 983 #ifndef _LOCORE 984 extern void next_tick __P((long)); 985 #endif 986
Indexes created Mon Sep 29 21:09:56 GMT 2025