ctlreg.h revision 1.31
1 /* $NetBSD: ctlreg.h,v 1.31 2004/03/14 18:18:54 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1996-2002 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 /* 27 * Sun 4u control registers. (includes address space definitions 28 * and some registers in control space). 29 */ 30 31 /* 32 * The Alternate address spaces. 33 * 34 * 0x00-0x7f are privileged 35 * 0x80-0xff can be used by users 36 */ 37 38 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 39 40 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 41 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 42 43 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 44 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 45 46 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 47 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 48 49 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 50 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 51 52 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 53 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 54 55 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 56 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 57 58 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 59 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 60 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 61 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 62 63 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 64 65 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 66 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 67 68 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 69 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 70 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 71 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 72 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 73 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 74 75 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 76 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 77 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 78 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 79 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 80 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 81 82 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 83 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 84 85 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 86 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 87 88 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 89 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 90 91 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 92 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 93 94 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 95 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 96 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 97 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 98 99 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 100 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 101 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 102 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 103 104 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 105 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 106 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 107 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 108 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 109 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 110 111 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 112 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 113 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 114 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 115 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 116 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 117 118 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 119 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 120 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 121 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 122 123 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 124 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 125 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 126 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 127 128 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 129 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 130 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 131 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 132 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 133 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 134 135 136 /* 137 * These are the shorter names used by Solaris 138 */ 139 140 #define ASI_N ASI_NUCLEUS 141 #define ASI_NL ASI_NUCLEUS_LITTLE 142 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 143 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 144 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 145 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 146 #define ASI_P ASI_PRIMARY 147 #define ASI_S ASI_SECONDARY 148 #define ASI_PNF ASI_PRIMARY_NOFAULT 149 #define ASI_SNF ASI_SECONDARY_NOFAULT 150 #define ASI_PL ASI_PRIMARY_LITTLE 151 #define ASI_SL ASI_SECONDARY_LITTLE 152 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 153 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 154 #define ASI_FL8_P ASI_FL8_PRIMARY 155 #define ASI_FL8_S ASI_FL8_SECONDARY 156 #define ASI_FL16_P ASI_FL16_PRIMARY 157 #define ASI_FL16_S ASI_FL16_SECONDARY 158 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 159 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 160 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 161 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 162 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 163 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 164 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 165 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 166 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 167 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 168 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 169 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 170 #define ASI_BLK_P ASI_BLOCK_PRIMARY 171 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 172 #define ASI_BLK_S ASI_BLOCK_SECONDARY 173 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 174 175 /* Alternative spellings */ 176 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 177 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 178 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 179 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 180 181 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 182 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 183 184 /* 185 * The following are 4u control registers 186 */ 187 188 189 /* Get the CPU's UPAID */ 190 #define UPA_CR_MID(x) (((x)>>17)&0x1f) 191 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 192 193 /* 194 * [4u] MMU and Cache Control Register (MCCR) 195 * use ASI = 0x45 196 */ 197 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 198 #define MCCR 0x00 199 200 /* MCCR Bits and their meanings */ 201 #define MCCR_DMMU_EN 0x08 202 #define MCCR_IMMU_EN 0x04 203 #define MCCR_DCACHE_EN 0x02 204 #define MCCR_ICACHE_EN 0x01 205 206 207 /* 208 * MMU control registers 209 */ 210 211 /* Choose an MMU */ 212 #define ASI_DMMU 0x58 213 #define ASI_IMMU 0x50 214 215 /* Other assorted MMU ASIs */ 216 #define ASI_IMMU_8KPTR 0x51 217 #define ASI_IMMU_64KPTR 0x52 218 #define ASI_IMMU_DATA_IN 0x54 219 #define ASI_IMMU_TLB_DATA 0x55 220 #define ASI_IMMU_TLB_TAG 0x56 221 #define ASI_DMMU_8KPTR 0x59 222 #define ASI_DMMU_64KPTR 0x5a 223 #define ASI_DMMU_DATA_IN 0x5c 224 #define ASI_DMMU_TLB_DATA 0x5d 225 #define ASI_DMMU_TLB_TAG 0x5e 226 227 /* 228 * The following are the control registers 229 * They work on both MMUs unless noted. 230 * 231 * Register contents are defined later on individual registers. 232 */ 233 #define TSB_TAG_TARGET 0x0 234 #define TLB_DATA_IN 0x0 235 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 236 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 237 #define SFSR 0x18 238 #define SFAR 0x20 /* fault address -- DMMU only */ 239 #define TSB 0x28 240 #define TLB_TAG_ACCESS 0x30 241 #define VIRTUAL_WATCHPOINT 0x38 242 #define PHYSICAL_WATCHPOINT 0x40 243 244 /* Tag Target bits */ 245 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 246 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 247 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 248 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 249 250 /* SFSR bits for both D_SFSR and I_SFSR */ 251 #define SFSR_ASI(x) ((x)>>16) 252 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 253 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 254 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 255 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 256 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 257 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 258 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 259 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 260 #define SFSR_CTXT(x) (((x)>>4)&0x3) 261 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 262 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 263 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 264 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 265 #define SFSR_W 0x00004 /* DMMU: attempted write */ 266 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 267 #define SFSR_FV 0x00001 /* Fault is valid */ 268 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 269 270 #if 0 271 /* Old bits */ 272 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 273 #else 274 /* New bits */ 275 #define SFSR_BITS "\177\20" \ 276 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 277 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 278 #endif 279 280 /* ASFR bits */ 281 #define ASFR_ME 0x100000000LL 282 #define ASFR_PRIV 0x080000000LL 283 #define ASFR_ISAP 0x040000000LL 284 #define ASFR_ETP 0x020000000LL 285 #define ASFR_IVUE 0x010000000LL 286 #define ASFR_TO 0x008000000LL 287 #define ASFR_BERR 0x004000000LL 288 #define ASFR_LDP 0x002000000LL 289 #define ASFR_CP 0x001000000LL 290 #define ASFR_WP 0x000800000LL 291 #define ASFR_EDP 0x000400000LL 292 #define ASFR_UE 0x000200000LL 293 #define ASFR_CE 0x000100000LL 294 #define ASFR_ETS 0x0000f0000LL 295 #define ASFT_P_SYND 0x00000ffffLL 296 297 #define AFSR_BITS "\177\20" \ 298 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 299 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 300 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 301 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 302 303 /* 304 * Here's the spitfire TSB control register bits. 305 * 306 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 307 */ 308 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 309 #define TSB_SIZE_1K 0x01 310 #define TSB_SIZE_2K 0x02 311 #define TSB_SIZE_4K 0x03 312 #define TSB_SIZE_8K 0x04 313 #define TSB_SIZE_16K 0x05 314 #define TSB_SIZE_32K 0x06 315 #define TSB_SIZE_64K 0x07 316 #define TSB_SPLIT 0x1000 317 #define TSB_BASE 0xffffffffffffe000 318 319 /* TLB Tag Access bits */ 320 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 321 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 322 323 /* 324 * TLB demap registers. TTEs are defined in v9pte.h 325 * 326 * Use the address space to select between IMMU and DMMU. 327 * The address of the register selects which context register 328 * to read the ASI from. 329 * 330 * The data stored in the register is interpreted as the VA to 331 * use. The DEMAP_CTX_<> registers ignore the address and demap the 332 * entire ASI. 333 * 334 */ 335 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 336 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 337 338 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 339 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 340 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 341 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 342 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 343 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 344 345 /* 346 * Interrupt registers. This really gets hairy. 347 */ 348 349 /* IRSR -- Interrupt Receive Status Ragister */ 350 #define ASI_IRSR 0x49 351 #define IRSR 0x00 352 #define IRSR_BUSY 0x020 353 #define IRSR_MID(x) (x&0x1f) 354 355 /* IRDR -- Interrupt Receive Data Registers */ 356 #define ASI_IRDR 0x7f 357 #define IRDR_0H 0x40 358 #define IRDR_0L 0x48 /* unimplemented */ 359 #define IRDR_1H 0x50 360 #define IRDR_1L 0x58 /* unimplemented */ 361 #define IRDR_2H 0x60 362 #define IRDR_2L 0x68 /* unimplemented */ 363 #define IRDR_3H 0x70 /* unimplemented */ 364 #define IRDR_3L 0x78 /* unimplemented */ 365 366 /* SOFTINT ASRs */ 367 #define SET_SOFTINT %asr20 /* Sets these bits */ 368 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 369 #define SOFTINT %asr22 /* Reads the register */ 370 #define TICK_CMPR %asr23 371 372 #define TICK_INT 0x01 /* level-14 clock tick */ 373 #define SOFTINT1 (0x1<<1) 374 #define SOFTINT2 (0x1<<2) 375 #define SOFTINT3 (0x1<<3) 376 #define SOFTINT4 (0x1<<4) 377 #define SOFTINT5 (0x1<<5) 378 #define SOFTINT6 (0x1<<6) 379 #define SOFTINT7 (0x1<<7) 380 #define SOFTINT8 (0x1<<8) 381 #define SOFTINT9 (0x1<<9) 382 #define SOFTINT10 (0x1<<10) 383 #define SOFTINT11 (0x1<<11) 384 #define SOFTINT12 (0x1<<12) 385 #define SOFTINT13 (0x1<<13) 386 #define SOFTINT14 (0x1<<14) 387 #define SOFTINT15 (0x1<<15) 388 389 /* Interrupt Dispatch -- usually reserved for cross-calls */ 390 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 391 #define IDSR 0x00 392 #define IDSR_NACK 0x02 393 #define IDSR_BUSY 0x01 394 395 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 396 397 /* Interrupt delivery initiation */ 398 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70) 399 400 #define IDDR_0H 0x40 /* Store data to send in these regs */ 401 #define IDDR_0L 0x48 /* unimplemented */ 402 #define IDDR_1H 0x50 403 #define IDDR_1L 0x58 /* unimplemented */ 404 #define IDDR_2H 0x60 405 #define IDDR_2L 0x68 /* unimplemented */ 406 #define IDDR_3H 0x70 /* unimplemented */ 407 #define IDDR_3L 0x78 /* unimplemented */ 408 409 /* 410 * Error registers 411 */ 412 413 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 414 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 415 #define AFAR 0x00 416 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 417 #define AFSR 0x00 418 419 #define ASI_P_EER 0x4b /* Error enable register */ 420 #define P_EER 0x00 421 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 422 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 423 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 424 425 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 426 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 427 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 428 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 429 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 430 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 431 432 433 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 434 435 #ifndef _LOCORE 436 /* 437 * GCC __asm constructs for doing assembly stuff. 438 */ 439 440 /* 441 * ``Routines'' to load and store from/to alternate address space. 442 * The location can be a variable, the asi value (address space indicator) 443 * must be a constant. 444 * 445 * N.B.: You can put as many special functions here as you like, since 446 * they cost no kernel space or time if they are not used. 447 * 448 * These were static inline functions, but gcc screws up the constraints 449 * on the address space identifiers (the "n"umeric value part) because 450 * it inlines too late, so we have to use the funny valued-macro syntax. 451 */ 452 453 /* 454 * Apparently the definition of bypass ASIs is that they all use the 455 * D$ so we need to flush the D$ to make sure we don't get data pollution. 456 */ 457 458 static __inline__ u_char lduba __P((paddr_t loc, int asi)); 459 static __inline__ u_short lduha __P((paddr_t loc, int asi)); 460 static __inline__ u_int lda __P((paddr_t loc, int asi)); 461 static __inline__ int ldswa __P((paddr_t loc, int asi)); 462 static __inline__ u_int64_t ldxa __P((paddr_t loc, int asi)); 463 static __inline__ u_int64_t ldda __P((paddr_t loc, int asi)); 464 465 static __inline__ void stba __P((paddr_t loc, int asi, u_char value)); 466 static __inline__ void stha __P((paddr_t loc, int asi, u_short value)); 467 static __inline__ void sta __P((paddr_t loc, int asi, u_int value)); 468 static __inline__ void stxa __P((paddr_t loc, int asi, u_int64_t value)); 469 static __inline__ void stda __P((paddr_t loc, int asi, u_int64_t value)); 470 471 #if 0 472 static __inline__ unsigned int casa __P((paddr_t loc, int asi, 473 unsigned int value, unsigned int oldvalue)); 474 static __inline__ u_int64_t casxa __P((paddr_t loc, int asi, 475 u_int64_t value, u_int64_t oldvalue)); 476 #endif 477 478 #ifdef __arch64__ 479 static __inline__ u_char 480 lduba(paddr_t loc, int asi) 481 { 482 register unsigned int _lduba_v; 483 484 __asm __volatile("wr %2,%%g0,%%asi; " 485 " lduba [%1]%%asi,%0; wr %%g0, 0x82, %%asi" : 486 "=r" (_lduba_v) : 487 "r" ((unsigned long)(loc)), "r" (asi)); 488 return (_lduba_v); 489 } 490 #else 491 static __inline__ u_char 492 lduba(paddr_t loc, int asi) 493 { 494 register unsigned int _lduba_v, _loc_hi, _pstate; 495 496 _loc_hi = (((u_int64_t)loc)>>32); 497 if (PHYS_ASI(asi)) { 498 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 499 " rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; " 500 " membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; " 501 " membar #Sync; wr %%g0, 0x82, %%asi" : 502 "=&r" (_lduba_v), "=&r" (_pstate) : 503 "r" ((unsigned long)(loc)), "r" (_loc_hi), 504 "r" (asi)); 505 } else { 506 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 507 " or %0,%1,%0; lduba [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduba_v) : 508 "r" ((unsigned long)(loc)), 509 "r" (_loc_hi), "r" (asi)); 510 } 511 return (_lduba_v); 512 } 513 #endif 514 515 #ifdef __arch64__ 516 /* load half-word from alternate address space */ 517 static __inline__ u_short 518 lduha(paddr_t loc, int asi) 519 { 520 register unsigned int _lduha_v; 521 522 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0; " 523 " wr %%g0, 0x82, %%asi" : 524 "=r" (_lduha_v) : 525 "r" ((unsigned long)(loc)), "r" (asi)); 526 return (_lduha_v); 527 } 528 #else 529 /* load half-word from alternate address space */ 530 static __inline__ u_short 531 lduha(paddr_t loc, int asi) { 532 register unsigned int _lduha_v, _loc_hi, _pstate; 533 534 _loc_hi = (((u_int64_t)loc)>>32); 535 536 if (PHYS_ASI(asi)) { 537 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 538 " rdpr %%pstate,%1; wrpr %1,8,%%pstate; " 539 " or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; " 540 " membar #Sync; wr %%g0, 0x82, %%asi" : 541 "=&r" (_lduha_v), "=&r" (_pstate) : 542 "r" ((unsigned long)(loc)), "r" (_loc_hi), 543 "r" (asi)); 544 } else { 545 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 546 " or %0,%1,%0; lduha [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v) : 547 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 548 } 549 return (_lduha_v); 550 } 551 #endif 552 553 554 #ifdef __arch64__ 555 /* load unsigned int from alternate address space */ 556 static __inline__ u_int 557 lda(paddr_t loc, int asi) 558 { 559 register unsigned int _lda_v; 560 561 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : 562 "=r" (_lda_v) : 563 "r" ((unsigned long)(loc)), "r" (asi)); 564 return (_lda_v); 565 } 566 567 /* load signed int from alternate address space */ 568 static __inline__ int 569 ldswa(paddr_t loc, int asi) 570 { 571 register int _lda_v; 572 573 __asm __volatile("wr %2,%%g0,%%asi; " 574 " ldswa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" : 575 "=r" (_lda_v) : 576 "r" ((unsigned long)(loc)), "r" (asi)); 577 return (_lda_v); 578 } 579 #else /* __arch64__ */ 580 /* load unsigned int from alternate address space */ 581 static __inline__ u_int 582 lda(paddr_t loc, int asi) 583 { 584 register unsigned int _lda_v, _loc_hi, _pstate; 585 586 _loc_hi = (((u_int64_t)loc)>>32); 587 if (PHYS_ASI(asi)) { 588 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" 589 " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; " 590 " lda [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; " 591 " wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (_pstate) : 592 "r" ((unsigned long)(loc)), "r" (_loc_hi), 593 "r" (asi)); 594 } else { 595 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 596 " or %0,%1,%0; lda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) : 597 "r" ((unsigned long)(loc)), 598 "r" (_loc_hi), "r" (asi)); 599 } 600 return (_lda_v); 601 } 602 603 /* load signed int from alternate address space */ 604 static __inline__ int 605 ldswa(paddr_t loc, int asi) 606 { 607 register int _lda_v, _loc_hi, _pstate; 608 609 _loc_hi = (((u_int64_t)loc)>>32); 610 if (PHYS_ASI(asi)) { 611 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" 612 " wrpr %1,8,%%pstate; sllx %3,32,%0;" 613 " or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; " 614 " membar #Sync; wr %%g0, 0x82, %%asi" : 615 "=&r" (_lda_v), "=&r" (_pstate) : 616 "r" ((unsigned long)(loc)), "r" (_loc_hi), 617 "r" (asi)); 618 } else { 619 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 620 " or %0,%1,%0; ldswa [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) : 621 "r" ((unsigned long)(loc)), 622 "r" (_loc_hi), "r" (asi)); 623 } 624 return (_lda_v); 625 } 626 #endif /* __arch64__ */ 627 628 #ifdef __arch64__ 629 /* load 64-bit int from alternate address space -- these should never be used */ 630 static __inline__ u_int64_t 631 ldda(paddr_t loc, int asi) 632 { 633 register long long _lda_v; 634 635 __asm __volatile("wr %2,%%g0,%%asi; " 636 " ldda [%1]%%asi,%0; wr %%g0, 0x82, %%asi" : 637 "=r" (_lda_v) : 638 "r" ((unsigned long)(loc)), "r" (asi)); 639 return (_lda_v); 640 } 641 #else 642 /* load 64-bit int from alternate address space */ 643 static __inline__ u_int64_t 644 ldda(paddr_t loc, int asi) 645 { 646 register long long _lda_v, _loc_hi, _pstate; 647 648 _loc_hi = (((u_int64_t)loc)>>32); 649 if (PHYS_ASI(asi)) { 650 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" 651 " wrpr %1,8,%%pstate; sllx %3,32,%0; or %0,%2,%0; membar #Sync;" 652 " ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" : 653 "=&r" (_lda_v), "=&r" (_pstate) : 654 "r" ((unsigned long)(loc)), "r" (_loc_hi), 655 "r" (asi)); 656 } else { 657 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " 658 " or %0,%1,%0; ldda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) : 659 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 660 } 661 return (_lda_v); 662 } 663 #endif 664 665 666 #ifdef __arch64__ 667 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 668 static __inline__ u_int64_t 669 ldxa(paddr_t loc, int asi) 670 { 671 register unsigned long _lda_v; 672 673 __asm __volatile("wr %2,%%g0,%%asi; " 674 " ldxa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" : 675 "=r" (_lda_v) : 676 "r" ((unsigned long)(loc)), "r" (asi)); 677 return (_lda_v); 678 } 679 #else 680 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 681 static __inline__ u_int64_t 682 ldxa(paddr_t loc, int asi) 683 { 684 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; 685 686 _loc_hi = (((u_int64_t)loc)>>32); 687 if (PHYS_ASI(asi)) { 688 __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " 689 " sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; " 690 " ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; " 691 " srlx %0,32,%1; srl %0,0,%0; wr %%g0, 0x82, %%asi" : 692 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : 693 "r" ((unsigned long)(loc)), "r" (_loc_hi), 694 "r" (asi)); 695 } else { 696 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 697 " or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; " 698 " srl %0,0,%0;; wr %%g0, 0x82, %%asi" : 699 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : 700 "r" ((unsigned long)(loc)), "r" (_loc_hi), 701 "r" (asi)); 702 } 703 return ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); 704 } 705 #endif 706 707 /* store byte to alternate address space */ 708 #ifdef __arch64__ 709 static __inline__ void 710 stba(paddr_t loc, int asi, u_char value) 711 { 712 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; " 713 " wr %%g0, 0x82, %%asi" : : 714 "r" ((int)(value)), "r" ((unsigned long)(loc)), 715 "r" (asi)); 716 } 717 #else 718 static __inline__ void 719 stba(paddr_t loc, int asi, u_char value) 720 { 721 register int _loc_hi, _pstate; 722 723 _loc_hi = (((u_int64_t)loc)>>32); 724 if (PHYS_ASI(asi)) { 725 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; " 726 " rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; " 727 " wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" : 728 "=&r" (_loc_hi), "=&r" (_pstate) : 729 "r" ((int)(value)), "r" ((unsigned long)(loc)), 730 "r" (_loc_hi), "r" (asi)); 731 } else { 732 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 733 " or %2,%0,%0; stba %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) : 734 "r" ((int)(value)), "r" ((unsigned long)(loc)), 735 "r" (_loc_hi), "r" (asi)); 736 } 737 } 738 #endif 739 740 /* store half-word to alternate address space */ 741 #ifdef __arch64__ 742 static __inline__ void 743 stha(paddr_t loc, int asi, u_short value) 744 { 745 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi; " 746 " wr %%g0, 0x82, %%asi" : : 747 "r" ((int)(value)), "r" ((unsigned long)(loc)), 748 "r" (asi) : "memory"); 749 } 750 #else 751 static __inline__ void 752 stha(paddr_t loc, int asi, u_short value) 753 { 754 register int _loc_hi, _pstate; 755 756 _loc_hi = (((u_int64_t)loc)>>32); 757 if (PHYS_ASI(asi)) { 758 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; " 759 " rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; " 760 " wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" : 761 "=&r" (_loc_hi), "=&r" (_pstate) : 762 "r" ((int)(value)), "r" ((unsigned long)(loc)), 763 "r" (_loc_hi), "r" (asi) : "memory"); 764 } else { 765 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 766 " or %2,%0,%0; stha %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) : 767 "r" ((int)(value)), "r" ((unsigned long)(loc)), 768 "r" (_loc_hi), "r" (asi) : "memory"); 769 } 770 } 771 #endif 772 773 774 /* store int to alternate address space */ 775 #ifdef __arch64__ 776 static __inline__ void 777 sta(paddr_t loc, int asi, u_int value) 778 { 779 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi; " 780 " wr %%g0, 0x82, %%asi" : : 781 "r" ((int)(value)), "r" ((unsigned long)(loc)), 782 "r" (asi) : "memory"); 783 } 784 #else 785 static __inline__ void 786 sta(paddr_t loc, int asi, u_int value) 787 { 788 register int _loc_hi, _pstate; 789 790 _loc_hi = (((u_int64_t)loc)>>32); 791 if (PHYS_ASI(asi)) { 792 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; " 793 " rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; " 794 " wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" : 795 "=&r" (_loc_hi), "=&r" (_pstate) : 796 "r" ((int)(value)), "r" ((unsigned long)(loc)), 797 "r" (_loc_hi), "r" (asi) : "memory"); 798 } else { 799 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 800 " or %2,%0,%0; sta %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) : 801 "r" ((int)(value)), "r" ((unsigned long)(loc)), 802 "r" (_loc_hi), "r" (asi) : "memory"); 803 } 804 } 805 #endif 806 807 /* store 64-bit int to alternate address space */ 808 #ifdef __arch64__ 809 static __inline__ void 810 stda(paddr_t loc, int asi, u_int64_t value) 811 { 812 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi; " 813 " wr %%g0, 0x82, %%asi" : : 814 "r" ((long long)(value)), "r" ((unsigned long)(loc)), 815 "r" (asi) : "memory"); 816 } 817 #else 818 static __inline__ void 819 stda(paddr_t loc, int asi, u_int64_t value) 820 { 821 register int _loc_hi, _pstate; 822 823 _loc_hi = (((u_int64_t)loc)>>32); 824 if (PHYS_ASI(asi)) { 825 __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; " 826 " rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; " 827 " wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" : 828 "=&r" (_loc_hi), "=&r" (_pstate) : 829 "r" ((long long)(value)), "r" ((unsigned long)(loc)), 830 "r" (_loc_hi), "r" (asi) : "memory"); 831 } else { 832 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " 833 " or %2,%0,%0; stda %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : 834 "=&r" (_loc_hi) : 835 "r" ((long long)(value)), "r" ((unsigned long)(loc)), 836 "r" (_loc_hi), "r" (asi) : "memory"); 837 } 838 } 839 #endif 840 841 #ifdef __arch64__ 842 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 843 static __inline__ void 844 stxa(paddr_t loc, int asi, u_int64_t value) 845 { 846 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi; " 847 " wr %%g0, 0x82, %%asi" : : 848 "r" ((unsigned long)(value)), 849 "r" ((unsigned long)(loc)), "r" (asi) : "memory"); 850 } 851 #else 852 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 853 static __inline__ void 854 stxa(paddr_t loc, int asi, u_int64_t value) 855 { 856 int _stxa_lo, _stxa_hi, _loc_hi; 857 858 _stxa_lo = value; 859 _stxa_hi = ((u_int64_t)value)>>32; 860 _loc_hi = (((u_int64_t)(u_long)loc)>>32); 861 862 if (PHYS_ASI(asi)) { 863 __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; " 864 " sllx %6,32,%0; or %1,%3,%1; rdpr %%pstate,%2; or %0,%5,%0; " 865 " wrpr %2,8,%%pstate; stxa %1,[%0]%%asi; wrpr %2,0,%%pstate; " 866 " membar #Sync; wr %%g0, 0x82, %%asi" : 867 "=&r" (_loc_hi), "=&r" (_stxa_hi), 868 "=&r" ((int)(_stxa_lo)) : 869 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 870 "r" ((unsigned long)(loc)), "r" (_loc_hi), 871 "r" (asi) : "memory"); 872 } else { 873 __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " 874 " or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : 875 "=&r" (_loc_hi), "=&r" (_stxa_hi) : 876 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 877 "r" ((unsigned long)(loc)), "r" (_loc_hi), 878 "r" (asi) : "memory"); 879 } 880 } 881 #endif 882 883 #if 0 884 #ifdef __arch64__ 885 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 886 static __inline__ u_int64_t 887 casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue) 888 { 889 __asm __volatile("wr %3,%%g0,%%asi; casxa [%1]%%asi,%2,%0; " 890 " wr %%g0, 0x82, %%asi" : 891 "+r" (value) : 892 "r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi) : 893 "memory"); 894 return (value); 895 } 896 #else 897 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 898 static __inline__ u_int64_t 899 casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue) 900 { 901 int _casxa_lo, _casxa_hi, _loc_hi, _oval_hi; 902 903 _casxa_lo = value; 904 _casxa_hi = ((u_int64_t)value)>>32; 905 _oval_hi = ((u_int64_t)oldvalue)>>32; 906 _loc_hi = (((u_int64_t)(u_long)loc)>>32); 907 908 #ifdef __notyet 909 /* 910 * gcc cannot handle this since it thinks it has >10 asm operands. 911 */ 912 if (PHYS_ASI(asi)) { 913 __asm __volatile("wr %6,%%g0,%%asi; sllx %1,32,%1; rdpr %%pstate,%2; " 914 " sllx %0,32,%0; or %1,%2,%1; sllx %3,32,%3; or %0,%4,%0; or %3,%5,%3; " 915 " wrpr %2,8,%%pstate; casxa [%0]%%asi,%3,%1; wrpr %2,0,%%pstate; " 916 " andn %0,0x1f,%3; membar #Sync; " 917 " sll %1,0,%2; srax %1,32,%1; wr %%g0, 0x82, %%asi " : 918 "+r" (_loc_hi), "+r" (_casxa_hi), 919 "+r" (_casxa_lo), "+r" (_oval_hi) : 920 "r" ((unsigned long)(loc)), 921 "r" ((unsigned int)(oldvalue)), 922 "r" (asi)); 923 } else { 924 __asm __volatile("wr %7,%%g0,%%asi; sllx %1,32,%1; sllx %5,32,%0; " 925 " or %1,%2,%1; sllx %3,32,%2; or %0,%4,%0; or %2,%4,%2; " 926 " casxa [%0]%%asi,%2,%1; sll %1,0,%2; srax %o1,32,%o1; wr %%g0, 0x82, %%asi " : 927 "=&r" (_loc_hi), "+r" (_casxa_hi), "+r" (_casxa_lo) : 928 "r" ((int)(_oval_hi)), "r" ((int)(oldvalue)), 929 "r" ((unsigned long)(loc)), "r" (_loc_hi), 930 "r" (asi) : "memory"); 931 } 932 #endif 933 return (((u_int64_t)_casxa_hi<<32)|(u_int64_t)_casxa_lo); 934 } 935 #endif 936 #endif /* 0 */ 937 938 939 940 /* flush address from data cache */ 941 #define flush(loc) ({ \ 942 __asm __volatile("flush %0" : : \ 943 "r" ((unsigned long)(loc))); \ 944 }) 945 946 /* Flush a D$ line */ 947 #if 0 948 #define flushline(loc) ({ \ 949 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 950 membar_sync(); \ 951 }) 952 #else 953 #define flushline(loc) 954 #endif 955 956 /* The following two enable or disable the dcache in the LSU control register */ 957 #define dcenable() ({ \ 958 int res; \ 959 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 960 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 961 }) 962 #define dcdisable() ({ \ 963 int res; \ 964 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 965 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 966 }) 967 968 /* 969 * SPARC V9 memory barrier instructions. 970 */ 971 /* Make all stores complete before next store */ 972 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 973 /* Make all loads complete before next store */ 974 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 975 /* Make all stores complete before next load */ 976 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 977 /* Make all loads complete before next load */ 978 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 979 /* Complete all outstanding memory operations and exceptions */ 980 #define membar_sync() __asm __volatile("membar #Sync" : :) 981 /* Complete all outstanding memory operations */ 982 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 983 /* Complete all outstanding stores before any new loads */ 984 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 985 986 #ifdef __arch64__ 987 /* read 64-bit %tick register */ 988 #define tick() ({ \ 989 register u_long _tick_tmp; \ 990 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 991 _tick_tmp; \ 992 }) 993 #else 994 /* read 64-bit %tick register on 32-bit system */ 995 #define tick() ({ \ 996 register u_int _tick_hi = 0, _tick_lo = 0; \ 997 __asm __volatile("rdpr %%tick, %0; srl %0,0,%1; srlx %0,32,%0 " \ 998 : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ 999 (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ 1000 }) 1001 #endif 1002 1003 extern void next_tick __P((long)); 1004 #endif 1005
Indexes created Tue Sep 30 11:09:46 GMT 2025